Foundry WLSI Technology for Power Management System Integration

Transcription

1 1 Foundry WLSI Technology for Power Management System Integration Chuei-Tang Wang, Chih-Lin Chen, Jeng-Shien Hsieh, Victor C.Y. Chang, Douglas Yu R&D,TSMC Oct. 2016

2 2 Motivation Outline PMIC system integration trends Foundry WLSI technology Portfolio High Performance Computing System (HPC) on CoWoS VR on CoWoS Impact of Si interposer Mobile AP and PMIC System (MAPS) on InFO Power Delivery Network PVR on InFO Summary & Outlook

3 3 Motivation: High Efficiency Power Management System PMIC System Trend: System on PCB System on /Package Shared Voltage Per-core Voltage Control V dd Scaling Low PDN Impedance Needed Long Battery Life High Efficiency Voltage Regulator System on PCB System on /Package

4 Supply voltage Core 1 Core 2 Core 3 Core 2 Core 1 Supply voltage Core 1 Core 2 Core 3 Core 2 Core 1 4 Motivation: High Efficiency Power Management System Shared voltage Per-core voltage control 1V 0.9V 1V 0.8V 0.9V 0.8V t t V dd Scaling 0.74V Low PDN Impedance Long Battery Life High Efficiency VR Low Ohmic Loss V out Vout I I I out out 2 out R I Low Ohmic Loss R a h 0 Source: 2013 ITRS & JEDEC

5 5 System Integration from PCB to Package Benefits from System on Package PDN path: Long Short Discrete component number: Dozen Several Switching frequency: 10 MHz 100 MHz L: μh nh C: μf nf Form factor: Large Small

6 IO # to Substrate or PCB 6 TSMC WLSI Technology Platforms from low cost to high performance Heterogeneous Integration InFO Multi-chip integration 3D integration Smallest form factor Cost competitive InFO_PoP DRAM 1 2 Homogeneous Integration CoWoS High performance and bandwidth Multi-chip integration Flexible integration PKG Size (mm 2 ) * WLSI: Wafer Level System Integration

7 7 and VR(M) System Design on CoWoS System 1: VRM on board, on substrate (FCBGA) VRM PCB System 2: VRM on board, on Si interposer PCB VRM System 3: VR and on Si interposer VR PCB

8 8 1. and VR(M) System Design on CoWoS PDN 2. PDN VRM VRM 3. PDN VR System 1: VRM on board, on substrate PDN path: VRM PCB Substrate PDN L/W: PCB/50/5 mm, Substrate/12/4 mm PDN metal layer: PCB/2, Substrate/10 System 2: VRM on board, on Si interposer PDN path: VRM PCB Substrate Si Interposer PDN L/W: PCB/50/5 mm, Substrate/12/4 mm, Si interposer/12/4 mm PDN metal layer: PCB/2, Substrate/8, Si Interposer /2 System 3: VR and on Si interposer PDN path: VR Si Interposer and Substrate PDN L/W: Substrate/12/4 mm, Si interposer/12/4 mm PDN metal layer: Substrate/8, Si Interposer /2 FOM: PDN impedance, voltage drop and voltage variation

9 PDN Z ( ) PDN Z ( ) 9 PDN Impedance Reduction from Si Interposer 1. PDN VRM 2. PDN VRM 3. PDN VR VRM on board, on Substrate 2. VRM on board, on Si interposer VRM on board, on Si interposer 3. VR and on Si interposer Frequency (GHz) Interposer mitigates anti-resonance at high frequencies Frequency (GHz) Short interconnect reduces PDN impedance: DC and AC Numbers of De-cap to be decreased

10 Normalized voltage supply Normalized voltage supply 10 Si Interposer Reduces Voltage Drop and Voltage Variation 1. VRM on board, on substrate 2. VRM on board, on Si interposer 3. VR and on Si interposer 1. VRM on board, on substrate 2. VRM on board, on Si interposer 3. VR and on Si interposer 1x 1.03x 0.23x Time DC voltage drop 1x 0.8x 0.93x Time Voltage variation 2GHz switching freq.) The voltage drop and voltage variation from VR to PDN Impedance The VR and on Si interposer system DC voltage drop: 23% of VRM on board, on substrate system Voltage variation: 80% of VRM on board, on substrate system

11 PDN Z ( ) 11 Capacitance of Si Interposer Suppresses PDN Z Anti-Resonances Si conductivity 0 S/m Si conductivity 1 S/m Si conductivity 10 S/m Frequency (GHz) High conductivity Si interposer suppresses the anti-resonances High Si conductivity High TSV Liner capacitance More suppression of PDN Z anti-resonance VR Cross section of TSV and equivalent circuits P G P Cap 259pF Cap 507pF Effect of Si conductivity G Si Cu Liner

12 12 and VR(M) System Design on InFO for Mobile Products PVR Logic System 1: FC and PMIC System 1: FC and PMIC PDN path: VRM PCB Substrate PDN routing: in millimeter scale System 2: InFO and PMIC PDN path: VRM PCB InFO PDN routing: in millimeter scale System 3: InFO with partitioned VR (PVR) PDN path: VR InFO System 2: InFO and PMIC PDN routing: in micrometer scale InFO and FC PKG System 3: InFO with PVR FOM: PDN impedance, voltage drop, voltage variation, power response

13 13 Power Integrity PDN Impedance Calculation P G P G P Ground Power VR PCB PI: A measure for power supply stability; related to impedance of power distribution network (PDN) PDN impedance is Z R PDN 1 j L ( // ZVR) j C where Z VR is the impedance of voltage regulator. Z PDN R L C VR Low R & L in PDN Low Z PDN Better PI performance

14 14 Low PDN Impedance in InFO Package 170 μm 430 μm 3 RDLs InFO 4L Substrate FC 4 GHz PDN impedance: InFO_PoP is 16% of the FC_PoP. InFO_PoP: Substrate & C4 Bump eliminated and thin RDL Low PDN impedance High power stability

15 15 The PDN Impedance for the InFO + PVRs system Frequency PDN impedance InFO with PVRs InFO & PMIC FC & PMIC Resistance and Inductance InFO with PVRs system PDN impedance: 9% of FC & PMIC system Resistance: 17% of FC & PMIC system Inductance: 9% of FC & PMIC system

16 16 The Voltage Drop and Variation for the InFO + PVRs System Time DC voltage drop Time Voltage variation (ΔV) The voltage drop and voltage variation from VR to AP PDN Impedance The InFO with PVRs system DC voltage drop: 17% of FC & PMIC system Voltage variation: 25% of FC & PMIC system

17 17 Power Response for InFO + PVRs System Power on/off Probe for supply voltage PMIC PDN PKG Transient time: Time period for power on from 0 to 1 stable state The InFO with PVRs system Transient time: 11% of FC & PMIC system Time Dynamic power response

18 18 Summary of the PI Results System specifications PDN PDN Voltage drop Voltage variation System 1: VRM on board, on substrate (FCBGA) 1x 1x 1x 1x System 2: VRM on board, on Si interposer 1.01x 0.45x 1.03x 0.93x System 3: VR and on Si interposer 0.14x 0.27x 0.23x 0.8x System specifications Resistance Inductance Voltage variation Transient time InFO with PVRs 0.17x 0.09x 0.25x 0.11x InFO & PMIC 0.91x 0.63x 0.67x 1x FC & PMIC 1x 1x 1x 1x

19 19 Summary and Outlooks Foundry WLSI technology, CoWoS and InFO, provides leading edge solutions for power management system integration. The technologies provide excellent PDN performance for low power consumption, low voltage drop and low voltage variation for system design. V dd scaling of leads to power system design challenges TSMC WLSI technology provides the design solution.

20 20 Thanks for your attention!