Microelectronic sensors for impedance measurements and analysis

Transcription

1 Microelectronic sensors for impedance measurements and analysis Ph.D in Electronics, Computer Science and Telecommunications Ph.D Student: Roberto Cardu Ph.D Tutor: Prof. Roberto Guerrieri

2 Summary 3D integration Overview Capacitive coupling interconnections Modeling and characterization of capacitive interconnections Wireless wafer probing Overview Design of I/O pads for wireless probing Functional Brain Imaging Overview EEG and EIT Design and preliminary testing of active electrodes

3 3D integration More-than-Moore trend Several 3D approaches allow to stack multiple chips Ohmic (TSVs, wire bonding, bumps) Wireless (inductive or capacitive coupling) Pros Shorter interconnections Reduced footprints Reduced volume Heterogeneous integration Cons Increased system design complexity Increased manufacturing costs

4 3D interconnections landscape Capacitive Inductive Technological complexity Through Via Micro-Bump Wire-Bond Interconnection pitch

5 Capacitive coupling interconnections Tx C 3D C TX C RX Rx Chip 2 Chip 1 Inter-chip dielectric

6 Modeling and characterization Complex physical structure (many dielectric and metal layers) Channel performance related to layout choices Multiple channels can be simultaneously switching and introducing crosstalk Capacitive network C3D Crosstalk capacitances Substrate capacitances TX1 RX1 TX2 RX2 TX3 RX3

7 Design space exploration Place capacitive interconnections as macro blocks Layout and manufactory choices: Number of lines and columns (i.e. 3x1, 3x3) Electrodes Spacing (S) Electrodes Widths (W) Dielectric properties Thickness Permittivity

8 Standard characterization flow Standard flow: Parasitic extraction tools + external EM simulator (FEM) Solutions are not independent error in superposition FEM simulator is not integrated with IC design tools Long design space exploration time

9 Proposed characterization flow Characterization of capacitive coupling interconnections through the use of standard CAD tools Shorter design space exploration time (electrodes widths and spacing, inter-chip dielectric properties...) Chip 1 Inter-chip dielectric 3D structure generator Chip 2 Placement as any standard macro in a digital design flow EM Extractor

10 Wireless wafer probing Current approach open issues: Testing costs (Wafer test time, Tester capability) Yield (Contact between pad and probe, pad damaging) New non-contact approach benefits: Eliminates probe and pad damage Yield improvement Increases test speed and increases test parallelism Faster Test time Enables Full Wafer Test Enables test cost reduction Better KGD Higher Test coverage Wireless Probe Card Antenna TX/RX

11 Test-chip for wireless capacitive probing 16 Different Test Structures & 9 Transceiver Design Topology Every Test Structure comprises 10 PADs: Where C (contact) W (wireless) W C C/W C C Vdd_core Gnd_core Vdde Gnde Vssub µm Pad open metallization for contact 38 µm 975 µm µm 63 µm 131µm

12 Chip floorplan o PAD Wireless Stand Alone PAD fly placed in the core chip Test internal node Minimum parasitic capacitance Chip FloorPlan o PAD Wireless Stand Alone with Ring Integrated in the pad-frame Only wireless testing o PAD I/O Standard & Wireless Integrated in the pad-frame Standard I/O PAD & Wireless Standard Input & Output Wireless Input & Output Test Block

13 Wireless probing setup Probe Station Cascade Summit Cascade Adaptor 3 Probe cards from TechnoProbe One with a wireless electrode One with two wireless electrodes One for crosstalk analysis

14 Wireless probing setup

15 Preliminary experimental results Wireless input on pad 1 Standard output on pad 2 Input 1MHz Output Input

16 Functional Brain Imaging Measure an aspect of brain function to understand the relationship between activity in certain brain areas and specific mental functions Cognitive neurosciences Medicine (epilepsy, Parkinson s...) Technologies:... Positron Emission Tomography (PET) functional Magnetic Resonance Imaging (fmri) multichannel electroencephalography (EEG) magnetoencephalography (MEG) Electrical Impedance Tomography (EIT)

17 Electroencephalography (EEG) First recording by German psychiatrist Hans Berger in Recording of electrical activity along the scalp produced by the firing of neurons within the brain. Spontaneous activity is confined at low frequencies (0.5 to 100Hz approx.); amplitude is about 100µV when measured on the scalp, 1mV on brain surface.

18 Electrical Impedance Tomography (EIT) First reported use: geological studies in 1930s. Process of estimating internal admittivity of a body from known currents and voltages at the surface. Impedance variations can occur as result of changes in blood volumes due to activation of some regions Inject currents on body surface (10kHz-1MHz) Measure voltages on the body surface Try to infer internal conductivity from boundary data

19 Simultaneous EEG, EIT and ESI Currently no combined solutions exist to measure EEG and EIT simultaneously. EIT can possibly provide complementary information since the physical principle observed is correlated but different from that of EEG EIT might help give a-priori information for the EEG source localization problem Continuous Electrode Skin Impedance (ESI) monitoring based on injection of AC test currents between adjacent electrodes and the measurement of the corresponding AC differential voltage to improve quality of acquisition.

20 Active electrode IC CMOS 0.35µm Read-Out Circuitry 8mm 6mm

21 Read-out circuitry Power supply and output signals share a single wire. EEG, EIT and ESI signals share the same output line. EEG signal is DSB mixed at central frequency 2kHz. EIT signal is down-converted at 4kHz. Electrode read-out measured performance: Input referred noise EEG ( Hz) = 0.6µVrms Input impedance > 100 MΩ Electrode offset = 50 mv Area 0.56 mm 2 Power consumption 1mW CMRR = 63 db

22 Patents and Publications Patents 2 pending patents related to wireless probing in collaboration with STMicroelectronics. Publications M. Scandiuzzo, R. Cardu, S. Cani, S. Spolzino, L. Perugini, E. Franchi, R. Canegallo, R. Guerrieri. 3D System on Chip Memory Interface Based on Modeled Capacitive Coupling Interconnections. To be presented at IEEE International Conference on 3D System Integration (3D IC), November R. Cardu, M. Scandiuzzo, S. Cani, L. Perugini, S. Spolzino, E. Franchi, R. Canegallo, R. Guerrieri. Characterization of Chip-to-Chip Wireless Interconnections Based on Capacitive Coupling. IEEE VLSI-SoC 2010, September R. Cardu, M. Scandiuzzo, S. Cani, L. Perugini, E. Franchi, R. Canegallo, R. Guerrieri. Chip-to-Chip Communication Based on Capacitive Coupling. IEEE International Conference on 3D System Integration (3D IC), September M. Scandiuzzo, L. Perugini, R. Cardu, M. Innocenti, R. Canegallo. 3D Integration with AC Coupling for Wafer-Level Assembly. European Microelectronics and Packaging Conference, June 2009.