A DRY ELECTRODE LOW POWER CMOS EEG ACQUISITION SOC FOR SEIZURE DETECTION

Transcription

1 A DRY ELECTRODE LOW POWER CMOS EEG ACQUISITION SOC FOR SEIZURE DETECTION TEAM 6: MATTHIEU DURBEC, VALENTIN BERANGER, KARIM ELOUELDRHIRI ECE 6414 SPRING 2017

2 OUTLINE Project motivation Design overview Body-Electrode Interface Voltage references Chopper Stabilized LNA Low Pass filter ADC Driver SAR-ADC Conclusion

3 PROJECT MOTIVATION Epilepsy neurological disorder Abnormal firing in a group of neurons Clinical onset: Loss of coherence/cognition Loss of motor control Convulsions Objective: sense these signals and establish correlation with clinical onset Use of machine learning techniques and training to patient-specific data

4 DESIGN OVERVIEW Multi Channel EEG Acquisition system Wireless low power chip Digitized EEG signals transmitted for processing Machine learning algorithm for processing channel signals IC design specifications

5 BODY-ELECTRODE INTERFACE Dry-electrode model: Gel free solution Increased impedance in the skin-electrode interface Circuit model: Resistor : body Resistor & Capacitance: Stratum Corneum Electrode offset voltage (EOV): mV EEG Signals: μv EEG frequency range: Hz

6 Chopper-stabilized LNA A chopper stabilized amplifier system consists of modulating and demodulating carriers with period T= 1/fchop, where fchop is the chopper frequency. DC servo loop uses for high pass filter and cancel residual offset Chopping reduces the DC input impedance of the sensing front-end. The low input impedance can result in attenuation of the weak input signals and degradation in noise performance

7 A fully differential chopper amplifier Chopping -> reduces the flicker noise Upmodulated flicker noise and offset show up as ripples at the output of the amplifier Sol :a parallel-rc impedance is added immediately after the 1st stage.

8 DC servo loop The EEG signal bandwidth is in the range Hz Pseudo-resistor larger than 100 GΩ in the feedback loop. Proccess variations (factor of 100). Duty-cycled resistors to enable high linearity and reliability

9 Impedance boosting Chopping reduces the DC input impedance of the sensing front-end -> Impedance boosting. Auxialiary path

10 Impedance boosting The auxiliary-path used charges the input caps Cin at the beginning of every chopping phase using aux-buffers reducing the charge provided by the input voltage, thus boosting Zin.

11 Impedance boosting Vin provides zero charge -> Problem : Amplification of aux-buffer offset and flicker noise

12 Impedance boosting Sol: Voff is up-modulated to fc/4 by using mixers M1 and M2 Voff creates a benign ripple instead of a DC offset. Storage capacitors Caux=8pF assist the aux-buffers at the beginning of the pre-charge phase. Higher input impedance without increasing power consumption

13 Results

14 Results Metrics Target Specification Voltage Supply 3.1V Power consumption 67µW Gain 43.5dB BW 0.5Hz-10kHz CMRR 55dB Input impedance Input-referred noise 0.75µVRMS (1-200Hz) 5.27µVRMS(200-10kHz) Ripple rejection yes Process 0.6 um

15 VOLTAGE REFERENCES: BGR Power supply: 3.7V Rechargeable Polymer Li-Ion battery Tenergy model PL Bandgap Reference Circuit: Constant Vref independent of temperature swings CTAT, PTAT and Start-up circuit Generated Vref: 3.14V at Vdd

16 VOLTAGE REFERENCES: BGR

17 VOLTAGE REFERENCES: REGULATOR Voltage Regulator: Ensures constant voltage across the system Negative feedback control loop Supplies reference voltage to the entire chip Output of the regulator 95% the voltage reference generated by BGR

18 VOLTAGE REFERENCES: REGULATOR

19 VOLTAGE REFERENCES: REGULATOR

20 LOW PASS FILTER Fully differential topology with common mode feedback and gain enhancement Provide frequency cut off for EEG signals and gain Low pass filter specifications

21 LOW PASS FILTER

22 ADC DRIVER Drive capacitance sample & hold of the ADC Fully differential amplifier with common mode feedback and gain enhancement Additional gain to reach the ADC dynamic range ADC Driver specifications

23 ADC DRIVER

24 ADC DRIVER

25 SAR ADC Design 12-bit successive approximation register converter 6-bit main-dac and 6-bit sub-dac architecture, both implemented as passive charge-redistribution capacitor arrays, providing an inherent sample and hold function Energy per conversion down to very low speeds (i.e., around 600 S/s)

26 SAR ADC Operation Principle Three steps: purging, auto-zeroing and sampling Management of clocking is crucial in this design Use of a consequent number of switches

27 Digital to Analog Converter (DAC) Charge scaling DAC Unit capacitance - 500fF Importance of transmission gate

28 Successive Approximation Register

29 Specifications

30 CONCLUSION Comparison with State of the Art

31 REFERENCES [1] N. Verma, A. Shoeb, J. Bohorquez, J. Dawson, J. Guttag and A P. Chandrakasan, A Micro Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System, IEEE journal of solid-state circuits, vol.45, no. 4, April [2] S. Lim, C. Seok, H. Kim, H. Song and H. Ko, A Fully Integrated EEG Analog Front-End IC with Capacitive Input Impedance Boosting Loop, IEEE Custom Integrated Circuits Conference (CICC), [3] YM. Chi, T-P Jung, G Cauwenberghs, Dry-contact and Noncontact Biopotential Electrodes: Methodological Review, IEEE Reviews in Biomedical Engineering, vol. 3, [4] A. Bragin I. Fried R. J. Staba, C. L.Wilson and Jr J. Engel, Quantitative analysis of high-frequency oscillations (80500 hz) recorded in human epileptic hippocampus and entorhinal cortex, J. Neurophysiol., vol. 88, pp , [5] F. Shahrokhi, K. Abdelhalim, D. Serletis, P.L. Carlen, and R. Genov, The 128-channel fully differential digital integrated neural recording and stimulation interface, Biomedical Circuits and Systems, IEEE Transactions on, vol. 4, no. 3, pp , June [6] N.Verma and A.P.Chandrakasan, An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes, IEEE J. Solid- State Circuits, vol. 42, no. 6, pp , Jun [7] G. Promitzer, 12-bit low-power fully differential noncalibrating successive approximation ADC with 1 MS/s, IEEE J. Solid-State Circuits, vol. 36, no. 7, pp , Jul [8] T. Denison, et al., A 2 μw 100 nv/rthz chopper-stabilized instrumentation amplifier for chronic measurement of neural field potentials, IEEE J.Solid-State Circuits, vol. 42, no. 12, pp , Dec [9] R. Jacob Baker, CMOS Circuit Design, Layout, and Simulation, 3rd Edition, IEEE Press Series on Microelectronic Systems, [10] Q. Fan, F. Sebastiano, J. H. Huijsing, and K. A. A. Makinwa,, A 1.8 μw60 nv/ Hz capacitively-coupled chopper instrumentation amplifier in 65 nm CMOS for wireless sensor nodes, IEEE J. Solid-State Circuits, vol. 46, no. 7, pp , Jul [11] J. Xu et al., A 160 μw 8-channel active electrode system for EEG monitoring, IEEE Trans. Biomed. Circuits Syst., vol. 5, no. 6, pp , Dec [12] H. Chandrakumar et.al, A Simple Area-Efficient Ripple-Rejection Technique for Chopped Biosignal Amplifiers, IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 62, no. 2, pp , Feb [13] H. Chandrakumar, et al., A 2μW 40mVpp Linear-Input-Range Chopper-Stabilized Bio-Signal Amplifier with Boosted Input Impedance of 300MΩ and Electrode-Offset Filtering, ISSCC, pp , Feb [14] H. Chandrakumar, et al., 2.8μW 80mVpp-Linear-Input-Range 1.6GΩ-Input Impedance Bio-Signal Chopper Amplifier Tolerant to Common-Mode Interference up to 650mVpp IEEE International Solid-State Circuits Conference (ISSCC) 2017

32 Thank you for your attention Do you have any questions?