ISSCC 2003 / SESSION 20 / WIRELESS LOCAL AREA NETWORKING / PAPER 20.5

Transcription

1 ISSCC 2003 / SESSION 20 / WIRELESS LOCAL AREA NETWORKING / PAPER A 2.4GHz CMOS Transceiver and Baseband Processor Chipset for b Wireless LAN Application George Chien, Weishi Feng, Yungping Alvin Hsu, Lawrence Tse Marvell Semiconductor, Sunnyvale, CA This paper describes a complete PHY chipset that consists of a fully integrated CMOS transceiver and a baseband processor (BBP) and complies with the IEEE b Wireless Local Area Network (WLAN) standard. Figure shows a block diagram of the CMOS transceiver that employs the superheterodyne architecture. The RF LO generates a channel-selecting frequency to down-convert the received signal to the IF. After IF filtering, the desired signal is amplified before down-conversion to baseband. By performing amplification and filtering at the IF, large off-chip passive LC filters are avoided in the baseband, and the DC offset problem found in other architectures is alleviated. In the TX path, the baseband signal is up-converted in two steps. Unlike a direct conversion topology, separation of the two LO frequencies minimizes VCO pulling by the power amplifier (PA) and allows integration of an on-chip PA with power control loop. In the RX path, the LNA is a differential common-source amplifier with cascode transistors to maximize reverse isolation, and inductor degeneration to achieve the real-part impedance matching. In order to meet the maximum signal requirement of 4dBm, the LNA incorporates two gain settings which are determined by a peak detector in the IF stage. In low-gain mode, a separate input transistor is biased in the high over-drive region to achieve attenuation and a high 1dB compression point. The RF mixer uses an open-drain double-balanced Gilbert cell multiplier. To maintain a high IP3 in the RX path, the mixer input stage uses a combination of saturation and triode devices [2] (Fig ). The triode device compliments the saturation device and effectively extends the linear range of the input gm stage. The dynamic range of b dictates a gain range of 74dB in the IF stage and is controlled by the BBP. To achieve high gain and IF bandwidth simultaneously, a transimpedance amplifier is used. The IF mixer is a Gilbert cell multiplier with resistor degeneration. An anti-alias LPF is implemented with a simplified biquad, followed by a fixed gain stage to maximize ADC dynamic range. A 6b offset cancellation DAC eliminates the DC offset due to LO self-mixing and baseband mismatch. The corner frequency of the LPF is calibrated to 8.5MHz to guard against RC variations in the process [3]. In the TX path, the modulated baseband I and Q signals are lowpass filtered before being applied to the IF mixer. In order to minimize LO leakage, the TX path between the baseband and IF mixer is calibrated to remove the DC offset. The TX IF mixer uses resistor degeneration in conjunction with op-amp feedback to boost the linearity of the input stage. During the calibration mode, the inputs are effectively zeroed, and the switching pairs in the mixers are disabled (Fig ). To compensate for external component variations, a fair amount of gain range is designed into the IF gain stage and the PA predriver stage. The IF gain stage is similar to the RX path, and the differential-to-single-ended conversion of mixer outputs is implemented with an on-chip transformer. The PA pre-driver accepts the single-ended signal input and is capable of driving up to 0dBm output to the on-chip or optional external PA. The on-chip PA is a fully-differential three-stage amplifier; each stage can be independently controlled for optimal power consumption and linearity. The first two stages of the PA incorporate on-chip inductors to resonate the load capacitance of the next stage. Cascode transistors are used to ensure device reliability. The third stage consists of open-drain devices that drive external matching networks. To ensure constant output power over process and external component variation, a power control loop adjusts the output level to match a pre-defined reference. Channel selection is performed with the RF LO, and its frequency varies from 2038MHz to 2110MHz. The varactors used in the fully differential VCO s are implemented with NMOS in n-well accumulation mode devices, and the inductor is a cross-coupled differential inductor. The synthesizer phase-locks the VCO frequency to a 1MHz reference and achieves a phase noise of 110dBc/Hz at a 1MHz offset. Figure shows a block diagram of the BBP. In addition to the mandatory modes, the BBP supports a 22Mb/s mode using uncoded DQPSK operating at 11Mbaud/s. The modulated chip-rate Tx signal is up-sampled by eight times and interpolated through 2 Tx LPF's to meet the spectral mask requirement and relax the LPF after the DAC. Two 9b 88MS/s current DAC s transmit the complex baseband signal to the transceiver IC to be up-converted. The BBP receiver digitizes the I/Q baseband signal from the transceiver IC with two 6b ADC s. The ADC and the following digital LPF operate at 44MS/s to provide additional adjacent channel rejection. In preamble/header and 1Mb/s and 2Mb/s modes, the signal is processed by a Barker de-spreader to provide processing gain. To combat multipath and maximize SNR, an adaptive RAKE filter is employed before the symbol detector. For high data rate signals (5.5, 11 and 22Mbps), a decision feedback equalizer (DFE) is used. Each tap in both feed-forward and feedback filters is made adaptive using a signed-lms algorithm. The adaptation begins in preamble and continues throughout the packet using decision-directed error from the RAKE and CCK outputs. Figure shows the measured constellation before and after equalization under the JTC [4] indoor commercial B channel model. For 5.5 and 11Mb/s signals, the CCK demodulator correlates the equalized CCK symbol with the 4/64 CCK vectors, respectively. The magnitude of the correlation is generated by sum-of-absolutes instead of sum-of-squares. The RX achieves 150ns RMS delay spread under an exponential channel model. For 22Mb/s data signals, the equalized signal bypasses CCK and is demodulated by DQPSK. The BBP also supports various control loops including AGC, carrier recovery, and symbol timing recovery. The carrier loop is designed to compensate for up to 100ppm frequency offset between TX and RX. The BBP features packet-based antenna selection diversity. The RX constantly scans between the two antennas until it detects the presence of the b signal. After measuring the SNR and signal quality of both antennas, one of them will be selected. This selection process finishes in less than 20µs. RX diversity typically provides an additional 2~3dB gain in SNR. In TX mode, the antenna can be set to one of the antennas or to track the RX selection. The PHY chipset fully complies with the IEEE b WLAN standard. Typical measured performance is summarized in Fig The transceiver and BBP are implemented in 0.25µm and 0.15µm CMOS technology with die areas of 16 mm 2 and 3.1mm 2 respectively. Both IC s are packaged in leadless QFN packages, and the die micrographs are shown in Fig References [1] Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: Higher-speed Physical Layer Extension in the 2.4 GHz band, IEEE Std b. [2] S. Tanaka, F. Behbahani, A. A. Abidi, A Linearization Technique For CMOS RF Power Amplifiers, Digest of the 1997 Symposium on VLSI Circuits. [3] P. Roo, S. Sutardja, S. Wei, F. Aram, Y. Cheng, A CMOS Transceiver Analog Front-End for Gigabit Ethernet over CAT-5 Cables, ISSCC Digest of Technical Papers, vol. 44, pp. 310, Feb, [4] JTC Technical Report on RF Channel Characterization and Deployment Modeling, Air Interface Standards, Sep

2 ISSCC 2003 / February 12, 2003 / Salon 9 / 10:45 AM Figure : Block diagram of the complete PHY chipset for IEEE b. OUTP OUTN EXTERNAL VDD VDD From BBP RL1 RL2 DAC OUT LO LO_IN M1 VB1 VB2 INP M1 M2 INN R1 R2 R3 R4 M2 Figure : RX RF mixer schematic. Figure : TX baseband offset cancellation. 20 Figure : Basaeband processor architecture.

3 Figure : Measured equalizer performance (corrupted constellation, eye diagram, spectrum and equalized signal). Figure : Performance summary. Figure : (a) RF-based transceiver; (b) baseband processor/modem. 20

4 Figure : Block diagram of the complete PHY chipset for IEEE b.

5 OUTP OUTN EXTERNAL VDD LO_IN VB1 VB2 INP M1 M2 INN Figure : RX RF mixer schematic.

6 VDD From BBP RL1 RL2 DAC OUT LO M1 R1 R2 M2 R3 R4 Figure : TX baseband offset cancellation.

7 Figure : Basaeband processor architecture.

8 Figure : Measured equalizer performance (corrupted constellation, eye diagram, spectrum and equalized signal).

9 Figure : Performance summary.

10 Figure : (a) RF-based transceiver; (b) baseband processor/modem.