A Highly Integrated Dual Band Receiver IC for DAB

Transcription

1 A Highly Integrated Dual Band Receiver IC for DAB 陳彥宏 Yen-Horng Chen High Frequency IC Design Dept. Abstract A dual band receiver IC for Digital Audio Broadcasting (DAB) is described in this paper. The chip integrates most of the functions necessary to receive and down convert DAB L-Band (1452~ 1492MHz) and Band3 (174~240MHz) signals for further baseband processing, including two variable gain LNAs, mixers, VGA, IF amplifiers, L-Band PLL, and Band3 VCO. The overall Band3 receiver gain is 92dB and NF is 4.5dB. L-Band receiver gain is 91dB and NF is 8.9dB. In both bands, gain control ranges are over 84dB and THD remains above 30dBc up to input levels of 14dBm. The linearity and dynamic range of this system can be improved by using an external attenuator that has 20dB variable attenuation. Two AGC stages are implemented in this receiver. With the novel reference-current-based, programmable AGC design, this receiver provides 8dB range to optimize output level to match the dynamic range of the following A/D converter. The prescalar used in L-Band PLL realizes a programmable divide - by-multi-divisor function, 2 n -2, 2 n -1, 2 n, and 2 n +1, by utilizing conventional divide-by-4/5 stage with slow and simple logic timing. This circuit was fabricated in TSMC 0.35µm SiGe process with 3.3V power supply. It consumes 88mA and 65mA for L-Band and Band3 mode, respectively. 1. Introduction Digital Audio Broadcasting (DAB) developed by the EUREKA-147 project [1] has already been introduced as the digital standard for audio broadcasting and used successfully around the world. It was designed to be a reliable digital broadcasting system aimed at mobile fixed and portable receivers. The DAB system uses multi-carrier transmission technology, COFDM, which disperses the information to a large number of differential-qpsk modulated carriers with an aggregate bandwidth of 1.536MHz. Combining this frequency dispersal with time interleaving, guard intervals and digital audio compression technique (MPEG layer II), the reception and audio signal quality can be improved. It will be capable of transmitting 6 CD-quality stereo programs simultaneously, and the signal can carry data as well. The DAB system is revolutionary in moving from analog broadcasting to digital radio, while adding flexibility and robustness in wireless broadcasting. DAB receivers have been developed for many years, however, most of the previous designs have less integration and large power consumption [2]-[4]. The chip presented in this paper integrates most of the functions necessary to receive and down convert DAB L-Band (1452 ~ 1492MHz) and 108 系統晶片 002 期

2 Band3 (174 ~ 240MHz) signals for further baseband processing. The circuit was implemented using TSMC 0.35µm SiGe process with 3.3V power supply. It consumes 88mA and 65mA for L-Band and Band3 operation, respectively. In this paper, section 2 and section 3 describe the receiver architecture and the building blocks design in detail, respectively. Die photograph and the measured results are given in section 4, and section 5 summarizes this work. 2. DAB Receiver Architecture Fig. 1 demonstrates the configuration used in this DAB receiver design. RF signal from the antenna is divided in frequency domain by duplexer (DUP) into two separate channels. They are then filtered by external bandpass filters to achieve the necessary image rejection for later down mixing. Output from the filter drives separate on-chip variable gain LNAs and the following filters. The on-chip L-Band mixer converts the L-Band signal down to a frequency within Band3 frequency range. The required LO signal is provided by L-Band PLL. The following IF mixer converts either L-Band or Band3 signal down to IF frequency of MHz. The LO signal comes from on-chip Band3 VCO. After the IF mixer, the two band paths share a single receiver chain, including IF amplifier (AMP1), variable gain amplifier (VGA), IF buffer amplifier (AMP2), channel selective and noise rejection filters. The IF amplifier (AMP1) is followed by an external filter which provides the ultimate selectivity of the radio frequency parts of the receiver. The variable gain amplifier (VGA) provides the necessary gain and dynamic range of this receiver. The IF buffer amplifier (AMP2) is the last stage of the analog receiver. It provides an additional gain to produce a high-level output and drives the following circuits. The signal path of this receiver comprises two AGC stages, RF and IF AGC. Detector (D1) with an external attenuator (ATN), L-Band LNA and mixer or Band3 LNA provides RF AGC function. Detector (D2) with VGA and AMP2 provides IF AGC function. 3. Building Blocks Design 3.1 Variable Gain LNAs Design The L-Band and Band3 variable gain LNAs are Fig. 1 DAB receiver configuration SoC Technical Journal 109

3 common emitter transconductance stages that use current steering method to accomplish the necessary gain range of each band. Single-ended rather than differential designs are used to achieve minimum NF and minimize the number of external components. The simplified schematic of variable gain LNAs, for both bands, is shown in Fig. 2(a). Parallel connected transistor in cascode diverts RF signal away from the load, resulting in continuous variable gain. Transistor Q 1 is biased using a current mirror concept (Q 1 -Q 2 ). Additional resistors (R 1, R 2 ) are added to increase the input impedance seen from Q 2 towards the bias circuit. 3.2 Mixer Design 3.3 IF Amplifier (AMP1) Design Because AMP1 directly drives a filter with a large in-band loss, in order to maintain a good noise performance of the receiver, it must have high gain and low noise figure. Fig. 3(a) is the simplified schematic of AMP1. Single-ended design is used because of its better NF performance. It is a common emitter stage with external emitter degeneration inductor L 1. Transistor Q 1 is the input transistor and the external LC tank is tuned to MHz. This amplifier is designed with approximately 23dB of power gain while maintaining match at the input and output of 50Ω. A double-balanced Gilbert mixer topology is used for L-Band and IF mixers (Fig. 2(b)). The mixers employ bipolar inputs with degeneration resistors to improve linearity. In IF mixer design, the two band paths have separate input stages respectively and share a single switching pairs to down convert the RF current. The output of mixer consists of an inductor in parallel with a capacitor that are used to reject the undesired signals. Fig. 3 Simplified schematic of (a) AMP1 and (b) AMP2 3.4 IF Variable Gain Amplifier Design Fig. 2 Simplified schematic of (a) variable gain LNA and (b) mixer A classical Gilbert-quad based on current steering is used for VGA design, as shown in Fig. 4. It consists of three-stage Gilbert-quad amplifiers, a gain control block that provides the voltage transformation function, and a fixed gain amplifier that enhances the overall gain. The gain versus control voltage of this VGA is expressed as [5] A R V = BGR C V gmr L R 3 VBGR From the above expression, by choosing R 系統晶片 002 期

4 and R BGR as the same type, the gain of this VGA is insensitive to process and temperature. The three stages of Gilbert-quad amplifiers together with a fixed gain cascode amplifier is designed with the highest gain of 60dB and more than 60 db gain range as V C varies from 0.18 to 2V. Fig. 4 Simplified schematic of VGA accurate gain function against the unideal process variation. 3.6 Detector and Programmable AGC Fig. 5 shows the architecture of the RF and IF AGC implemented in the DAB receiver. It is composed of a forward path and a feedback path. In the forward path, LNA & attenuator or VGA is controlled by a feedback dc signal (V C ) to provide a necessary gain range that fulfills the system dynamic range. The subsequent mixers or AMP2 provides not only an additional gain but also the amplitude information that is used to set the AGC loop. The feedback path includes two main components, detector and loop filter. The detector extracts the output amplitude information, which compares with a reference set point and the loop filter integrates their difference to obtain the control signal V C. 3.5 IF Buffer Amplifier (AMP2) Design AMP2 is the last stage of the analog receiver. It has to provide an adequate voltage swing to the following signal processing blocks, so high linearity and low distortion is needed. An amplifier structure that combines the concepts of device match and current amplification techniques, as shown in Fig. 3(b), is used to implement this circuit. The input transconductance stage with emitter degeneration resistor, two-stage current amplifier contains two current mirror pairs and the current-to-voltage converted resistor provides an Fig. 5 AGC architecture The RF and IF AGC are designed with a novel reference-current-based, programmable structure. Fig. 6 shows the block diagram. In conventional feedback path [6], detector extracts AGC output. The control voltage is obtained from the integration of the difference between V det and a reference voltage. In our feedback path, the AGC output is SoC Technical Journal 111

5 also extracted by a detector. This detector, including a full-wave rectifier, a level shift amplifier and a V/I converter, will generate an output DC current I 1 that is proportional to input AC signal. The reference current I 2 decides the AGC output setting amplitude. When I 2 is higher than I 1, the output level is smaller than the required one. In this case, current I 2 -I 1 will charge the capacitor, and then the control voltage increases, and with the gain of VGA and AGC output level, and vice versa. When the output level is equal to the leveled value, there will be no current charge or discharge this capacitor, so V C and the gain of VGA hold constant. The AGC has a fixed and stable output. It is easy to program this reference current, and with a proper design of V/I converter and the reference current, the symmetric topology can minimize the effect of process variation. Hence, a programmable and steady AGC can be achieved. multiplier (transistors Q 14 -Q 19 ) with a simple one-pole RC (R P and C P ) low-pass filter is used as a full-wave rectifier here. The rectifier signal is provided by a single-ended to differential amplifier and emitter followers (transistors Q 12 and Q 13 ). The level shift amplifier is a shunt-shunt feedback stage with a gain setting by R 7 / R 6 and it also provides the differential to single-ended conversion. A resistor (R 8 ), operational amplifier (OP2) and transistor (M 5 ) form the voltage to current converter. The output current (I 1 ) is proportional to the input signal divided by R 8. Fig. 7 Simplified schematic of the AGC feedback path Fig. 6 AGC feedback path. (a) Conventional AGC feedback path (b) Proposed AGC feedback path Fig. 7 is the simplified schematic of the AGC feedback path. The detector is composed of a full-wave rectifier, a level shift amplifier and a voltage to current converter. A Gilbert type The reference current (I 2 ) is generated by a bandgap reference voltage (V BGR ) divided by a resistor (R ref ) and a current mirror array (M 6 -M 10 ). With the combination of currents in the current mirror array, a reference current proportional to V BGR / R ref can be achieved. By choosing resistors R 8 and R ref as the same type, the effect of process variation on AGC output level setting can be minimized. In addition, other current mirrors (M 11 -M 12 and M 13 -M 14 ) are used to set the directions of I 1 and I 2 in order to ensure a negative 112 系統晶片 002 期

6 Fig. 8 Simulink simulation of the close loop AGC feedback loop. The loop filter is implemented using a capacitor (C 1 ). By carefully selecting the capacitor value, system time constant can be selected to optimize performance. Fig. 8 is the Simulink simulation of the close loop AGC. The output is constant with low and high input signal level. 3.7 Prescalar Design Fig. 9 Timing diagram of prescalar According to the frequency plan, L-Band PLL requires it to generate a LO signal at GHz feeding L-Band mixer. It can be accomplished by a divide-by-31 prescalar followed by a divide-by-640 stage with a reference clock of 64kHz. In avoiding tight logic timing and complex control in prescalar design, a conventional divide-by-4/5 core divider is utilized. As shown in the timing diagram Fig. 9, the trigger edge changes once the 30/31 th clock is counted, and the logics used to set divide-by-4/5 and invert the trigger edge only come from relatively slower signals than the divided signal. The edge-trigger-inverting function can also be bypassed to realize divide-by-32/33, and then achieve a divide-by-2 n -2, 2 n -1, 2 n, 2 n +1 multidivisor prescalar. This prescalar can work well up to the frequency of 1.5GHz. 4. Measured Performance The circuit was fabricated in TSMC 0.35μm SiGe process and packaged in plastic TQFP package. Fig. 10 is the die photograph. The detail-measured results are summarized in Table 1. The receiver gain control is distributed in LNAs and VGA, and an external attenuator provides extra 20dB variable attenuation that can extend the receiver dynamic range and alleviate the system linearity requirement. The measured dynamic responses of this IC are shown in Fig. 11. Band3 and L-Band receiver gain and NF are 92dB and 4.5dB, 91dB and 8.9dB. In both bands, gain control ranges are over 84dB and THD remains above 30dBc up to input levels of 14dBm. The NF SoC Technical Journal 113

7 degrades less than 1dB for 1dB gain reduction, insuring an improving C/N ratio as the input power increases. Besides, this receiver has a programmable output based on the design of reference-current-based, programmable AGC. This capability provides 8dB range to optimize output level to match the dynamic range of the following A/D converter. Fig. 10 Die photograph Table 1 Summary of Measurement Complete Receiver (wo external attenuator) Previous Work L-Band Band3 [2]* [3]** Conversion Gain 91dB 92dB 88dB 91dB Variable Gain range 84dB 94dB 87.4dB 106dB NF (max. gain) 8.9dB 4.5dB 6dB 9.5dB/12dB Power Consumption 290mW (88mA) 214mW (65mA) 730mW 1.1W / 646mW L-Band LNA Band3 LNA Power Gain Range -14 ~ 10dB -10 ~ 24dB NF (max. gain) 6.5dB 2.6dB iip3 (max. gain) -2.5dBm -6dBm ip1db (min. gain) -12dBm -19.3dBm Current 10.36mA 10.7mA L-Band Mixer IF Mixer Conversion Gain 14.4dB 14dB NF 8.7dB 11.9dB iip3-2dbm -2dBm ip1db -13.5dBm dBm Current 15.2mA 13.4mA AMP1 VGA AMP2 Gain 22.7dB -2 ~ 58dB 14dB NF 1.25dB 13dB iip3 4.5dB ip1db -9dBm -19.5dBm -3dBm Current 20.2mA 6.41mA 3.97mA * Separate RF and IF receiver ICs. L-Band VCO is included, but PLL is not included in this design. ** Independent L-Band and Band3 receiver ICs. The L-Band receiver receives and down converts L-Band signal within Band3 frequency range. L-Band VCO is included in this design. The NF shown here are individual NF of each IC. The power consumption is the requirement of each band operation mode. Fig. 11 Measured dynamic responses of DAB. (a) L-Band dynamic response (b) Band3 dynamic response 114 系統晶片 002 期

8 5. Conclusion A receiver IC has been presented which provides a dual band down conversion and AGC function for DAB system. This circuit integrates most of the functions necessary to receive and down convert DAB signals and consumes only 290mW and 214mW for L-Band and Band3 modes, respectively. A novel reference-current-based, programmable AGC and the proposed divideby-multi-divisor prescalar used in this work also enable flexibility and simplicity in wireless communication circuit design. 6. References [1] ETS , Radio broadcasting systems; Digital audio broadcasting to mobile portable and fixed receivers, ETSI, 2 nd ed., May [2] M. Bolle, D. Clawin, K. Gieske, F. Hofmann, T. Mlasko, M. J. Ruf, G. Spreitz, The receiver engine chip-set for digital audio broadcasting, ISSSE 98., pp , Oct [3] W. Titus, R. Croughwell, C. Schiller, L. DeVito, A Si BJT RF dual band receiver IC for DAB, IEEE MTT-S International, vol. 1, pp , June [4] U2730B, L-Band down-converter for DAB receiver, U2731B, DAB one-chip front end, ATMEL Wireless & Micro-controllers, Oct [5] Yen-Horng Chen, A reference-current-based, programmable IF AGC for a DAB receiver, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp , June [6] Z. Lao, M. Berroth, V. Hurm, A. Thiede, R. Bosch, P. Hofmann, A. Hulsmann, C. Moglestue, K. Kohler, 25 Gb/s AGC amplifier, 22 GHz transimpedance amplifier and 27.7 GHz limiting amplifier ICs using AlGaAs/GaAs-HEMTs, ISSCC Digest of Technical Papers, pp , Feb Author 陳彥宏 Yen-Horng Chen was born in Taipei, Taiwan, He received the B.S. in electrical engineering and the M.S. in communication engineering from National Taiwan University, Taipei, in 1999 and 2001 respectively. He worked on the design of microwave circuit and MMIC from 1999 to In 2001, he joined SoC Technology Center (STC), Industrial Technology Research Institute (ITRI), HsinChu, Taiwan. His research interests are in the area of wireless communication integrated circuits. He is currently working on SiGe BiCMOS WCDMA transceiver, DAB receiver and CMOS radio frequency circuits. yenhorng@itri.org.tw ( 本文章摘錄自 系統晶片 002 期, 由工研院系統晶片技術發展中心發行 ) SoC Technical Journal 115