RF CMOS 0.5 µm Low Noise Amplifier and Mixer Design

Transcription

1 RF CMOS 0.5 µm Low Noise Amplifier and Mixer Design By VIKRAM JAYARAM, B.Tech Signal Processing and Communication Group & UMESH UTHAMAN, B.E Nanomil FINAL PROJECT Presented to Dr.Tim S Yao of Department of Electrical and Computer Engineering The University of Texas at El Paso in Partial Fulfillment of the Course Work in RADIO FREQUENCIES & INTEGRATED CIRCUITS EE 5390 Department of Electrical and Computer Engineering THE UNIVERSITY OF TEXAS AT EL PASO April 20th, 2004

2 ABSTRACT A 900MHz Low Noise Amplifier and Mixer has been designed to meet the given specifications. The theory, design process, circuit and simulations results are presented here. INTRODUCTION There is a continuously growing demand for wireless portable communication systems. With minimum feature sizes still obeying Moore s Law, CMOS technology has evolved as the most promising one. The use of CMOS technology is very attractive for integrating the base band Intermediate frequency and Radio Frequency modules in a single chip, now that the passive components like inductors are available on chip. The other advantages of using CMOS technologies over other process are low cost, high integration, mass productivity and easy access to the technology. Here an LNA has been designed using 0.5um CMOS technology. LNA THEORY Low Noise Amplifier is the block dedicated to amplify the weak signal received by the antenna in a receiver system. The main function of a LNA is to provide enough gain to overcome the noise of the subsequent stages (like mixer) as LNA is the first stage of a receiver. This is evident from the Friis formula as given below NF is noise figure and G is the gain [1]. 1 NF rec _ front = ( NFsubsequent 1) + NFLNA GLNA Additionally, the previous stage of a LNA is an antenna or a filter, a specific input impedance of 50ohms is required for maximum power transfer. This matching of input impedance allows in the freedom of choice of different receiver architectures to be used. The LNA should have good linearity so as to accommodate large signals without distortion and noise. Thus LNA design is full of trade offs between these parameters and the design can be complicated. Design Specification Frequency Range Input Impedance Zin Voltage Gain A v Noise Figure with 50 Ω input matching P 1dB IIP 3 Total Current 940 MHz 980 MHz 50 ohm ± 10%, 0 ± 2.5 degree > 20dB < 3dB >-20dBm >-10dBm <5mA

3 LNA Architecture Using CMOS technology the commonly used architectures are common gate (CG) or common source(cs). To meet the noise figure requirements, CS configuration was selected over CG configuration as the CS configuration can overcome the transistor noise by the matching network[2]. Inductive source degeneration has been used to provide real input impedance. The cascaded stage has been used to improve the output impedance. The basic LNA diagram is shown below [3]. DESIGN PROCEDURE Figure 1 Basic LNA schematic and equivalent circuit The design procedure for 0.5um technology is given below.fig2 shows the simplified equivalent circuit of the LNA. At resonance, using the equivalent model [3], we have Rg is taken as zero for most MOSFETS; hence the input impedance is Ra+j [X LS -X CGS ] for inductive source degeneration. As seen in the schematic, another inductor Lg is added in series with the gate to resonate so as to cancel out Cgs capacitance. We need to achieve Rin = (L s. g m )/C gs where Rin is usually about 50 ohms. The usual design procedure is to assume Ls and then find out Lg and g m. For 0.5um technology f T is given as 4GHz. Hence 10 Rs WT = 2. π. ft = 2.51x10 And Ls = = 1.9nH. But to get high gain, we WT arbitrarily increased the value of L s to about 11nH. Next we find the value of L g QL.50 1 Lg = Ls = 13.86n. C gs is given ascgs = = 1. 25pf. With Cgs, 2 WT w0.( Ls + Lg) now we can calculate the width of the transistors given by

4 W 3. C gs = = um where Cox is given by 2.( Cox. L min) ox 0x 3 2 Cox = ε = pf / um. Now g m can be calculated as T g m = WT. Cgs = A / V. The drain current I D can be calculated using the equation 2 g m I D = = 2. 38mA Where k =100uA/V 2 [4]. Now using the gain 2. k '.( W ) L specification that the gain should be above 20dB, we can calculate the values of L3 and C 1 as follows L3 L3 Av = 20dB. i. e. > 10. Hence we assume L 3 =2nH L2.( 1 wc L3C1 ) L2.(1 wc L3C1 ) and 0.9 we have for C 1 C1 > = 12.3pf. The size of the cascade transistor is 2 (2. π. fc ) L3 ) W W chosen same as the M1. i.e. =.M3 is a current mirror and sets the LM1 LM 2 biasing for M1 and hence the width is made 1/10 th of M1 so that there is no wastage of power. The resistor values were chosen as 2Kohms and 200ohms. A DC voltage of 3.3V was chosen. SIMULATION RESULTS: The complete ADS schematic is shown below for the AC Parameter simulation and the S-Parameter simulation [4]. From the AC parameter simulation we obtain the gain to be about 40 db well above the specified value. Also the drain current is about 2.22mA well below the given value of 5mA. From the S-Parameter simulation plots, the noise figure is about 1.39dB. S(1,1) is about 0.6 and the input impedance is about 35 ohms. The input impedance is supposed to be about 50 ohms. The Simulation results are shown below.

5 Figure 2 Schematic for AC Simulation Figure 3 Shows Gain after AC simulation.

6 Figure 4 ADS schematic for S-Parameter simulation Figure 5 Noise Figure

7 Figure 6 Input Impedance Figure 7 Noise Figure minimum

8 MIXER DESIGN A Mixer is an analogue device that can multiply two signals together and also provides the difference of the two signals. They are composed of a non-linear device (a diode or a transistor) and passive couplers devices to inject the input mixing signals into the non-linear device that will perform the mixing. Current technology state-of-the-art in mixer realization shows that the bandwidth of mixers are limited by the passive devices and not by the diode or transistors, which have bandwidths exceeding the requirements. Bandwidth of the mixer will be limited by the bandwidth of the couplers. The multiplication process begins by inputting two signals: The resulting multiplied signal will be: This can be multiplied out thus: SINGLE BALANCED DESIGN The single-balanced mixer is the simplest approach that can be implemented in most semiconductor processes. The single balanced mixer offers a desired single-ended RF input for ease of application. Though simple in design, it has moderate gain and low noise figure. The single-balanced configuration exhibits less input referred noise for a given power dissipation than the double-balanced counterpart. However the circuit is more susceptible to noise in the LO signal[5].

9 MIXER SCHEMATIC Figure 8 Figure 1 shows the Mixer schematic from ADS. Here we use the Single Balanced mixer in our design. Notice that Vout is nothing but the difference in the Intermediate frequencies.

10 SIMULATION RESULTS

11 RESULTS Following results were obtained from the above graphs:- Mixer Conversion gain (output frequency = 10 Mhz)=6.02 db Amplitude of LO leakage at the IF output (V)= 678 mv DC offset at the IF output (V) =40.6 uv Amplitude of LO Leakage at the RF input (V)= 1 mv CONCLUSIONS The Low Noise Amplifier & Mixer were designed to operate in the 940 to 980 MHz range. The Noise figure, Gain, Total Current specifications have been met. However, the input impedance has to be improved. REFERENCES [1] D.K.Shaeffer, T.H.Lee, A 1.5V, 1.5GHz CMOS Low Noise Amplifier, IEEE Journal of Solid-State Circuits, vol.32, pp , May [2] A 900 MHz Low Noise Amplifiers by Vikas Chandra; Carnegie Mellon Pittsburgh, PA. [3] RF, RFIC and Microwave Theory and Design by John Silver. [4] VLSI for Wireless Communication by Bosco Leung. [5] RF Microelectronics by Behzad Razavi. [6]CMOS Integrated circuits by Thomas.H.Lee [7]Solid state Devices by Streetmann.

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