Quiz2: Mixer and VCO Design

Transcription

1 Quiz2: Mixer and VCO Design Fei Sun and Hao Zhong 1 Question1 - Mixer Design 1.1 Design Criteria According to the specifications described in the problem, we can get the design criteria for mixer design: Since f RF = 1.9GHz, f IF = 50MHz, then we have f LO = 1.85GHz; The Noise Figure of the receiver can be expressed as NF tot = NF LNA + NF MIXER 1 A p1, where NF LNA = = , A p1 = = and NF tot = = Then we can get NF MIXER = = 15.9dB; Because 1 A 2 IP 3 and α 2 1 = 1 A 2 IP 3,LNA + α 2 1 A 2 IP 3,Mixer, where A 2 IP 3,LNA 11 = = , so A 2 IP 3,Mixer = = 2.3dB; Supply Voltage is 2V; 10 = = 1 10, A2 15 IP 3 = = The system requires 16dB voltage gain and the gain of the LNA is 11dB, so the mixer gain should be larger than 5dB; The output port impedance is 1K ohms. The design criteria is summarized in table 1. 1

2 PARAMETER Specification Units FREQ-RF 1.9 GHz FREQ-LO 1.85 GHz Noise Figure (SSB) <15 db IIP3 >-2 dbm Voltage Gain >5 db Voltage Supply 2.0 V Input Impedance 50 ohms Output Impedance 1K ohms Table 1: The required specifications of the Mixer. 1.2 The starting point of the Mixer design There are various topographies from simple single ended, single balanced mixers to more complicated double balanced mixers. Since active FET mixers achieve conversion gain with lower LO power than their passive counterparts, the active CMOS single-balanced and double-balanced mixers are commonly used in the CMOS transceiver design. Compared with the single-balanced counterpart, the double-balanced mixer has a better better port-to-port isolation due to symmetrical architecture. In this paper, we will use the double-balanced Gilbert Cell mixer shown in Fig. 1 as our design topology. 2

3 mixer has better port-toarchitecture. The doublee figure due to more noise ixer linearity is controlled ce stage if the LO-driven es. The linearity can be eneration. A good underent degeneration architecgn. Mixer nonlinearity of series analysis has been FET nonlinearity analysis s also been presented [3]. less transfer nonlinearities ever, is unrealistic. equations using a Volterra ngle and double-balanced e degeneration are derived. ollector capacitance C,, is Fig. 1 Sirigle-balanced CMOS mixer I Ft LO- O I I 1 I I I I I RF- Y nd in revised form 1st Noveniber Reliability Laboratory, School or ce, University of Central Florida, + Fig. 2 Double-balanced CMOS mixer Figure 1: Double-balanced CMOS Gilbert mixer. IEE Proc.-Circuits Device7 Syst., Vol. 149, No. 2, April 2002 To improve the linearity, we add degeneration inductors to M1 and M2 sources. We start the design with hand calculations: 1. For simplicity, we use long-channel approximation IIP3 equation to compute the required over drive 2 voltage. Consider our target IIP3 = 0dBm, we have IIP3 = 4 3 (V GS V T ) = 10log( V 2 /(2 50) 1mW ), and then V = , therefore V GS V T = 96.8mV. 2. We select the resistive load R L = 200ohms. Putting a larger load will increase the conversion gain, however, large load resistance will leave less voltage headroom for the transistors which will make them deviate from the saturation region and incur linearity problem. 3. Conversion Gain: If there is no degeneration inductor, Gain = 2 π g m R L. Consider that we have a 1K output impedance and source degeneration inductors, we increase our target voltage conversion gain without source degeneration to 10dB. Thus we have g m = 1010/20 (2/π) 200 = 24.8ms. Using the equation given in [1], we have the overall effective transconductance G m = (2/π)g m Q in = ε ox t ox (2/π)g m 1+ω 0 C gs[r S +(g m/c gs+ω 0 )L s]. Because C gs = (2/3) W L C ox and C ox = = = 7fF/µm 2 (t ox = µm from IBM 6HP design kit document), then 3

4 we have C gs = (2/3) C ox = 172.5fF, R S = 50ohms and ω 0 = 2π = rad/s, so if we assume L s = 1nH, we have G m = 0.011ms, and then the overall conversion gain is G m R L = 7dB which will satisfy our requirement. 4. Since g m = k n W L (V GS V T ), where k n = µ n C ox = µ n ε ox t ox = µA/V 2, then we have W L = 640, and W = 154µm if L = 240nm. 5. From the equation NF = π2 4 (1 + γ g mr S + 2 g 2 mr S R L ), we have NF = = 9.0 db, where γ = From the equation I d = k nw 2L (V gs V T ) 2, we have one branch current through RF section: I d = 1.25mA, so the total current is 2 I d = 2.5mA. 1.3 Circuit Simulation According to our hand calculations, we implemented the Gilbert Cell mixer using IBM 6HP design kit. The design parameters are given in the table 2. Fig. 2 and 3 show the simulation schematic diagrams. PARAMETER VALUE Units FREQ-RF 1.9 GHz FREQ-LO 1.85 GHz L (All Transitors) 240 nm LO-Width (TN0,TN1, TN2, TN3) 150 µm RF-Width (TN4, TN5) 150 µm TN6-Width 150 µm Width (TN7, TN8) 15 µm R L0 = R L1 200 ohms L s1 = L s2 1.2 nh Supply Voltage 2.0 V LO biased Voltage 1.0 V Table 2: Design Parameters in Fig. 2 and 3. 4

5 Figure 2: double-balanced mixer 5

6 Figure 3: Testbench for double-balanced mixer 6

7 The performance from the simulations is shown in the table 3. Target Specification Theory (hand claculation) Simulation Result Comment Intermediate Frequency 50 MHz 50 MHz 50 MHz Noise Figure <15dB 9dB 9dB IIP3-2dBm 0 dbm 0.9 dbm 1dB Compression Point -12 dbm -10dBm -9.8dB Supply Voltage 2V 2V 2V Conversion Gain 5dB 7dB 9dB Current N/A 2.5 ma 4.8 ma LO-IF Isolation N/A N/A -46dB RF-LO Isolation N/A N/A -109dB Table 3: Summary of double-balanced mixer simulation results. 7

8 The simulation results are shown in the following figures, i.e. Fig. 4, 5, 6, 7, 8, 9 and 10. Figure 4: Conversion Gain Versus LO Power using PAC Analysis Figure 5: Conversion Gain Versus IF using Swept PAC Analysis 8

9 Figure 6: The LO-to-IF Feedthrough Using PXF Analysis Figure 7: The RF-to-LO Feedthrough Using using PAC Analysis 9

10 Figure 8: Noise Figure Figure 9: 1dB Compression Point Using QPSS Analysis 10

11 Figure 10: IIP3 Measurements Using QPAC Analysis 1.4 Discussion From table 3, we can easily see that a good agreement between the simulation results and analytical predictions is obtained. The design of mixers faces many comprises between conversion gain, local oscillator (LO) power, portto-port isolation, linearity, noise figure and power consumption. To improve the linearity of the mixer, we slightly increase the source degeneration inductance to 1.2 nh. From our simulation result and the equation mentioned in the above, G m = (2/π)g m 1+ω 0 C gs[r S +(g m/c gs+ω 0 )L s], increasing L s will decrease the conversion gain of the mixer. Also we increase the current to improve the conversion gain and IIP3 in the design, the penalty of this is power consumption. 11

12 2 Question2 - VCO Design A voltage controlled oscillators (VCO) is designed based on the popular complementary cross-coupled topology. The design result is summarized in the following table. VDD 2.0V f o 1.95 GHz Tuning range 26.6% Phase noise Power Dissipation offset 4mW Table 4: Design summary. 2.1 Theoretical Calculation 1 1. For f o = 1.95GHz, f o = 2π, We choose L = 2nH, thus at the middle of tuning range of the LC varactor C = 3.3pF. Considering the parasitic capacitance of active PMOS and NMOS, choose C a little smaller: C = 3pF. Here we choose relative small L in order to get more VCO tuning range. 2. For the 2nH inductor from 6HP library, at 1.95GHz, (from S parameter simulation), We abstain R s = 1.58 ohm, Q ind = 1/W L = 23.5, R p = R s Q 2 = ohm. Thus the tank loss R L 872 ohm. 3. Tuning range: 1 2π LC var,max < f osc < 1 2π LC var,min, where for the varactor we built C var,min = 2.2pF, and C var,max = 3.8pF. Thus 1.89GHz < f osc < 2.3GHz. The frequencies here are a little higher than we need, considering we would have parasitic capacitance. 4. For ensuring oscillation, g m = g mn + g mp 2 5 R L. Let g mn = g mp 45mS For appropriate oscillation swing (V osc I tank R L /2 I tail R L /2 0.9V ), choose I tail = 2mA, From W g mn = µ n C ox L I D We can get W L = 120um 240nm for NMOS and W L = 240um 240nm for PMOS. Here we choose minimum L to minimize parasitic capacitance. 5. Phase noise P N = 10log[ f o 2Q f 2 e 2 n(f) 2P sig ] 127dBc 12

13 2.2 Schematic and simulation Parameters of the transistor M1, M2, M3 and M4: L = 240nm, W n = 120um. W p = 240um Figure 11: VCO Schematic. 13

14 Figure 12: VCO test Schematic. Figure 13: Varactor Test Schematic. 14

15 Figure 14: Capacitance vs. tuning voltage. Figure 15: phase noise plot. 15

16 GHz V_tune (V) Figure 16: Tuning voltage vs. VCO output frequency. Figure 17: Transient simulation. 16

17 2.3 Discussion To reduce the noise and tank loss the PFET and NFET should use multiple fingers. The increase size of cross coupled NFET and PFET can reduce phase noise, however the tuning range will be reduced due to the more parasitic capacitance. To achieve wider tuning range, we can use a switched capacitor array with a small varactor. However the switches design will be critical to the tank loss and noise. 2.4 Comparison with some publications Reference This design [2] [3] [4] [5] Technology CMOS 0.25um CMOS 0.35um CMOS 0.35um CMOS 0.25um CMOS 0.18um f o (GHz) Vdd(V) Power Diss. (mw) Phase Noise (dbc/hz) Tuning Range 26.6% 9.1% 26% 17.9% 3.33% Table 5: Comparison with some publications. 17

18 References [1] Q. Li and J.S. Yuan, Linearity analysis and design optimisation for 0.18µm CMOS RF mixer, in IEE Proceedings on Circuits, Devices and Systems, April 2002, pp [2] Yao-Huang Kao and Meng-Ting Hsu, Theoretical analysis of low phase noise design of cmos vco, in Microwave and Wireless Components Letters, Jan. 2005, pp [3] D. Ham and A. Hajimiri, Concepts and methods in optimization of integrated lc vcos, in IEEE J. Solid-State Circuits, Jun. 2001, p [4] Y.-Z. Juang T.-Y. Lin and C.-F. Chiu, A low power ghz cmos vco with a symmetrical spiral inductor, in IEEE Int. Symp. Circuits Syst., [5] T. K. K. Tsang and M. N. El-Gamal, A high figure of merit and area efficient low-voltage(0.71 v) 12 ghz cmos vco, in Radio Frequency Integrated Circuits Symp., 2003, p