Course Project Topic: RF Down-Conversion Chain Due Dates: Mar. 24, Apr. 7 (Interim reports), Apr. 28 (Final report)

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1 Course Project Topic: RF Down-Conversion Chain Due Dates: Mar. 24, Apr. 7 (Interim reports), Apr. 28 (Final report) 1 Objective The objective of this project is to familiarize the student with the trade-offs and design choices encountered in the design of an RF down-conversion chain. The specifications have been designed to give students freedom to experiment with different architectures and circuit toplogies. The specifications are based on the receive band of a fictional cellular phone standard. Since the design of a complete down-conversion chain is a substantial undertaking, the design will be done in an incremental manner. The first project will encompass the design of the LNA, the second project will encompass the design of the mixer, and the third project will involve the design of the VCO and the integration of the three blocks. The performance metrics fall into five different areas: noise figure, linearity, gain, power consumption, and layout area (you will not have to layout your circuits, this will be an estimate based on your schematics, see Table 1 for details). In each area the student projects will be ranked against each other, and part of the final grade will be determined by these performance rankings. Thus, the student may choose to focus on one particular area, or attempt to compromise and perform reasonably well in all of the areas. Different component topologies will enhance performance in certain areas, so in making design choices you should keep in mind which of these areas you would like to perform well in. Interim reports will be turned in with each of the projects, and are primarily intended to ensure that the student is on track for completing the overall design. The majority of the project grade will be determined by the final report. 2 Requirements The design will be implemented in a representative 0.13 µm CMOS process, with a supply voltage of 1.2 V. Inductors and capacitors will be implemented using the provided models which include estimated parastics. It may be helpful to do the initial design using ideal components (from analoglib) and then sub in the parasitic-laden versions once you have it working. Resistors will be assumed to be ideal, and can be taken from the analoglib library. Varactors will be implemented using MOS varactors. You can use one ideal transformer in your design for single-ended to differential conversion. If you choose to do this, you must factor in 1.5 db of losses for the transformer/balun to your overall system performance calculations. You can use one ideal current source per block for biasing purposes. 1

2 The standard we are designing for has 20 channels (each with a bandwidth of 5 MHz) centered around 2 GHz. The intermediate frequency at the output of the mixer must be 200 MHz, and your VCO must tune over a range of 300 MHz to account for process variation (i.e., your VCO must tune from MHz or from MHz). 3 Tools The design will be carried out using Cadence, available in the ECE department UNIX and Linux labs. It is assumed that students are familiar with the Cadence design tools from previous courses (such as the prerequisite, ECE 5720). If necessary, a Cadence tutorial will be held to review the operation of these tools (date TBA). There are some useful Cadence tutorials on Prof. Brunvand s ECE 5710 page at The help files that accompany Cadence on the ECE servers will also be useful. 4 Grading The overall grading breakdown for the project is shown below: First interim report (due with project 1) % Second interim report (due with project 2) % Final Performance % Final report % The grading for the interim reports will be lenient, as they are primarily intended to ensure that the student is on track for completing the final system design. The performance component will be divided into 10% for the performance of the overall system, and 10% for the performance of the individual blocks in isolation. The performance of the overall system will be divided among the five different areas mentioned previously. For each area, the projects will be ranked and seperated into 4 quartiles. The students in the top quartile will receive 4/4 for that specification, the students in the next quartile will receive 3/4, etc. Additionally, the top student in each area will receive one bonus point as well as the respect and accolades of his/her peers. The performance of each block will be graded similarly. The 60% final report component of the overall grade will be broken down as follows: 5 Report System level design choices and justification % LNA design and justification % Mixer design and justification % VCO design and justification % Schematics, waveforms % Report quality (writing style, structure, clarity) % 5.1 First Interim Report (due Mar. 24) The first interim report will describe the design of the LNA, and should consist of the sections described below: 2

3 A brief introduction describing which performance parameters you have chosen to focus on, and the architectural choices that you have made as a result of this. A section describing your design, the strategies you used for sizing the components, and the trade-offs encountered. You must also provide a transistor level schematic for the LNA. This section will be graded on a complete/incomplete scale in this report, but you might as well do a good job since you can then include it in your final report. Waveforms and metrics from required performance simulations (see Section 8). 5.2 Second Interim Report (due Apr. 7) The second interim report will describe the design of the mixer, and should consist of the sections described below: A brief introduction describing which performance parameters you have chosen to focus on, and the architectural choices that you have made as a result of this. A section describing the mixer you have designed. You should describe your design, why you choose the topology, the strategies you used for sizing the components, and the trade-offs encountered in the design. You must also provide transistor level schematics. This section will be graded on a complete/incomplete scale in this report, but you might as well do a good job since you can then include it in your final report. Waveforms and metrics from required performance simulations (see Section 8). 5.3 Final Report (due Apr. 28) I would like the final report to be formatted in the form of a paper that would appear in an IEEE publication. Since (most of) you are graduate students, there is a good chance you will find yourselves publishing your work at some point, and now is as good a time as any to get familiar with the formatting used. Templates for your paper-style reports can be found at http: // I recommend using the L A TEX template, but for those of you who prefer inferior software there is a Word template available as well. The final report will contain descriptions of the designs for each component, as well as the results of performance simulations. The final report will also contain a number of performance characterizations for the overall system. The final report should consist of the sections described below: An introduction to the problem, and a description of the performance parameters you have chosen to design for. A section describing your top level architecture (including a high level block diagram). One section for each of the components you have designed, describing the architecture you selected (and how that impacts performance of the system as a whole), your approach for transistor/passive sizing, and any tradeoffs that were encountered in the design of the component. You must also include the transistor level schematic for each component, and reproduce the performance plots and tables required for each component. 3

4 Device Area MOSFET (W idth + 1 µm) Length Resistor R (kω) 200 µm 2 Capacitor C (ff ) 0.25 µm 2 Inductor L (nh) 20, 000 µm 2 Table 1: Formulae for calculating the layout areas for your components. A section describing the performance of your system in the specified areas (see Section 8). This section should include a table summarizing the relevant performance parameters for your design. A conclusion summarizing what you have learned in designing your project, and anything that you would do differently if you were to do it again. 6 Getting Started This section will provide you with the information you need to get started running simulations for the project. It is assumed that the student has a working knowledge of Cadence. 1. Start an xterm session on one of the ECE Unix or Linux machines. 2. Add the following lines to your.tcshrc file: set path=($path /uusoc/facility/cad common/local/bin/s06) setenv LOCAL CADSETUP /uusoc/facility/cad common/local/class/6830/s09 The directory in the second line is 6830 as we are borrowing the setup scripts from Prof. Brunvand s VLSI Architecture class. 3. Go to your home directory, and make a directory called Cadence6730 (this is the directory from which you will invoke Cadence). 4. Go to this newly created directory and type ln -s /uusoc/facility/cad common/ncsu/cdk-f07/.cdsinit. (this file does some initialization when you start up Cadence). 5. While still in the same directory, cp /home/ccharles/cadence6730/.cdsenv./.cdsenv (this file sets some environment variables for simulations). 6. While still in the same directory, cp /home/ccharles/cadence6730/cds rename.lib./cds.lib (this file creates the default libraries needed for the course). 7. Finally, type cad-ncsu to start up Cadence, and you are on your way! 7 Instantiating Components This section will provide details on how to instantiate basic circuit elements in your schematic. For general information on how to use Cadence, see Prof. Brunvand s excellent book draft available 4

5 at The book is entitled Digital VLSI Chip Design using Cadence and Synopsys CAD Tools, but chapters 1, 2, 3, and 7 are also applicable to the Analog design that we will be doing. MOSFETs: type i to instantiate a new component, then from the analoglib library browse to the Actives section, and select nmos or pmos. Under Model name enter nfet130 or pfet130. Enter the desired width and length (no less than 130n m) into their respective fields, and if you wish to divide the transistor into a number of smaller fingers, use the Multiplier field. Passives: for your intial design, I would recommend using ideal components, and then replacing these with the lossy models once you have it working. For ideal components, from the analoglib library, browse to the Passives section, and select cap, ind, or res. For non-ideal components, from the Passives library, select either cap real or ind real. We will use ideal resistors. Sources: from the analoglib library browse to the Sources section, where you can select independant or dependant sources, or globals (for vdd and gnd). 8 Performance Simulations 8.1 Low Noise Amplifier Include waveform plots in your report as specified in each of the following simulations, and also include a table which summarizes your designs performance in each of the following areas. It is recommended that you create seperate cell views for each of the simulations described below. It may also be easiest to create a symbol for your LNA that can be instantiated in each of your simulation schematics so that changes made to the LNA are reflected in all of the schematics Area Consumption No simulation is required for this metric, just add up the areas for all for all of the components in your LNA schematic. Be sure to include blocking capacitors and biasing circuitry Power Consumption 1. Ground the input and output of your LNA (if you have no blocking capacitor at the output just leave it open). 2. Open the Analog Design Environment, and enable a dc simulation, with Save DC Operating Point selected. 3. Run the simulation, and when it is finished, in the Analog Design Environment select Results->Annotate->DC Operating Point. DC bias currents and voltages will now be shown on your schematic, as seen in Fig Record the total power consumption as the power supply voltage (1.2 V) multiplied by the current drawn from the power supply (13.94 ma in Fig. 1). No waveforms need to be reported for this simulation. 5

6 Figure 1: Schematic for power consumption simulation S-Parameters 1. Instantiate ports (analoglib->sources->ports->port) at the input and output of your LNA. 2. Edit the input port so that the Resistance is 50 Ω, the Port Number is 1, and the Source Type is dc. 3. Edit the output port in the same way, except set the Port Number to 2. Here we are assuming that the LNA will be driving a 50 Ω output impedance. In reality the LNA will be driving the mixer, so once we have designed the mixer the LNA may need some tweaking according to the chance in output loading. 4. Open the Analog Design Environment and enable an sp simulation. Select the ports in your schematic for the Ports entry, and select Frequency as the Sweep Variable with Sweep Range set to Start at 1.5G and Stop at 2.5G. Set Sweep Type to Linear and select Number of Steps and set it to Run the simulation, then select Results->Direct Plot->Main Form. 6. Using the resulting form, plot S11 with Plot Type set to Rectangular and Modifier set to db20. 6

7 7. Place markers on the resulting plot at 1.95 GHz and 2.05 GHz (the extremes of the band that we are interested in recovering). Quote the maximum of these values as the S11 measurement in your performance summary table, and include this plot in your report. 8. Repeat the previous two steps for S21, this time quoting the minimum of the two values in your performance summary table Noise Figure 1. Follow steps 1-4 from Section In the Choosing Analysis form in step 4, select yes for Do Noise and select the input and output ports. 2. Now we need to modify the schematic to include the effects of induced gate noise. For each noise critical transistor in your LNA (generally, any transistor that appears in the signal path), add the circuitry described in Lecture 10 for induced gate noise simulations. An example for an LNA with one noise critical transistor is shown in Fig. 2. The core LNA circuitry is in the top half of the figure, and the additional dummy transistor for generating the induced gate noise are in the lower half of the figure. The additions that must be made to the core LNA circuitry are highlighted in red. 3. For the current controlled current sources, use analoglib->sources->dependant->cccs. Each cccs requires a dc voltage source (with DC Voltage set to 0) to be inserted where the controlling current is to be measured (in Fig. 2 the dc voltage source monitoring the drain current of M1 is highlighted in red). In the properties of each cccs, set Type of Source to cccs, set Current gain to the appropriate value, and set Name of voltage source to the name of the dc voltage source that monitors the controlling current. 4. For the voltage buffers, use analoglib->sources->dependant->vcvs with the Voltage gain set to Run the simulation, then select Results->Direct Plot->Main Form. 6. Using the resulting form, select NF under Function, and plot the noise figure with the Modifier set to db10. Be sure that Plotting Mode is set to Append, select NFmin under Function, and plot the minimum noise figure on the same plot. 7. Place markers on the noise figure at 1.95 GHz and 2.05 GHz, and include this plot in your report, citing the higher of the two values in your performance summary table IIP3 1. Instantiate a port (analoglib->sources->ports->port) at the input and output of your LNA. 2. Edit the input port so that the Resistance is 50 Ω, the Port Number is 1, and the Source Type is sine. Fill in Fund1 for Frequency name 1, 1.95 GHz for Frequency 1, and prf for Amplitude 1 (dbm). Click on Display second sinusoid and fill in Fund2 for Frequency name 2, 2.05 GHz for Frequency 2, and prf for Amplitude 2 (dbm). 7

8 Figure 2: Schematic for noise figure simulation. 3. Edit the output port so that the Resistance is 50 Ω, the Port Number is 2, and the Source Type is dc. 4. Open the Analog Design Environment, and enable a pss simulation. 5. Verify that Fund1 and Fund2 show up in the Fundamental Tones window, and select Beat Frequency and Auto Calculate. 8

9 6. Fill in 60 for Number of harmonics. 7. Select conservative for Accuracy Defaults. 8. Select Sweep and enter prf for Variable Name. 9. Select Start-Stop for Sweep Range, and set it to -30 to Select Linear for Sweep Type, and set the Step Size to Run the simulation, then select Results->Direct Plot->Main Form. 12. Using the resulting form, select IPN Curves under Function, then select Variable Sweep. 13. Enter -20 for Input Power Extrapolation Point (you may need to replot it with a different value here depending on how your curves look). 14. Make sure that Input Referred IP3 is selected, with Order set to 3rd. 15. Select 2.15G for 3rd Order Harmonic, and select 2.05G for 1st Order Harmonic. 16. Move to the schematic window, click on the output port, and hit escape. 17. Your plot should look something like the example in Fig. 3. From the fundamental you can clearly see where the 1-dB compression point occurs, your IP3 point should occur at a higher power. You may need to replot with a different Input Power extrapolation, choose one in a range where 3rd order curve has about the right slope (as in Fig. 3. Include this plot with your report, and cite the IIP3 value in your performance summary table. 18. For more information on IP3 simulations, open Help->Cadence Documentation and browse to Spectre RF->SpectreRF Simulation Option User Guide->Simulating Low-Noise Amplifiers. 8.2 Mixer Coming soon Voltage Controlled Oscillator Coming soon Complete System Coming soon... 9 Helpful Hints 9.1 Transistor Parameters For the initial design procedure, it is useful to know the relevant transistor characteristics )g m, C gs, etc. The best way to find these is to bias the transistor with the proper current and node voltages, run a dc simulation (as described in the LNA power consumption simulation), and then select 9

10 Figure 3: Example plot from IP3 simulation. Results->Print->DC Operating Points and click on the transistor. Don t worry about some of the small signal capacitances being negative, that is just a result of the way they are calculated, use the absolute value. 9.2 Parametric Simulations For optimizing different variables, it can be useful to run parametric simulations. To do this, replace the quantity you would like to optimize with a variable name (e.g., fill in Lg for the inductance of one of your inductors), then in Analog Design Environment select Variables->Copy From Cellview. Now select Tools->Parametric Analysis, and in the resulting form fill in the variable name and the range over which you would like to sweep it. You can then plot all of the usual quantities over this range for whatever simulations that you have enabled. 9.3 Noise Optimization For optimizing noise performance, it can be useful to know which noise sources are dominating the noise at the output. To determine this, run a pnoise simulation, and you can then print out the percentage noise contributions of the different noise sources in the circuit. For details on how to run pnoise simulations, see the relevant section in the SpectreRF user guide, which can be 10

11 accessed by opening Help->Cadence Documentation and browsing to Spectre RF->SpectreRF Simulation Option User Guide->Simulating Low-Noise Amplifiers. 11