Design and power optimization of CMOS RF blocks operating in the moderate inversion region
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1 Design and power optimization of CMOS RF blocks operating in the moderate inversion region Leonardo Barboni, Rafaella Fiorelli, Fernando Silveira Instituto de Ingeniería Eléctrica Facultad de Ingeniería Universidad de la República Montevideo, Uruguay F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
2 Outline I. Motivations, Objectives, Introduction II. Tool for CMOS RF Amplifier Power Optimization III. 900 MHz Amplifiers prototypes and experimental results IV. 900 MHz Voltage Controlled Oscillator Design Phase Noise Design Methodology and Trade Offs Inductor Design Experimental Results V. Conclusions F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
3 I. Motivations and Framework. Applications: Short Range (< 10m) Links for Wireless Sensors or Telemetry (WPAN: Wireless Personal Area Networks) - IEEE (2003) / Zigbee - f (MHz): 868 / 915/ / 10 / 16 Channels - 20 / 40 / 250 kbps (*)"IEEE : A Developing Standard for Low Power Low Cost Wireless Personal Area Networks",IEEE Network, Oct2001 F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
4 I. Objectives Design of IEEE (or ad hoc) transmitter + integrated sensor. Test possibility of translating low-frequency ultra low power analog experience to the RF domain. Tool to design and evaluate the operation of RF circuits in Weak and Moderate Inversion. (previous work Porret et al, CSEM, 0.5µm, 433MHz, JSSC 3/2001) First experiences in design of RF integrated circuits. F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
5 I. Introduction: MOST Inversion Regimes Strong Inversion (S.I.) I D (V G -V T ) 2 Moderate inversion Weak inversion: I D e VG/(n.UT) F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
6 I. Introduction: Intrinsic MOS Amplifier V DD A (db) A 0 =g m /g d vi I D vo C L f T =g m /(2.π.C L ) f(hz) OTA: Operational Transconductance Amplifier gm gm A 0 = gm.ro = =. VA gd ID f T gm = 2πC L, A0 A = s.a 1+ 2πf 0 T Consumption: I D Speed g m /C L Speed - Consumption trade-off : g m /I D F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
7 I. Introduction:Optimum of Power Consumption Weak inversion: I D e VG/(n.UT) Moderate inversion gm/id (1/V) Strong inversion (I D (V G -V T ) 2 ) ID/(W/L) (A) Working towards WI g m /I D I D W/L C g m Usually an optimum exists in moderate inversion F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
8 Outline I. Motivations, Objectives, Introduction II. Tool for CMOS RF Amplifier Power Optimization III. 900 MHz Amplifiers prototypes and experimental results IV. 900 MHz Voltage Controlled Oscillator Design Phase Noise Design Methodology and Trade Offs Inductor Design Experimental Results V. Conclusions F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
9 II. MOS transistor modeling (I) Continuous model for W.I to S.I => ACM model Basic structures modeled as 2-port network F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
10 II. MOS transistor modeling (2) Medium frequency model: 5 capacitors, Quasi-static, No velocity saturation effect Quasi-static: g m gm ω = 1 + jωτ ( ) gm f QSmax ft 10 = π Quasi-static model limit g m = ( C ) gs + Cgb + Cgd ID f g m F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
11 II. Object of study: Basic RF amplifier stages 1 Vdd Me_1 Me_0 2. Iref 4 RF 3 CL Vo. Cd M1. 5 Vin R1 R2 C2. F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
12 II. Design Space Exploration ISCAS 2006 In the design space (I D -gm/i D ) are calculated the curves of constant gain A. F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
13 II. Ex. (1): One Stage Amplifier One stage amplifier at 910MHz and L=0.35um with: Load capacitance CL=0.5pF Feedback resistance RF=5kΩ Rg neglected Minimum A=2V/V calculated simulated F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
14 II. Ex. (2):Effect of gate resistance Gate resistance, non interdigitized layout 1 W R g R 3 L Original optimum not considering Rg F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
15 II. Tool user interface F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
16 II. Ex. (3): Technology comparison One stage amplifier with G=2V/V, C L =0.1pF and no R F. L min = 0.8µm L min = 0.35µm 900MHz is not high frequency for 0.35µm technology Ultra low power consumption techniques (MOS transistor in MI and WI) can be used increase efficiency It is possible to work optimally in MI and in QS region F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
17 II. Other Recent Results:IMEC, 2004, 90nm g m /I ds (V -1 ) and g m /g ds moderate inversion g m /g ds g m /I ds strong inversion f max Drain current, I (µa/µm) ds f T f T and f max (GHz) Design specification: f max and f T > 5-10 times f application Moderate inversion Up to 5GHz applications. Low power consumption. Strong inversion Up to 20GHz applications. Higher power consumption. * W. Jeamsaksiri et al. Symposium on VLSI Technology, June, 2004 ** J. Ramos et al. ESSDERC, September 2004 F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
18 Outline I. Motivations, Objectives, Introduction II. Tool for CMOS RF Amplifier Power Optimization III. 900 MHz Amplifiers prototypes and experimental results IV. 900 MHz Voltage Controlled Oscillator Design Phase Noise Design Methodology and Trade Offs Inductor Design Experimental Results V. Conclusions F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
19 1- PA of a Low Power Short Range Tx 2- Optimum Amplifier Stage III. Experimental Prototypes 3- Three Stages Preamplifier (2) Me_1 Me_2 Me_3 Vdd Ld Me_0 Iref. (3) Ce GND (A). (12) (11) M1 5K (10) M2 15K (9) M3. 13p (13) CL L A1 Cb. Vo. RL Vbias2 (1) Mp A2 Vin GND... 50K (3) 50K. C2.. F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
20 III. Measurement: Optimal Stage F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
21 III. Measurement: Optimal Stage F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
22 III. Measurement: Optimal Stage ID= 0.50mA estimated, 0.53mA simulated, 0.54mA measured. With Input Power estimated from simulations Pout Gp (Power Gain) Simulated dBm db Measured Estimated dBm dBm 10.6 db 11 db F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
23 Outline I. Motivations, Objectives, Introduction II. Tool for CMOS RF Amplifier Power Optimization III. 900 MHz Amplifiers prototypes and experimental results IV. 900 MHz Voltage Controlled Oscillator Design Phase Noise Design Methodology and Trade Offs Inductor Design Experimental Results V. Conclusions F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
24 IV. Phase Noise in LC VCOs V0 (t) = Acos(ω0t + φ) V0 (t) = A(t)cos(ω 0t + φ(t)) Origin Upconversion of the 1/f noise and white noise due to a nonlinear system F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
25 IV. Phase Noise in LC VCOs Phase noise definition L( ω) = [ L( ω )] = dbc/hz P (ω 10log sideband 0 + P carrier ω,1hz) 1/f 3 1/f 2 F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
26 IV. Gm LC Complementary VCO Circuit Margin g f m 0 = g αg = 2π tank tank /2 /2 1 LC tank F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
27 IV. VCO Design Methodology Ind L C Mi C var f 0 gl,par W Mi Q L I D g m = αg L,par /2 α g m /I D L f 0 = 2π 1 LC tank If L >L max C var <C min F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
28 IV. VCO Design Trade-offs Q L g m /I D ( ID ) L but... L 2 x2 then P d (-6dB) F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
29 IV. VCO Final Design Design parameter Value L 5nH g m /I D 11 C var W n 0.7pF 336µm W p 782µm F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
30 IV. Phase Noise Phase noise models: Linear time invariant model (LTI) (by Leeson, Proc. IEEE, 1966), Adjustment parameter F. Linear time variant model (LTV) (by Hajimiri and Lee, JSSC 2000) F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
31 IV. Phase Noise Phase noise obtained from simulation With a Matlab routine: LTI model LTV model Differences probably due to factor F With Cadence: F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
32 IV. Inductors Design Characteristics Inductance value Quality factor Self resonance frequency Area, number of turns and width. Dependent on the technology characteristics:» Number of metal layers» Inductor metal thicknesss» Resistivity of the substrate F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
33 IV. Inductors Design Modelling Lumped inductor model:» Mohan s inductance expressions» Yue s model Q = L ω 0 R L s s π net F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
34 IV. Inductors Design Inductor losses Metal losses» Skin effect» Eddy currents in the winding Substrate losses» Eddy currents in the substrate F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
35 IV. Inductors Design Final inductor design Geometry Metal Number of turns W s Square Top metal 14µm d out 1.5 µm µm L(nH)Characteristics 5.1 Rs(Ω) calculated with 9 3 tools: Cs(fF) Cox(fF) Q Matlab ASITIC Cadence F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
36 IV. Varactor Inversion Mode MOS F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
37 IV. VCO Layout Final design F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
38 IV. VCO Measurements Measurement setup F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
39 IV. VCO Measurements VCO oscillation frequency versus V bias K VCO =-169MHz/V tuning range=11% K VCO =-214MHz/V tuning range=15% F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
40 IV. VCO Measurements PSD and phase IDD = 3mA, VDD=3V =-87dBc/Hz =-102dBc/Hz =-107dBc/Hz F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
41 V. Conclusions Inversion level that gives an optimum consumption for a given gain. Matlab tool which helps in the design of low power RF blocks. Feasibility of working in moderate inversion at 910MHz in 0.35µm technology. Experience in ultra low power analog design may be reused here. VCO: Moderate inversion provides a good compromise between phase noise and consumption. Layout wiring parasitics and package parasitics strongly affect performance F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
42 Thank you! F. Silveira Univ. de la República, Montevideo, Uruguay EAMTA
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