A 5GHz, 32mW CMOS Frequency Synthesizer with an Injection Locked Frequency Divider. Hamid Rategh, Hirad Samavati, Thomas Lee

Transcription

1 A 5GHz, 32mW CMOS Frequency Synthesizer with an Injection Locked Frequency Divider Hamid Rategh, Hirad Samavati, Thomas Lee

2 OUTLINE motivation introduction synthesizer architecture synthesizer building blocks injection locked frequency divider (ILFD) voltage controlled oscillator (VCO) prescaler charge pump and loop filter summary conclusion

3 MOTIVATION large demand on wideband wireless LAN systems 20+Mb/s data rate low cost low power new released frequency band unlicensed national information infrastructure (U NII) band

4 GOAL design a 5GHz frequency synthesizer for a U NII band wireless LAN receiver (HIPERLAN compatible) implement in CMOS minimize power consumption

5 FREQUENCY OF OPERATION HIPERLAN U-NII MHz (a) GHz GHz (b)

6 RECEIVER ARCHITECTURE I LNA Q f RF = GHz f LO = f RF 90 o Frequency Synthesizer H. Samavati et al., A 12.4mW CMOS Front End for a 5GHz Wireless LAN Receiver, 1999 Symposium of VLSI Circuits, Session 9.2.

7 f out = M f ref INTEGER N FREQUENCY SYNTHESIZER f ref PFD f out =M.f ref Loop Filter VCO M Channel Selection M = M o + S = 0; 1; 2; :::; 7 S

8 f in = (PN + S) f out PULSE SWALLOW FREQUENCY DIVIDER Prescaler Program Counter f in N/N+1 P f out M Modulus Control S Reset Swallow Counter Channel Selection one output cycle = + 1)S + (P, S)N = PN + S input cycles. (N M = PN + S = M o + S

9 PROPOSED ARCHITECTURE f ref PFD Charge Pump Loop Filter VCO f out f ref =11MHz f o = GHz 8 channels M= N=22 Program & Pulse Swallow Counters M Prescaler N/N VCDILFD Channel Select Modulus Control

10 ILFD SIMPLIFIED PICTURE ω i ω i 2 e f(e) = e ω i ω i 2 u, 2ω, 3 2 i ω i Η(ω) ω i 2 oscillator feedback model with perturbation oscillation conditions should be satisfied in the presence of the incident signal

11 VOLTAGE CONTROLLED DIFFERENTIAL ILFD Vdd 0.24m CMOS Vdd=1.5V + Vout Vc f o =2.25GHz M2 M1 I bias I bias =300A f i =4.5GHz R2 M4 M3 R1 Vin

12 INDUCTOR DESIGN (ILFD) maximum locking range ) maximize L minimum power consumption ) maximize LQ

13 INDUCTOR DESIGN C s L s R s C ox C ox OD R si C si C si R si w Sub design parameters: w: metal width s: metal spacing OD: outer dimension n: number of turns s

14 INDUCTOR DESIGN (ILFD) in planar spiral inductors maximizing L does not maximize LQ + maximize L for a given LQ

15 VCDILFD FREQUENCY RANGE 0.24m CMOS Vdd=1.5V I bias =300A Incident amplitude (V) Vc=0.0V Vc=2.0V Incident frequency (MHz)

16 TRACKING ILFD V c VCO V i VCDILFD 1 2 V o locking range extension

17 die area 0.186mm 2 ILFD SUMMARY maximum frequency of operation 5GHz output frequency tuning 110MHz 5% input referred locking range 450MHz 0.7mW 900MHz 1.0mW technology 0.24m CMOS flip flop based divider 0.24m CMOS(simulation) 0.1m CMOS (Razavi et al., JSSC Vol. 30, No.2, pp , Feb. 1995) 5GHz 5GHz

18 VOLTAGE CONTROLLED OSCILLATOR Vdd 0.24m CMOS Vdd=1.5V I bias =2.0mA Vout Vc + f o =4.85GHz M2 M1 I bias M3

19 VARACTOR n+ G n- n - n+ S/D + G C N-well Sub S/D accumulation mode MOS capacitor large quality (> factor 5GHz) flat band voltage zero A. S. Porret et al., CICC Digest, pp , V FB V GS T. Soorapanth et al., Symposium on VLSI Circuits Digest, pp 32 33, 1998.

20 INDUCTOR DESIGN (VCO) maximum Q ) minimum inductor noise if inductors are not the main source of noise, maximum LQ ) maximum oscillation amplitude for a given bias current minimum phase noise

21 VCO FREQUENCY TUNING 0.24m CMOS Vdd = 1.5V I bias = 2.0mA f = 370MHz 7.7% V c =1.5V ( df Frequency (GHz) dv ) max =500MHz/V Control voltage (V)

22 PRESCALER In Clk MC 2/3 MC MC Q Clk 2/3 MC Q Clk 2/3 Q Clk 2 Q Out D Q D Q Clk Q Clk Q divide by 22/23 N = S 1 :2 0 + S 2 :2 1 + S 3 :2 2

23 PRESCALER (ZERO GATE DELAY) ( 2/3) ( 2/3) ( 2/3) 3 01 ( 2) N = S 1 :2 0 + S 2 :2 1 + S 3 :2 2 T clk = 400ps D FO4 = 160ps (Slow process + high temperature)

24 PRESCALER (NON ZERO GATE DELAY) ( 2/3) ( 2/3) ( 2/3) 3 ( 2) problem: gate delays add solution: make gates faster ) burn more power use quadrature outputs to generate swallow commands

25 CHARGE PUMP AND LOOP FILTER I=50A I Vdd vco R1=47k U M3 M4 U C1 C2 C3 R3=8k C1=30pF C2=3.3pF O n 1 O p R1 R3 Vc C3=2pF D M2 M1 D I

26 LOOP FILTER NOISE 10MHz 22MHz Phase noise (dbc/hz) noise of R1 noise of R Offset frequency (Hz)

27 PLL PHASE NOISE MHz Phase noise (dbc/hz) Offset frequency (Hz)

28 SYNTHESIZER CHIP MICROGRAPH 0.24m CMOS PRESCALER VCDILFD area=1.6mm 2 1.6mm) (1mm COUNTERS PFD & CHG PUMP BIAS LOOP FILTER VCO

29 Die area 1.6mm 2 SUMMARY Synthesized frequencies Reference frequency LO spacing Spurs Phase noise VCO power VCDILFD power Prescaler power Total power Supply voltage GHz 11MHz 22MHz fref, 2 fref 1MHz 3.0mW 1.2mW 25.4mW 32mW 2.0V (1.5V for VCO & VCDILFD) Technology 0.24m CMOS

30 COMPARISON f reference (GHz) power L FM comment Parker, JSSC mW 0.6m 10.6 integer N Craninckx, ISSCC mW 0.4m 14.1 fractional N Shahani, JSSC mW 0.5m 22.2 dividerless This work mW 0.24m 37.5 integer N FM= fl power

31 CONCLUSION A 5GHz frequency synthesizer is fully integrated in 0.24m CMOS power consumption is reduced by employing a voltage controlled ILFD optimizing spiral inductors for the VCO and ILFD taking advantage of quadrature outputs in the prescaler loop filter noise is kept small by using reasonably small resistors low spurious side bands are achieved by using a semi differential charge pump designing a fourth order loop

32 ACKNOWLEDGMENTS M. Hershenson S. Mohan T. Soorapanth National Semiconductor Stanford Graduate Fellowship Program