A Low Phase Noise 24/77 GHz Dual-Band Sub-Sampling PLL for Automotive Radar Applications in 65 nm CMOS Technology

Transcription

1 A Low Phase Noise 24/77 GHz Dual-Band Sub-Sampling PLL for Automotive Radar Applications in 65 nm CMOS Technology Xiang Yi, Chirn Chye Boon, Junyi Sun, Nan Huang and Wei Meng Lim VIRTUS, Nanyang Technological University, Singapore 1

2 Outline Motivation Dual-band VCO Dual-band PLL Measurement Results Conclusions 2

3 Motivation 24/77 GHz automotive radar applications Applications Range Frequency Adaptive Cruise Control 200 meters 77 GHz Pre-Crash 30 meters 24/77 GHz Blind Spot Detection 20 meters 24/77 GHz Stop and Go 30 meters 24/77 GHz From 3

4 Motivation Dual-band to reduce cost and power Integer-N: 1.5GHz 16(48)=24(77)GHz FMCW reference is needed Mixer LNA IF Output FMCW 24/77GHz PLL ~1.5GHz N=16(48) 24/77GHz 4 PA

5 Dual-band VCO Dual-peak (ω osc1 and ω osc2 ) At ω osc1, V 1 = V 2 At ω osc2, V 1 =- V 2 Z Z C 1 in L 2 V 1 V 2 L 1 C 2 sl ( s L C 1) in 4 2 s L1C 1L2C2 s L1C 1 L1C 2 L2C2 ( ) 1 Phase (Degree) Magnitude (Ohm) ω osc1 V 1 V V 1 V 2 ω osc / LC / LC osc1,2 1 (1 ) 2 ( 1 2 ) 1 ( 1 2 ) 1 2 Frequency (GHz) 5

6 Schematic of Dual-band VCO No switch in the signal path B24=1, 24GHz mode B77=1, 77GHz mode V DD B77 I B77 M 3 M 4 V ctrl L 1 L 1 C 1 C 1 L 2 C 2 /2 L 2 V 1p V 1n V 2p V 2n M 1 M 2 M 5 M 6 I tail B24 I B24 B24=B77 6

7 Operation of Dual-band VCO 24GHz mode V 1p =V 2p B77 I B77 V DD M 3 M 4 V ctrl L 1 L 1 C 1 C 1 L 2 C 2 /2 L 2 V 1p V 1n M 1 M 2 M 5 M 6 V 2n V 2p I tail B24 I B24 7

8 Operation of Dual-band VCO 77GHz mode V 1p =-V 2p B77 I B77 V DD V 2p V 2n V M 3 ctrl L 1 L 1 C 1 C 1 L 2 C 2 /2 L 2 V 1p V 1n M 1 M 2 M 5 I tail B24 I B24 8

9 Layout of Inductors HFSS EM simulation: 3.3μm copper layer, high impedance shielding L 1 160pH, L 2 100pH 24GHz: Q L1 Q L2 20; 77GHz: Q L1 8, Q L μm L 1 V DD L 2 176μm L 1 Active Devices L 2 9

10 Simulated Results 24GHz 77GHz Ivco(mA) Phase Phase Tuning Range ~1GHz ~3GHz 10

11 Schematic of Dual-band PLL Sub-sampling is used to reduce the in-band phase noise from divider and PFD/CP Pulse generator / programmable charge pump are used to control the loop bandwidth FMCW Sub Sampling f in =~1.5GHz PD Pulse Gen V sam TIA CP f pul R p C p f fb =~24GHz V ctrl C p2 24/77GHz VCO f vco ILO Buffer / 3 ILFD 24/77GHz Buffer f LO 24GHz Buffer Divider/PFD/CP L in-band are reduced by 16X in 77GHz mode! f out 11

12 Injection-locked Oscillator Can work as an injection-locked buffer (24GHz input) or a divide-by-3 divider (77GHz input) Input Amplitude (mv) GHz Buffer (w/o symbol) Input Frequency (GHz) V b =1.2V V b =0V V b V DD f vco + f vco - f fb - f fb GHz Divider (w/i symbol) Input Frequency (GHz) 12

13 Sub-sampling Phase Detector f fb is sub-sampled by f in, the phase error is converted into voltage error Self-bias inverters provide isolation f fb + V Sam + f in f fb - V Sam - 13

14 Transimpedance Amplifier Charge Pump Voltage error is converted into charge/discharge current Pulse width and charge current can be tuned to control the bandwidth V DD I cp,up f pul + f pul - V Sam + V Sam - f pul - V ctrl f pul + I cp,dn 14

15 Die Photo GLOBALFOUNDRIES 65 nm LP CMOS ILO Buffer 3 ILFD 24GHz Buffer Dual-Band Buffer L 2 L 1 900μm 550μm f out LPF SSPD + TIA CP 24/77 GHz Dual-Band VCO f in 15

16 24GHz mode Output Spectrum Operation range: GHz 16

17 77GHz mode Output Spectrum Operation range: GHz 17

18 Output Spectrum Reference spur: -38dBc 18

19 Frequency Error Measurement FMCW Mixer HMC554 SMF100A Signal Generator 24/77GHz PLL ~24GHz LO 20GHz DSO 91304A Oscilloscope PC Matlab Signal Generator E8267D 19

20 FMCW Frequency FMCW reference is from a signal generator SMF100A 20

21 Frequency Error 21

22 Frequency Error 22

23 Phase Noise (dbc/hz) Phase Noise Small loop bandwidth GHz Mode 77GHz Mode (Divide-by-3) -120 Small loop -130 bandwidth 1k 10k 100k 1M 10M Offset Frequency (Hz) 23

24 Phase Noise (dbc/hz) Phase Noise Large loop bandwidth GHz Mode 77GHz Mode (Divide-by-3) -120 Large loop bandwidth k 10k 100k 1M 10M Offset Frequency (Hz) 24

25 Comparison Ref. [1] Jain JSSC 2009 [2] Mitomo JSSC 2010 [3] Lee JSSC 2010 [4] Ye IMS 2012 Tech μm BiCMOS 90 nm CMOS 65 nm CMOS 65 nm CMOS V DD (V) f ref (MHz) Range (GHz) MHz (dbc/hz) Power (mw) ~ This work 65 nm CMOS 1.3 ~ References are in the next slides. 25

26 References in the comparisons [1] V. Jain et al., A BiCMOS dual-band millimeterwave frequency synthesizer for automotive radars, IEEE J. Solid- State Circuits, vol. 44, no. 8, pp , Aug [2] T. Mitomo et al., A 77 GHz 90 nm CMOS transceiver for FMCW radar applications, IEEE J. Solid-State Circuits, vol. 45, no. 4, pp , Apr [3] J. Lee et al., A fully-integrated 77-GHz FMCW radar transceiver in 65-nm CMOS technology, IEEE J. Solid-State Circuits, vol. 45, no. 12, pp , Dec [4] L. Ye et al., A W-band divider-less cascading frequency synthesizer with push-push 4 frequency multiplier and sampling PLL in 65nm CMOS, in IEEE MTT-S Int. Microw. Symp. Dig. Papers, Jun. 2012, pp

27 Conclusions Dual-band VCO is presented to generate two LO signals Sub-sampling is used to reduce phase noise Pulse width and charge current can be tuned to control the loop bandwidth Dual-band PLL achieves low phase noise and power consumption performance 27

28 Thank you! 28