A 0.2-to-1.45GHz Subsampling Fractional-N All-Digital MDLL with Zero-Offset Aperture PD-Based Spur Cancellation and In-Situ Timing Mismatch Detection

Transcription

1 A 0.2-to-1.45GHz Subsampling Fractional-N All-Digital MDLL with Zero-Offset Aperture PD-Based Spur Cancellation and In-Situ Timing Mismatch Detection Somnath Kundu 1, Bongjin Kim 1,2, Chris H. Kim 1 1 Dept. of ECE, University of Minnesota, Minneapolis, MN 2 Rambus Inc., Sunnyvale, CA 1

2 Outline Background: PLL vs. MDLL Reference Spur Cancellation In-situ Reference Spur Detection 65nm Test Chip Architecture Measurement Results Conclusion 2

3 PLL based Clock Generation VCO phase noise is filtered by PLL loop bandwidth Maximum PLL bandwidth is roughly f REF /10 3

4 Multiplying DLL (MDLL) based PLL VCO phases are periodically replaced by reference phases Main advantage: Phase noise suppression above the PLL bandwidth Ref: S. Ye, et al., JSSC

5 Reference Spur Issue in MDLL ΔT ΔT=ΔT1+ΔT2 REF ΔT1 PD ΔT1: PD offset ΔT2: Divider delay REF DIV 2T Multiplexed Ring VCO OUT T+ΔT T-ΔT DIV ΔT2 Divider OUT Output Spectrum spur spur -f REF f OUT +f REF Mismatch in phase detection and reference injection path causes reference spur Divider delay and phase detector (PD) fixed offset are significant source of mismatch 5

6 Outline Background: PLL vs. MDLL Reference Spur Cancellation In-situ Reference Spur Detection 65nm Test Chip Architecture Measurement Results Conclusion 6

7 Reference and DCO Phase Realignment REF DTC ΔT REF' PD DIV Divider OUT Additional reference delay in phase detection path cancels spur Challenge: Delay should be adjusted and tracked precisely 7

8 Reference and DCO Phase Realignment Phase detector for reference and DCO phase realignment should have no inherent phase offset 8

9 Zero-offset Aperture Phase Detector Latch based PD has ideally zero phase offset 9

10 Outline Background: PLL vs. MDLL Reference Spur Cancellation In-situ Reference Spur Detection 65nm Test Chip Architecture Measurement Results Conclusion 10

11 Drawback in Off-chip Measurement Requires high frequency probes or packages, off-chip drivers and connectors Each of these components introduces inaccuracy in the measurement 11

12 Error Rate Calculation T CK1 CK Prog. delay (T p ) D Q CK OUT T CK1 T p Error Rate = Avg(T OUT) T CK Error pulse generated when programmable delay is larger than clock period 12

13 Error Rate Calculation ΔT T CK1 CK Prog. delay (T p ) D Q CK OUT ΔT T CK1 T p Error Rate = Avg(T OUT) T CK T CK2 T CK2 T p Skew between two error rate plot is the time period difference 13

14 Timing Mismatch Detection from Error Rate Calculation S0 selects 1 st clk period, S1 selects 2 nd, and so on Error rate is calculated for each selection 14

15 Timing Mismatch Detection from Error Rate Calculation Error rate Error rate In-situ time domain measurement of phase mismatch in MDLL 15

16 Outline Background: PLL vs. MDLL Reference Spur Cancellation In-situ Reference Spur Detection 65nm Test Chip Architecture Measurement Results Conclusion 16

17 Proposed MDLL Architecture Fractional FD 5 5:1 Sel. logic FRAC<1:0> INT<7:0> Frequency locking path Edge counter 10 ʃ LDO Phase locking path REF D Q CK 1-bit SSPD K F DLF K I K P ʃ Ref. injection path ΔΣ S 0 -S 4 5 OUT Spur cancellation circuit FLL 6 ʃ Zerooffset APD MDLL operation sequence Spur PLL cancellation One time operation MDLL REF Sel. logic In-situ time domain mismatch detection D OUT 17

18 Frequency Locking Fractional FD 5 5:1 Sel. logic FRAC<1:0> INT<7:0> Frequency locking path Edge counter 10 ʃ LDO REF D Q CK K F K I K P ʃ ΔΣ OUT S 0 -S 4 5 FLL 6 ʃ Zerooffset APD MDLL operation sequence Spur PLL cancellation MDLL REF Sel. logic In-situ time domain mismatch detection D OUT 18

19 Phase Locking 5 5:1 Sel. logic FRAC<1:0> INT<7:0> Edge counter 10 ʃ LDO Phase locking path REF D Q CK 1-bit SSPD K F DLF K I K P ʃ ΔΣ OUT S 0 -S 4 5 FLL 6 ʃ Zerooffset APD MDLL operation sequence Spur PLL cancellation MDLL REF Sel. logic In-situ time domain mismatch detection D OUT 19

20 Spur Cancellation 5 5:1 Sel. logic FRAC<1:0> INT<7:0> Edge counter 10 ʃ LDO REF D Q CK 1-bit SSPD K F DLF K I K P ʃ ΔΣ OUT S 0 -S 4 5 FLL 6 ʃ Zerooffset APD MDLL operation sequence Spur PLL cancellation MDLL REF Sel. logic In-situ time domain mismatch detection D OUT 20

21 Reference Injection 5 5:1 Sel. logic FRAC<1:0> INT<7:0> Edge counter 10 ʃ LDO REF D Q CK 1-bit SSPD K F DLF K I K P ʃ Ref. injection path ΔΣ OUT S 0 -S 4 5 FLL 6 ʃ Zerooffset APD MDLL operation sequence Spur PLL cancellation MDLL REF Sel. logic In-situ time domain mismatch detection D OUT 21

22 Key Design Features Subsampling 1-bit phase detector for in-band noise reduction Fractional-N MDLL by periodic rotation of multiple DCO phases Phase mismatch cancellation loop with zerooffset aperture phase detection In-situ phase mismatch detection in time domain 22

23 Reference Realigned DCO Fine<9:0> Distributed switched capacitor elements... Φ0 0 1 S0 Φ3 0 1 S Φ2 0 1 S2 x1024 x16 REF 0 1 Enable MDLL Replica path Replica path matches the rise time of injected reference and DCO phase Frequency (MHz) 23

24 Outline Background: PLL vs. MDLL Reference Spur Cancellation In-situ Reference Spur Detection 65nm Test Chip Architecture Measurement Results Conclusion 24

25 Measured Error Rate for Mismatch Detection 25

26 MDLL Fractional Spur Spurs at the multiple of f REF /5 are cancelled by the cancellation circuit 26

27 Measured Output Spectrum and Phase Noise Output Spectrum Phase Noise Input frequency 87.5MHz, output frequency GHz MDLL shows 9dB lower noise than PLL at 100kHz offset 27

28 Performance Comparison Table This Work [6] ISSCC 15 [1] ISSCC 14 [3] ISSCC 12 Architecture MDLL Soft IL-PLL MDLL IL-PLL Process 65nm 65nm 65nm 65nm Output frequency /Range (GHz) Ref. frequency (MHz) /( ) /( ) /( ) /( ) Power (mw) Intg. RMS jitter (ps) 2.8 (0.39%) (10kHz 10MHz) 3.6 (0.55%) (1kHz 100MHz) 1.4 (0.23%) (30kHz 30MHz) 8 (0.46%) (100Hz 40MHz) FoM* (db) Area (mm 2 ) *FoM=20log(σ/1s)+10log(P/1mW) 28

29 Die Photo and Result Summary PLL MDLL Technology CMOS 65nm, 1.2V Output frequency Integer: 1.4GHz Fraction: GHz Frequency range GHz DCO type 5-stage ring oscillator In-band PN Integer Fraction Integ. RMS jitter (10kHz-10MHz) Power (mw) FOM (db) Area Integer 8.1ps 2ps Fraction 11.7ps 2.8ps DCO 4.5 Total 8.0 Integer Fraction Core 180µm x 300µm Total 300µm x 400µm 29

30 Conclusion Subsampling fractional-n all-digital MDLL designed in 65nm CMOS Zero-offset aperture phase detector based spur cancellation circuit is implemented for reference and DCO phase alignment First in-situ detection circuit to measure the mismatch between reference and DCO phase in time domain MDLL measurement result shows 9dB lower phase noise than PLL at 100kHz offset 30