A Wide-Bandwidth 2.4GHz ISM Band Fractional-N PLL with Adaptive Phase Noise Cancellation. Outline

Transcription

1 A Wide-Bandwidth 2.4GHz ISM Band Fractional-N PLL with Adaptive Phase Noise Cancellation Ashok Swaminathan,2, Kevin J. Wang, Ian Galton University of California, San Diego, CA 2 NextWave Broadband, San Diego, CA Outline Phase-Noise Canceling Phase-locked loops Adaptive Phase-Noise Cancellation Circuits Experimental Results Conclusion

2 Reference Oscillator frequency: f ref Fractional-N PLL Tradeoff PFD and C2 R C v ctrl (t) VCO frequency: (N+ ) f ref Digital Modulator N + y[n] y[n] Loop Filter Tradeoff: Widening the loop BW greatly increases phase noise: Digital Logic A pity, because it also: reduces PLL settling time reduces sensitivity to VCO pulling enables an on-chip loop filter enables in-loop transmit modulation dbc/hz 2 Fractional-N Phase Noise Reference Oscillator frequency: f ref PFD and R C 2 C v ctrl (t) Loop Filter Residual noise in v ctrl (t): N + y[n] Digital Modulator Digital Logic y[n] Each CP pulse is mostly quantization noise But the quantization noise is known, so it can be cancelled with a 3

3 Phase Noise Cancellation i (t) Residual noise in v ctrl (t) Reference Oscillator frequency: f ref PFD and i cp(t) i (t) Current C2 R C v ctrl (t) VCO frequency: (N+ ) f ref N + y[n] Loop Filter Digital Modulator Digital Logic e y[n] [n] z z e cp [n] The cancels most of the quantization noise prior to loop filter so PLL bandwidth need not be small 4 Result of Gain Error i (t) Residual noise in v ctrl (t) Ideally, residual noise in v ctrl is zero except during CP and pulses gain error spoils this result Increased phase noise! Each halving of f ref increases the required matching accuracy by 9 db! 5

4 Prior Adaptive Calibration PFD and i (t) Current e cp[n] R C C2 Loop Filter v ctrl (t) I bias sgn{e cp [n]} A Sign-LMS algorithm adjusts I bias until gain is correct Term proportional to e cp [n] remains in v ctrl if cancellation is not perfect Since sgn{e cp [n]} e cp [n] = e cp [n], integrator ramps up or down until I bias is adjusted properly 6 What s the Catch? PFD and i (t) Current e cp [n] R C C2 Loop Filter v ctrl (t) db I bias sgn{e cp [n]} v ctrl can have a large DC component (it sets the VCO freq) Hence, the LMS loop contains a large sgn{e cp [n]} term But sgn{e cp [n]} contains large spurious tones To suppress the tones, the LMS loop BW must be very low Very slow calibration settling, e.g., s in prior art 7

5 Proposed Adaptive Calibration Idea: Split the VCO s varactor into 2 parallel halves; use the common-mode voltage to control the VCO and the differential-mode voltage to control the calibration loop VCO is controlled by its common-mode input voltage, but is insensitive to differential-mode voltage The differential-mode voltage is now available to independently control calibration loop 8 Proposed Adaptive Calibration Cont. C2/2 C/2 PFD/ C/2 2R 2R VCO sgn{ecp[n]} C2/2 Current I bias g m Two parallel half-sized loop filters and varactors create differential signal path for calibration loop Multiplication by ± performed by current steering Calibration feedback loop is DC-free 9

6 The Calibration Loop Signal Path C2/2 icp+i C/2 2R icp i sgn ecp [ n] C/2 2R sgn{ecp[n]} C2/2 I bias g m The calibration loop is controlled by a differential-mode signal that has no DC component Calibration signal does not have to be filtered out by the calibration loop Can have a wide calibration loop BW! 0 The PLL Signal Path The VCO output is insensitive to calibration signal Calibration does not affect operation of PLL!

7 2 MHz Block Diagram of PLL IC v ref PFD and N+ y[n] i cp i -b I- Bank C/2 C/2 I bias C2/2 2R 2R C2/2 g m VCO 6 6 2nd-Order Digital Modulator 3 y[n] 9 e [n] z z Pseudo-Random Number Generator 8 sgn{ } Integrated Circuit 8 Dithered 0 e cp[n] Quantizer 26 Segmented DEM Encoder 2 MHz Digital Logic PLL output GHz; PLL Bandwidth is 730kHz 2 A Side-Effect of Wideband PLLs If PLL BW is increased, must decrease CP noise to maintain same out-of-band performance Example: Case : PLL BW is 00kHz Case 2: PLL BW is 500kHz but CP current sources are 64 larger than in Case to reduce CP noise dbc/hz PLL Phase Noise from CP Only Same out-ofband performance CP current consumption becomes significant as PLL loop BW is increased Hz 3

8 Dynamic CP Biasing to Save Current The CP pulses are on for only a fraction of the reference period, so the CP itself only consume 50 ua on average But if the CP bias is left on for the whole reference period, it consumes ma! By powering down the bias circuitry between CP pulses, the average current consumption is reduced by over 8 ma (circuit details on next slide) 4 CP & Bias Circuit Details en en 2 en en 2 en 2 en 2 sgn e [ n] cp en en and en 2 are high during CP pulse Cascode transistors switch pulses between loop filter halves 5

9 Cancellation Structure Segmented dynamic element matching used to eliminate harmonic distortion from non-ideal weights and pulse shapes (extension of that in [Chan & Galton, ISSCC 06]) 6 Segmented DEM Encoder Segmented DEM Encoder S, S,2 MSB xk,[n] sk,[n] /2 S k, : k = 5, 6,..., 9 S2, S,3 S4, S3, S2,2 S,4 dk[ n], if x,[ ] even,[ ] k n qk n, else S3,2 S2,3 S,5 S2,4 S,6 xk, r[n] sk,r[n] /2 d[n] d2[n] S6, S5, S,7 S,8 S,9 S,0 /2 S k, r : k =,...,4, r =,..., 3 dk [ n], if x, [ ] odd, [ ] kr n skr n 0, else d9[n] x[n] S9, S8, S7, S, S,2 S,3 LSB d [n],..., d 9 [n] are pseudo-random independent, white ± sequences 7

10 -bit Circuit Details 32 -bit Enp x[n] 0 Segmented DEM Encoder 32 -bit 32 -bit 6 -bit 6 -bit 8 -bit 8 -bit 4 -bit 4 -bit 2 -bit 2 -bit -bit -bit i(t) From Bias Enn -bit To Loop Filter M and M 2 used to minimize injection of channel charge into loop filter Separate connected to each loop filter i (t) 8 injection error Additional Circuit Details Divider: Pulse-swallowing 2/3 dividers; 2 stages CML, 5 stages CMOS VCO: g m CMOS LC; coarse switched-capacitor tuning in 2MHz steps Calibration loop op-amp: folded-cascode; 67dB DC gain, 28MHz UGBW Loop Filter: On-chip; Poly and MiM capacitors; poly resistors with coarse tuning to account for PVT shift Digital: 0.8 m standard cell library 9

11 Die Photograph 2.2 mm Loop Filter VCO & Buffers Cal. Circuit Divider Digital PFD & CP Xtal 2.2 mm 20 Measured Phase Noise Disabled Enabled Calibration Enabled 2

12 Calibration Loop Settling 35 s 22 Spurious Performance 66 db (Fractional Spur) 55 db (Reference Spur) 23

13 Performance Table Design Details Technology TSMC 0.8 m P6M CMOS Package and Die Area 32 pin TQFN, mm 2 Reference Frequency 2 MHz Output Frequency GHz Loop Bandwidth > 730 khz Measured Core Current Consumption (at.8v) VCO and Divider Buffer 6.9 ma Divider 5.8 ma CP (dynamic biasing enabled) 2.7 ma Digital 0.5 ma 20.9 ma 3.6 ma Calibration.4 ma Measured Worst Case Integer-N Performance Phase 00 khz 04 dbc/hz Phase 3 MHz 26 dbc/hz Reference Spur 55 dbc Measured Worst Case Performance with and Calibration Disabled Phase 00 khz 88 dbc/hz Phase 3 MHz 9 dbc/hz Fractional 3 MHz 45 dbc Reference Spur 52 dbc Measured Worst Case Performance with and Calibration Enabled Phase 00 khz 0 dbc/hz Phase 3 MHz 24 dbc/hz Fractional 3 MHz 62 dbc Reference Spur 53 dbc 24 Conclusion Have presented an adaptive calibration technique that solves the path matching problem in phasenoise cancelling fractional-n PLLs and avoids the slow settling problem Have demonstrated the technique in a fractional- N PLL IC, which, compared to relevant prior art, has the lowest reference frequency, f ref (2 MHz) the highest reported BW/f ref (730 khz/2 MHz) significantly lower calibration settling time 25