A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5 GHz Wireless LAN Receiver. Hamid Rategh

Transcription

1 A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5 GHz Wireless LAN Receiver Hamid Rategh Center for Integrated Systems Stanford University

2 OUTLINE Motivation Introduction to wireless LAN Synthesizer architecture Synthesizer building blocks Summary and conclusion

3 MOTIVATION Large demand for wideband wireless LAN systems 20+ Mb/s data rate Low cost Low power New released frequency band Unlicensed national information infrastructure (U NII) band

4 GOAL Design a 5 GHz frequency synthesizer for a U NII band wireless LAN receiver (HIPERLAN compatible). Implement in CMOS. Minimize power consumption.

5 FREQUENCY OF OPERATION HIPERLAN U-NII GHz 23.5 MHz GHz

6 HIPERLAN/1 STANDARD» Class A Class B Class C Transmitter power +10 dbm +20 dbm +30 dbm Receiver sensitivity -50 dbm -60 dbm -70 dbm Maximum signal level -25 dbm Modulation GMSK (BT=0.3) Data rate 20 Mb/s Topology multihop ad hoc Carrier switching time 1ms Channel bandwidth 23.5 MHz

7 HIPERLAN MULTIHOP ad hoc topology Forwarder

8 RECEIVER ARCHITECTURE f rf= GHz + Σ - I LNA LO1=f rf x 16 1 LO2=LO1x Σ + Q Weaver architecture. Frequency Synthesizer Requires quadrature LO s to reject the image signal.

9 TYPICAL PLL BASED FREQUENCY SYNTHESIZER f ref PFD Loop Filter VCO f =Mf ref out M Channel Selection Reference is a crystal oscillator. f out = M f ref Multiple LO frequencies are generated by changing M. Frequency dividers are power hungry. Their power consumption increases with frequency.

10 PROPOSED PLL ARCHITECTURE f ref PFD Charge Pump Loop Filter VCO f out f ref =11 MHz f o = GHz M 1 2 Tracking ILFD 8 channels M= N=8 Program & Pulse Swallow Counters Channel Select Prescaler N/N+1 Modulus Control

11 INJECTION LOCKING By impressing an oscillator with an external (incident) signal, frequency locking can be achieved. i First-harmonic injection locked oscillators = ( 1). f o f Subharmonic injection locked oscillators ( ). f i = 1 N o f Superharmonic injection locked oscillators ( f i f o = N ). Injection locked frequency dividers (ILFDs).

12 ILFD SIMPLIFIED PICTURE ω i ω i 2 e f(e) = e ω i ω i 2 u, 2ω, 3 2 i ω i Η(ω) ω i 2 Intermodulation of the input and output is the base of frequency division in an ILFD. An ILFD is an oscillator with perturbed oscillation. Oscillation conditions should be satisfied in the presence of the incident signal.

13 f(e) = a 0 + a 1 e + a 2 e 2 + a 3 e 3 SPECIAL CASE (DIVIDE BY TWO) Condition 1: j! j < j H 0a 2 V i 2Q j ; H 0 r! Condition 2: = LQ! r Q Q = L! r 0 (a H a 3V 2 i + a 2 V i cos(ffi)) < 1 2

14 TRACKING ILFD VCO Tracking ILFD V i 1 2 V o V c Locking range extension

15 DIFFERENTIAL TRACKING ILFD Vdd 0.24 μm CMOS Vdd=1.5 V I bias =300 μa + Vout Vc f o =2.45 GHz f i =4.9 GHz R2 M2 M4 Vx M3 M1 R1 I bias Vin

16 INDUCTOR DESIGN (ILFD) Maximum locking range ) maximize L Minimum power consumption ) maximize LQ

17 INDUCTOR DESIGN Cs Cp1 L Rs Cp2 OD Rsi Csi Csi Rsi w Sub Design parameters: w: metal width s: metal spacing OD: outer dimension n: number of turns s

18 INDUCTOR DESIGN (ILFD) In planar spiral inductors maximizing L does not maximize LQ maximize L for a given LQ +

19 ILFD FREE RUNNING OSCILLATION μm CMOS Vdd=1.5 V I bias =300 μa f =110 MHz (5%) V c =2 V Output frequency (MHz) Control voltage (V)

20 ILFD LOCKING RANGE/POWER CONSUMPTION 0.24 μm CMOS Vdd=1.5 V f o =2.45 GHz f i =4.9 GHz f =1 20%) Input referred locking range (MHz) Vc=1.5V Vc=2.0V Power (mw) Power= Incident amplitude (V)

21 PHASE NOISE MEASUREMENT TEST SETUP Vdd HP8563E 50 V i DILFD Ext. Amp. On chip

22 ILFD PHASE NOISE 0.24 μm CMOS Vdd=1.5 V f o =2.45 GHz f i =4.9 GHz Phase noise (dbc/hz) HP83732B Free running Middle freqeuncy Edge frequency Offset frequency (khz)

23 Die area mm 2 ILFD SUMMARY ß ß ß Frequency of operation 5 GHz Output frequency tuning 110 MHz 5% Input referred locking range 600 MHz 0.55 mw 1000 MHz 0.8 mw Technology 0.24 μm CMOS Flipflop based divider (for comparison) 0.24 μm CMOS(simulation) 5mW@5GHz 0.1 μm CMOS [1] GHz [1] Razavi et al., JSSC Vol. 30, No.2, pp , Feb. 1995

24 M = PN + S N = 8; P = 26; S = 12:::19; M = 220:::227 PROGRAMMABLE FREQUENCY DIVIDER Prescaler Program Counter f in N/N+1 P f out M Modulus Control S Reset Swallow Counter Channel Selection One output cycle = + 1)S + (P S)N = PN + S input cycles. (N

25 PRESCALER (Ξ 8/9) MC In MC Clk 2/3 Q Clk 2 Q Clk 2 O1 Q Out MC D Q FF2 Clk Q D Q FF1 Clk Q Q Clk

26 NOR/FLIPFLOP IMPLEMENTATION Vdd Vdd R R R R Q Q A B A B B A Clk Clk I bias

27 PROGRAM AND PULSE SWALLOW COUNTERS Program Counter (P=26) R Q T-FF Clk Q R Q T-FF Clk Q R Q T-FF Clk Q R Q T-FF Clk Q R Q T-FF Clk Q Reset Out clk Ch1 Ch2 Ch3 Ch4 Ch5 Reset D Q FF1 R Clk Q Q D FF2 Q Clk clk Swallow Counter (S=1,2,...,24) S=1,2,...,24 MC clk

28 PHASE/FREQUENCY DETECTOR U R D Q FF1 Clk Q Reset U i U D V Reset D Q FF2 Clk Q D i D Output stage

29 CHARGE PUMP AND LOOP FILTER Wp Wp U Wp M3 I Up M4 U Vdd vco M7 M8 C1 C2 C3 Vr O n 1 O p R1 R3 Vc M5 M6 Loop filter M1 D Wn 2Wn Wn M2 I Down D Replica bias Feedback network Charge pump

30 CHARGE PUMP CURRENT MATCHING <0.05% I I» V 0.25» V O 1.75 V <2% I I» V 0.1» V O 1.8 V (Id Iu)/Id* Vo (V)

31 LOOP FILTER PLL order 2 nd order 3 rd order 4 th order # Poles Independent design variables: 1) Phase margin 2) Loop bandwidth 3) Spur attenuation p p p p p p p

32 b = C 1 C +C 3 2 p c ß 1+b R C W 1 1 LOOP FILTER DESIGN (4 th ORDER PLL) 100 open loop transfer function R 3 C 3 fi R 1 (C 2 + C 3 ) Magnitude (db) p 1 ) 1+b 100 PM ß tan 1 ( p 1 + b) tan 1 ( Phase (degree) t s = f 2(PM) W c R 3 C 3 sets the spur attenuation In Frequency (Hz) R3 Out R1 C1 C2 C3

33 t s LOOP PARAMETERS Parameter Value 360 MHz/V (Average) K vco 500 MHz/V (Max) I p 3 μa 42 pf C 1 C 2 C 3 R 1 R pf 2.2 pf 170 kω 64.5 kω In R3 Out R1 C1 C2 C3 W c f ref ffi khz -45 db 35 μs < PM

34 LOOP FILTER NOISE L=-149 Phase noise (dbc/hz) noise of R1 noise of R3 total noise Offset frequency (Hz)

35 VOLTAGE CONTROLLED OSCILLATOR Vdd I bias 0.24 μm CMOS Vo Vc I1p I1m Vdd=1.5 V M7 M3 M4 M8 Vo2 I1=I1p-I1m f o =4.9 GHz Vdd Vo1 I bias =4.0 ma I bias Vo Vc I2p I2m -Vo2 I2=I2p-I2m M5 M1 M2 M6

36 INDUCTOR DESIGN (VCO) Maximum Q ) minimum inductor noise If inductors are not the main source of noise, maximum LQ ) Maximum oscillation amplitude for a given bias current. Minimum phase noise due to active devices.

37 VCO FREQUENCY TUNING 0.24 μm CMOS Vdd=1.5 V I bias =4.0 ma f =550 MHz (11%) ( max=500 MHz/V ) df dv Frequency (GHz) Control voltage (V)

38 PLL PHASE NOISE L=-134 Phase noise (dbc/hz) Offset frequency (Hz)

39 SPECTRUM OF THE SYNTHESIZED OUTPUT Power (dbm) Frequency (GHz)

40 SYNTHESIZER CHIP MICROGRAPH 0.24 μm CMOS Tracking ILFD Prescaler area=1.45 mm 2 (1 mm 1.45 ) 2 VCO PFD Counters Loop Filter Charge Pump Bias

41 Die area 1:45 mm 2 SUMMARY Synthesized frequencies Reference frequency Spurs Phase noise Loop bandwidth Settling time GHz 4:840 4:994 MHz dbc < 22MHz 134 khz 60 < 35 μs Power dissipation VCO ILFD Prescaler Digital+Bias Circuits Total Supply voltage Implementation mw 12 mw 1 mw 6:6 mw 2 mw 21:6 V (analog) 1:5 V (digital) 2:0 Technology 0:24 μm CMOS

42 f f COMPARISON [1] kHz dbc [2] MHz [3] MHz dbc [4] MHz dbc This work MHz dbc FM = f L P 5GHz 22MHz [1] J. Parker et al. A 1.6GHz CMOS PLL with On chip loop filter JSSC Vol 33 Mar 98. PN n = PN + 20 log [2] J. Craninckx et al. A Fully Integrated CMOS DCS 1800 Synthesizer JSSC Vol 33 Dec 98. [3] A. Shahani et al. Low Power Dividerless Frequency Synthesis... JSSC Vol 33, Dec 98. [4] C. Lam et al. A 2.6GHz/5.2GHz Frequency Synthesizer in a 0.4μm CMOS Technology, VLSI 99.

43 CONCLUSION A 5GHz frequency synthesizer is fully integrated in 0.24μm CMOS. Power consumption is reduced significantly by: employing a tracking ILFD. optimizing spiral inductors for the VCO and ILFD. current sharing in the prescaler. Loop filter noise is kept small by using reasonably small resistors. A spurious free output is achieved by: using a semi differential charge pump with well matched currents. minimizing the skew of the PFD complementary outputs. designing a fourth order loop.

44 CONTRIBUTIONS Developing a general theory for injection locked oscillators. Developing design techniques for very low power ILFD s with a wide locking range. Introducing the tracking ILFD. Designing a very low power and fully integrated CMOS frequency synthesizer at 5 GHz. Developing a very simple loop filter design recipe for third and fourth order PLL s. Demonstrating the operation of analog CMOS circuits with a sub 2 V supply.

45 ACKNOWLEDGMENTS National Semiconductor Stanford Graduate Fellowship Program Tektronix Conexant