A 1.2-to-1.4 GHz low-jitter frequency synthesizer for GPS application

Transcription

1 Journal of Chongqing University (English Edition) [ISSN ] Vol. 12 No. 2 June 2013 doi: /j.issn To cite this article: HU Zheng-fei, HUANG Min-di, ZHANG Li. A 1.2-to-1.4 GHz low-jitter frequency synthesizer for GPS application [J]. J Chongqing Univ: Eng Ed [ISSN ], 2013, 12(2): A 1.2-to-1.4 GHz low-jitter frequency synthesizer for GPS application HU Zheng-fei, HUANG Min-di, ZHANG Li Institute of Science, Nanjing University of Posts and Telecommunications, Nanjing , P. R. China Received 4 January 2013; received in revised form 25 April 2013 Abstract: A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS (complementary metal-oxide semiconductor) technology is proposed in this paper. The frequency synthesizer uses a novel singleend gain-boosting charge pump, a differential coupled voltage controlled oscillator (VCO) and a dynamic logic phase/frequency detecor (PFD) to acquire low output jitter. The output frequency range of the frequency synthesizer is up to MHz to MHz for GPS (global position system) application. The post simulation results show that the phase noise of VCO is only dbc/hz at a 1 MHz offset and the Vp-p jitter of the frequency synthesizer output clock is ps. The power consumption of the frequency synthesizer not including the divider is 4.8 mw for 1.8 V supply and it occupies a 0.8 mm 0.7 mm chip area. Keywords: frequency synthesizer; phase-locked loop; voltage controlled oscillator; phase/frequency detector; charge pump CLC number: TN962 Document code: A 1 Introduction a With the development of the communication industry, especially the rapid development of the wireless communication and optical communication, the frequency synthesizer of phase-locked loop (PLL) type becomes a basic and important module in analog and digital-analog mixed circuits. It can track the variation of the phase and frequency of the input signal and produce low-jitter clock signal, and it is widely used in a variety of applications including clock generation and skew compensation in microprocessors, clock and data recovery systems, and communication systems [1-5]. A typical block diagram of the frequency synthesizer in charge-pump PLL type is shown in Fig. 1. The PLL HU Zheng-fei ( 胡正飞 ): njhuzf@163.com. Funded by the Communication System Project of Jiangsu Provincial Education Committee under grant No.JHB contains phase/frequency detector (PFD), charge pump (CP), low pass filter (LPF), voltage control oscillator (VCO) and frequency divider modules. The PFD measures the phase/frequency difference between the input reference and the VCO output. Based on this difference, the PFD produces up and down pulses to later charge pump module. Depending on the status of these pulses, the CP sinks or sources current pulses into the loop filter whose low-pass output controls the output frequency of the VCO. Then, the outputs of VCO go through the programmable frequency divider and are fed back to the PFD input terminal to be compared with the input reference again. After a certain number of cycles, the whole loop will be locked in integral times of the reference frequency. A kind of single-end gain-boosting CP circuit which can accurately match the charge and discharge currents is proposed in this paper. The VCO adopts a differential coupled structure [6-7] which is able to reduce the effect of common-mode noise, such as the magnitude of current spikes injected to power supply and substrate, and ultimately the reduce jitter 97

2 generation. The PFD and D-type flipflop adopt true single phase clock (TSPC) logic structure which has no static power consumption and has low dynamic power consumption [8-9]. Additionally, differential buffers are used at the output of PFD and VCO to isolate the effects of loading of the subsequent blocks. Based on the standard 0.18 μm CMOS (complementary metal-oxide semiconductor) technology, the correctness of the design is verified by a series of chip design processes including schematic diagram design, pre-simulation, layout design, and post-simulation. design of the PFD to make sure that the combination of the PFD and the charge pump has a negligible deadzone. By respectively inserting two invertors at the input/output stage in Fig. 2, the dead-zone can be eliminated. The schematic of the D-flip flop is shown in Fig. 3. The structure is very simple of only six transistors. It has no static consumption and has low dynamic power consumption. Fig. 1 Block diagram of the frequency synthesizer, where PFD is the phase/frenquency detector, VCO the voltage controlled oscillator, fr the frenquency; and N the divided frequency ratio The architecture and circuit issues of the frequency synthesizer are described in Section II. Section III presents the post simulation results and layout, and Section IV gives the layout emphasis and experimental results. The conclusions are summarized in Section V. Fig. 2 Architecture of the phase/frenquency detector, where VDD is voltage source; CLK is clock; D is data; and Q is output. 2 Architecture and circuit In order to fulfill simultaneously low jitter and lowpower consumption operation, a novel single-end gainboosting CP circuit, a differential coupled VCO, a dynamic logic PFD, and a three-order passive loop filter are proposed. 2.1 PFD One of the critical frequency synthesizer building blocks is the phase/frequency detector [10]. As shown in Fig. 2, a simple three-state logic architecture is adopted in this work. One advantage of this PFD is that it uses only the filling edges of the input reference and the feedback signal to generate output signals. Therefore, a 50% duty cycle is not necessary for this phase/frequency detector. The other advantage of this PFD is that it will not lock on harmonics, so the hold frequency range of the PLL will be large. Additionally, compared to the traditional PFD, this PFD needs fewer transistors and consumes less power, and its structure is easy to achieve. Special attention has been paid to the Fig.3 D-Flipflop, where Mp1, Mp2, Mp3, Mn1, Mn2, and Mn3 are transistors, CLK is clock, and Qn is output 2.2 CP The schematic of the single-end gain-boosting CP is shown in Fig. 4. Specifically, it makes use of the folded-cascode amplifier to constitute a negativefeedback loop that can increase the output impedance. 98 J. Chongqing Univ. Eng. Ed. [ISSN ], 2013, 12(2):

3 High output impedance can greatly reduce the effect of channel length modulation, thus making charge current and discharge current accurate matching in wide output voltage range. As shown in Fig. 4, the transistors Mp2, Mp6, Mn9, Mn6 and Mn2 constitute a folded-cascode amplifier and meanwhile the transistors Mn6 and Mn2 constitute the current-source-load of the amplifier; the same is that, the transistors Mn3, Mn7, Mp9, Mp7 and Mp3 constitute another folded-cascode amplifier and meanwhile the transistors Mp7 and Mp3 constitute the current-source-load of the amplifier. High-swingcascode current source is adopted for the purpose of reducing the effect of channel length modulation. Additionally, in order to reduce the influence of charge-sharing, the discharge path is added by the way of transistors Mp10 and Mn10. This circuit can fulfill accurate current matching with a simple structure. the influence of capacitive voltage-dividing to the Q value of the resonant circuit, a source follower is adopted to buffer the output. Meanwhile, L2, C3 and C4 constitute the noise filtering network [11]. This noise filtering network can stop the power noise into the oscillator. Fig. 5 Diagram of inductance-capacitance voltage-controlled oscillator (LC VCO), where VDD is voltage source; M1 to M4 are transistors; R1 to R4 are resistors; C1 to C4 are capacitors; L1 and L2 are inductors; VAR1 and VAR2 are variable capacitors; and Vcon is output voltage 2.4 Loop parameters Fig. 4 Single-end gain-boosting charge pump, where VDD is voltage source; Mp1 to Mp10 and Mn1 to Mn10 are transistors; R is resistor; p is up node; n is down node; Cp is capacitor; and Vcon is output voltage 2.3 VCO One of the challenging building blocks of a fully integrated frequency synthesizer is the VCO. A major design challenge for integrated VCO is to have low phase noise and a large 1.2-to-1.4 GHz tuning range for the GPS application. In this work, the differential coupled VCO structure is shown in Fig. 5. The differential coupled structure can not only meet with stable oscillator signal output, but also have nice noise suppression ability. To reduce PLL is a kind of typical negative-feedback system. The circuit parameters, including charge current and discharge current of CP, component values of LPF, gain of VCO and frequency division ratio of divider, directly or indirectly decide the circuit performance, such as the output signal jitter, phase noise, locking time, and locking range. Considering the stability and the noise performance of the loop circuit, the charge current and discharge current are designed to be 100 A, and the VCO gain is 250 MHz/V. The frequency division ratio is temporarily set to be 512. The loop bandwidth should be less than 1/10 reference clock angular frequency [12-14]. Through comprehensive consideration, the loop bandwidth is designed as 1.25 MHz. The loop filter is mainly used to filter out the high frequency component and the noise. So, in the PLL system, we adopt a lowpass filter. Specifically, we can choose a third-order filter circuit as shown in Fig. 6. The resistor R1 in J. Chongqing Univ. Eng. Ed. [ISSN ], 2013, 12(2):

4 series with capacitor C1 of the loop filter produces some ripple at the output of the loop filter that can cause cycle-to-cycle jitter. As a common practice to reduce this effect, the capacitor C 2 is added in parallel with the RC filter. Additionally, R2 and C3 are added to avoid the control-voltage-overshoot. The loop is characterized by its natural loop frequency n and the damping factor : IK P VCO n, (1) 2πCN 1 1 TPLL S ( ), (3) 2πf u where T PLL is the RMS jitter of the PLL output clock; f u is the PLL high pass 3 db bandwidth to the VCO phase noise; ω is the offset angular frequency and ω 0 is the center oscillation frequency of VCO. S Φ ( ω) is the VCO free running phase noise. When T PLL is 1 ps and f u is set 1.2 MHz, ω 0 is 1.2 GHz, the phase noise of the VCO can be calculated as less than 110 dbc/hz at 1 MHz. 0 ξ R1 I C1K 2 2πN P VCO, (2) where I P is the charge pump current, and K VCO is the gain of the VCO. Fig. 6 The third-order filter Through calculation and simulation, the parameters of the low-pass filter are as follows: R1=26 kω, R2=20 kω, C1=80 pf, C2=5 pf, and C3=3 pf Fig. 7 The Logic function of phase/frequency detector, where V is voltage 3 Post simulation results The circuit is designed and simulated in SMIC 0.18 μm CMOS technology using Cadence RF. Meanwhile, the complete frequency synthesizer including the loop filter has been laid out by using Cadence Virtuoso. As shown in Fig. 7, the logic function of PFD is correct. Its dead-zone is eliminated well. Fig. 8 shows that the charge current and discharge current are matching well. When the voltage output range is 0.3 V to 1.6 V, the mismatch between the charge current and discharge current is 0.2 μa, and the mismatch proportion is only 0.2%. It almost reaches the ideal matching degree. The suggested integrated RMS jitter for 1.2 GHz LC-VCO-based GPS PLL from 10 khz to 10 MHz is about 1 ps to 2 ps. Fig. 8 Charge pump current match, where I p is current and V is voltage As can be seen from Figs. 9 and 10, the tuning range of the VCO is from MHz to Hz which covers the desired frequency synthesizer lock range. The open-loop phase noise is dbc/hz at 1 MHz, dbc/hz at 100 khz and 85.97dBc/Hz at 10 khz, respectively, which is satisfied with the specification of the GPS application. 100 J. Chongqing Univ. Eng. Ed. [ISSN ], 2013, 12(2):

5 The output clock waveform of the PLL is shown in Fig. 11. The Vp-p jitter of the PLL output clock is 13.65ps. Eq.(4) converts peak-to-peak jitter into RMS jitter for a given BER. PP jitter =N*RMS jitter, (4) N From BER erfc( ), N is when BER is to 5. So the RMS jitter is smaller than 2 ps, which accords with the suggested specifications. Finally, the locked state is shown in Fig. 12. The layout of the complete frequency synthesizer is shown in Fig. 13, with a chip area of 0.8 mm 0.6 mm. The performance summary and comparison with other GPS frequency synthesizer is shown in Table 1. Fig. 11 Output clock waveform of phase-locked loop Fig. 9 Tuning curve of the voltage controlled oscillator, where V is voltage Fig. 12 Lock state of the phase-locked loop, where V is voltage Fig. 10 Open-loop phase noise Fig. 13 Layout of the frequency synthesizer Table 1 Performance summary and comparison Research CMOS technology Supply voltage/v Output frequency/ghz Phase noise of VCO Power consumption/mw This work 0.18 m to dbc/hz at 1 MHz 4.8 Ref. [15] 0.18 m to dbc/hz at 1 MHz 5.6 Ref. [16] 90 nm to dbc/hz at 10 MHz 3.99 J. Chongqing Univ. Eng. Ed. [ISSN ], 2013, 12(2):

6 4 Conclusions A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS technology is proposed in this paper. The PLL uses a novel single-end charge pump, a differential coupled VCO and a dynamic logic PFD to fulfill lower noise and lower power simultaneously. The open-loop phase noise is dbc/hz at a 1 MHz offset and the Vp-p jitter of the locked PLL output clock is only ps. The frequency synthesizer occupies 0.8 mm 0.7 mm, and consumes 4.8 mw for 1.8 V supply. References [1] Liu YW, Wang ZG, Li W, GHz 0.25 m CMOS low-power phase-locked loop [J]. Chinese Journal of Semiconductor, 2006, 27(12): [2] Herzel F, Fischer G, Gustat H, et al. An integrated cmos pll for low-jitter applications [J]. IEEE Transactions on Circuits and Systems, 2002, 49(6): [3] Chen YM, Wang ZG, Zhang L. Low-jitter PLL based on symmetric phase-frequency detector technique [J]. Analog Integrated Circuits and Signal Processing, 2010, 62(1): [4] Kim DH, Kang JK. Clock and data recovery circuit with two exclusive-or phase frequency detector [J]. Electronics Letters, 2000, 36: [5] Lai YJ, Lin TH. A 10-GHz CMOS PLL with an agile VCO calibration [J]. Asian Solid-State Circuits Conference, 2005(11): [6] Tiebout M. Lower-power lower-phase-noise differentially tuned quadrature VCO design in standard CMOS [J]. IEEE Journal of Solid-State Circuits, 2001, 36(7): [7] Hsieh HHg, Hsu YC. A 15/30-GHz dual-band multiphase voltage-controlled oscillator in m CMOS [J]. IEEE Transaction on Microwave and Techniques, 2007, 55(3): [8] Guo XJ, Yin JH, Song MX, et al. Design of a gain boosting charge pump for phase-locked loops [J]. Microelectronics & Computer, 2009, 26(12): [9] Soliman S, Yuan F, Raahemifar K. An overview of design techniques for CMOS phase detectors [J]. IEEE International Symposium on Circuits and Systems, 2002, 5: V457-V460. [10] Liu RF, Li YM, Chen HY. A fully symmetrical PFD for fast locking low jitter PLL [J]. ASIC, Proceedings. 5th International Conference, 2003, 2: [11] Chen YM, Wang H, Yan SC, et al. A 10GHz multiphase LC VCO with a ring capacitive coupling structure [J]. Science China Information Sciences, 2012, 55(11): [12] Tao HB, Zhang PZ, Shao ZC. 1.8V CMOS low noise cppll design, electron devices and solid-state circuits [J]. IEEE International Conference, 2009(1): [13] Savoj J, Razavi B. A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency [J]. IEEE Journal of Solid-State Circuits, 2003, 38(1): [14] Gierkink SLJ, Li DD, Frye RC, et al. A 3.5-GHz PLL for fast low-if/zero-if LO switching in an transceiver [J]. IEEE Journal of Solid State Circuits, 2005, 40: [15] Jia HL, Ren T, Lin M, et al. A 5.6-mW power dissipation CMOS frequency synthesizer for L1/L2 dual-band GPS application [C]. In: International Conference on Solid-State and Integrated-Circuit Technology, Beijing, October 20-23, [S.l.:s.n.], 2008: [16] Hwang IC. A mm 2, 3.99 mw fully integrated 90 nm CMOS L1/L5 GPS frequency synthesizer using a regulated ring VCO [J]. IEEE Microwave and Wireless Components Letters, 2012, 22(6): J. Chongqing Univ. Eng. Ed. [ISSN ], 2013, 12(2):