Design of a 3.3-V 1-GHz CMOS Phase Locked Loop with a Two-Stage Self-Feedback Ring Oscillator

Transcription

1 Journal of the Korean Physical Society, Vol. 37, No. 6, December 2000, pp Design of a 3.3-V 1-GHz CMOS Phase Locked Loop with a Two-Stage Self-Feedback Ring Oscillator Yeon Kug Moon Korea Advanced Institute of Technology, ARALION Inc., Seoul Kwang Sub Yoon Department of Electronic Engineering, Inha University, Inchon Chang Ho Han Department of Computer Science and Engineering, Inha University, Inchon (Received 12 April 2000) A 3.3-V PLL (phase locked loop) is designed for high-frequency, low-voltage, and low-power applications. This paper proposes a new PLL architecture to improve the voltage-to-frequency linearity of a VCO (voltage controlled oscillator) with a new delay cell. The proposed VCO operates in a wide frequency range of 30 MHz 1 GHz with good linearity. The DC-DC voltage up/down converter is newly designed to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6-µm n-well CMOS process. The simulation results show a locking time of 2.6 sec at 1 GHz, a lock in range of 100 MHz 1 GHz, and a power dissipation of 112 mw. I. INTRODUCTION Phase locked loops (PLLs) are common building blocks widely used in telecommunication systems [1], such as clock recovery [2], clock synthesizer, carrier recovery, and FM demodulation circuits. The recent design trends of CMOS PLLs emphasize high operational frequency, fast acquisition time, low phase noise, a wide tuning range, and high integration. This paper proposes a 100 MHz 1 GHz lock-in range CMOS PLL with a two-stage self-feedback ring oscillator. The proposed self-feedback delay cell circuit enables us to realize a CMOS two-stage ring oscillator without a spiral inductor. Good linearity of the control voltage versus oscillation frequency is realized for MHz. ring oscillator, and a programmable 64 divider circuit. A fully differential structure for each module circuit is employed to remove common-mode noise. The proposed VCO circuit shown in Fig. 2(a) is based upon a two-stage self-feedback delay cell circuit. The circuit diagrams of the self-feedback delay cell and the buffer are shown in Fig. 2(b) and Fig. 2(c), respectively. The delay cell circuit consists of a NMOS source-coupled differential pair with PMOS loads [4](M5, M6, M10, M11, M12), a PMOS source-coupled pair with NMOS loads [3,5](M1, M2, M9, M17, M18), and active loads (M13, M14, M15, M16). The structure of the proposed delay cell to achieve a 90 of a phase shift limits the II. PLL DESIGN The proposed architecture of the PLL is shown in Fig. 1. It consists of a dead-zone free-phase frequency detector [3], a charge pump and loop filter circuit [3], a DC- DC voltage up/down converter, a two-stage self-feedback ksyoon@inha.ac.kr, Fax: Fig. 1. Block diagram of the proposed PLL

2 -804- Journal of the Korean Physical Society, Vol. 37, No. 6, December 2000 Fig. 2. Circuit diagram of (a) the ring oscillator structure, (b) the proposed self-feedback delay cell, and (c) the buffer circuit. output voltage swing of the circuit. To overcome this disadvantage, we connect the positive output node to the positive input node and the negative output node to the negative input node through selffeedback, thus increasing the gain of the self-feedback delay cell. The self-feedback delay cell has a common input node (V in and V in +) with both an NMOS source-coupled differential pair and a PMOS source-coupled differential pair to obtain a high g m and a high gain. The NMOS/PMOS source-coupled differential pair and active loads within the self-feedback delay cell are utilized to provide the sufficient gain greater than unity and a 90 phase shift. The gain loop equation of the proposed delay cell can be given as; [ ] 2 GM R T (jw) =, (1) 1 + jwrc and G M = g m2 + g m6 + g m1 + g m5, ( ) 1 R = 3 r d11g m13 r d13 // ( 1 3 r d17g m15 r d15 ), C = C gd13 + C gd (C gd8 + C gs8 + C gd4 + C gs4 ) + C db13 + C db (C gs8 + C gs4 ) + C db13 + C db15. Equations (1) and (2) should be met simultaneously to guarantee the oscillation of the proposed circuit where Fig. 3. Circuit schematic of (a) the DC-DC voltage up converter, (b) the DC-DC voltage down converter, and (c) the DC-DC converter characteristic curve. ω osc is the maximum oscillation frequency and k is an integer. [ ( ) ] 2 GM R P h = 2p k. (2) 1 + jω osc RC G M R 1 + jω osc RC 2 1. (3) Equation (3) can be obtained from Eq. (2). It can be seen from Eq. (3) that f osc up to 1.2 GHz can be achieved using the given 0.6-µm CMOS technology. 1 (1+R 2 C 2 ω osc ) 2 (G M R jg M R 2 C ω osc ) 2 1. (4) The proposed oscillator possesses a wide operating frequency range ( MHz) and tuning range ( V). In addition, the self-feedback delay cell shows a constant output characteristics of DC 1.65 V and generates full swing characteristic with a peak-to-peak output signal of over 2 V. These make it possible for the proposed ring oscillator to avoid using the replica bias circuits or the level shifters which are usually used in conventional ring oscillators.

3 Design of a 3.3-V 1-GHz CMOS Phase Locked Loop with a Yeon Kug Moon et al Fig. 4. Voltage-to-frequency characteristic curves of (a) two-stage self-feedback ring oscillator and (b) two-stage selffeedback ring oscillator with DC-DC voltage up/down converter. The DC-DC voltage up/down converter with the voltage pump circuit [6] shown in Fig. 3 is able to control the linearity of VCO s voltage to frequency characteristic. This circuit is proposed to limit eight MOS transisters (M11 M18) operating only in the linear region for purposes of widening the tuning range and making the oscillation frequency characteristic versus control voltage of the VCO linear. Using the proposed DC-DC voltage up/down converter, the output signal which goes through the buffer can hold a constant DC voltage (1.65 V) without a level shifter or an op-amp, and the effect of output swing voltage to jitter can be removed. If the DC output voltage is to be kept steady, the control voltage of the PMOS (M11-14) and the NMOS (M15-18) of the output stage should be reduced or increased on the same portion, and the MOS transistor (M11-18) should be controlled in the linear region. To make up for this, we must control the output voltage of the DC-DC voltage up converter to be between 1.75 V and 3.3 V. At the same time, the output voltage of the DC-DC voltage down converter should be controlled to be between 1.55 V and 0 V. This is implemented to reduce each V of the PMOS control voltage approximately from 1.55 V and to increase each V of the NMOS control voltage approximately from 1.75 V. Figure 4(a) and Fig. 4(b) show the voltage-to-frequency characteristic curves of the two-stage self-feedback ring oscillator and the twostage self-feedback ring oscillator with DC-DC voltage up/down converter, respectively. III. SIMULATION RESULTS AND LAYOUT Fig. 5. Pull in process characteristic of a 1-GHz operating frequency with a 125-MHz input frequency (3080-kHz loop bandwidth). Fig. 6. Pull in process characteristic of a 1-GHz operating frequency with a 125-MHz input frequency (2374-kHz loop bandwidth). Simulations of the proposed PLL circuit were performed in a standard 0.6-µm CMOS technology. Figure 5 and 6 show locking times of 2.6 sec and 4.0 sec at a 1-GHz operating frequency with a 125 MHz input frequency, for a loop bandwidth between 2.6 % (3080 khz) of input frequency and 2 % (2374 khz) of the input frequency.

4 -806- Journal of the Korean Physical Society, Vol. 37, No. 6, December 2000 Table 1. Simulation results for the designed PLL. Power Supply 3.3 V Input Locking Range 2 MHz 250 MHz Lock In Range 100 MHz 1 GHz GHz operating Locking Time frequency with 125 MHz input VCO Tuning Range 28 MHz 1040 MHz VCO Gain 404 MHz/V Supply Voltage Sensitivity 5.5 %/V Power Dissipation 112 mw Technology 0.6-µm CMOS Technology Figure 7 shows post layout simulation result and locking time of 17 sec at 768 MHz operating frequency with a 12 MHz of input frequency. Because the VCO consists of an even number of self-feedback delay cell stages, four oscillation waveforms with each 90 phase differences are obtained from each differential output node of the delay cell. The simulated oscillation frequency of the VCO ranges from 28 MHz to 1040 MHz. The slope of the characteristic curve is simulated to be 404 MHz/V. The linear frequency characteristic over Vcon is maintained between 0.2 V and 2.4 V. The simulated performance of the proposed CMOS PLL with a two-stage selffeedback ring oscillator is summarized in Table 1. Table 2 shows a summary of the performance comparison between a conventional three-stage CMOS VCO and the proposed two-stage CMOS VCO. The layout of the prototype PLL is shown in Fig. 8, and the active chip area, excluding pads, is mm. IV. CONCLUSIONS This paper presents the design of a 3.3-V, 1-GHz CMOS PLL with a two-stage self-feedback ring oscillator. The operational frequency of the designed VCO ranges from 30 MHz to 1 GHz when the input voltage ranges from 0.2 V to 2.51 V. This results in a wide input locking range and a fast acquisition time due to the high gain of the VCO and a stable operation due to a wide input voltage range. The Hspice simulation results for the designed PLL show a supply voltage sensitivity Table 2. Comparison of a three-stage VCO with the proposed VCO. Parameters Three-Stage VCO The proposed VCO Power Supply 3.3 V/5 V 3.3 V Operating Frequency N/A 1 GHz Power Dissipation >20 mw 13 mw(@1 GHz) Output Characteristic 60/stage 90/stage VCO gain N/A 404 MHz/V Fig. 7. Post layout simulation result and locking at 768MHz operating frequency with 12 MHz of input frequency. Fig. 8. Layout of the proposed PLL. of 5.5 %/V and a power dissipation of 112 mw with a 3.3-V single power supply. The input locking range of the designed PLL is MHz. ACKNOWLEDGMENTS The authors are grateful to Hyundai Electronics, Inc., and IDEC (IC Design Education Center) for fabrication of this chip. This research was supported under the contract No of the interdisciplinary research grants from KOSEF (Korea Science and Engineering Foundations). REFERENCES [1] Turgut S. Aytur and Behzad Razavi, IEEE J. Solid-State Cir. 30, 1457 (1995) [2] Joonbae Park, Wonchan Kim, An Auto-Ranging Mb/s Clock Recovery Circuit with a Time-to-Digital Converter, ISSCC Dig. Tech. Papers 350 (Feb. 1999). [3] Ian A. Young, Jeffrey K. Greason and Keng L. Wong, IEEE J. Solid-State Cir. 27, 1599 (1992). [4] Ilya Novof, John Austin, Ram Kelkar, Don Strayer and Steve Wyatt, Fully Integrated CMOS Phase-Locked

5 Design of a 3.3-V 1-GHz CMOS Phase Locked Loop with a Yeon Kug Moon et al Loop with 15 to 240 MHz Locking Range and ±50 ps Jitter, ISSCC Dig. Tech. Papers 112 (Feb. 1995). [5] Kamran Iravani and Gary Miller, VCOs with Very Low Sensitivity to Noise on the Power Supply, Proc. CICC (1998). [6] R. Jacob Baker, Harry W. Li and David E. Boyce, CMOS Circuit Design, Layout, and Simulation (IEEE Press, Piscataway, 1998).