5.5: A 3.2 to 4GHz, 0.25µm CMOS Frequency Synthesizer for IEEE a/b/g WLAN
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1 5.5: A 3.2 to 4GHz, 0.25µm CMOS Frequency Synthesizer for IEEE a/b/g WLAN Manolis Terrovitis, Michael Mack, Kalwant Singh, and Masoud Zargari 1 Atheros Communications, Sunnyvale, California 1 Atheros Communications, Irvine, California
2 Outline System Requirements Architecture and Circuit Description Measurements Conclusions
3 Design Goals Tuning Range GHz Reference Frequencies: 13.33M, 6.66M, 3.33M, 10M Drive LO Buffers at f VCO and I,Q LO Buffers at f VCO /2 Low Phase Noise Low Spurs
4 Xtal Osc Synthesizer Block Diagram Reg1 Reg2 Ref Div FF LPF PFD CP VCO f VCO 40MHz 16/17 Divider FF P & S counters 8/8.5 Div /2 Control Logic Lock Detector f VCO /4 I Q To LO Buffers
5 Design Choices Low VCO gain Good VCO phase noise Low LPF resistor noise contribution High charge pump current Low LPF resistor noise contribution Low charge pump noise
6 Voltage Controlled Oscillator (VCO) Regulated V DD (2.5V) 7-bit control C MIM C MIM V c
7 High-Frequency Divide-by-2 V DD D D q q I I D D q q Q Q s 2 s 1 L L L from VCO s 0 L q q D D H. Rategh and T. Lee Superharmonic Injection-Locked Frequency Dividers, JSSC, June clk clk
8 Adjustable Tuning Adjustable C Adjustable L R p =LωQ Equivalent parallel resistance ampl ampl freq freq
9 Multi-tap Inductors t1 t2c t2b t2a
10 Charge Pump Regulated V DD C P up up M P I BIAS +- C N dn dn Control Voltage M N Replica Bias
11 Programmable Integrated LPF V c V c R series C series C parallel
12 8/8.5 Dual Modulus Divider f VCO /2 f VCO /16 or f VCO /17 f2 I f2 I /2 Phase Multi- plexer f4 I f4 Q f4 I f4 Q /4 f2 Q f2 Q /2 State Machine div17 J. Craninckx, M. Steyaert A 1.75-GHz/3-V Dual-Modulus Divide-by- 128/129 Prescaler in 0.7-µm CMOS, JSSC, July 1996.
13 Phase Multiplexer V DD out out V DD s 0 s 0 s 2 s 2 s 4 V DD s 1 s 1 s 3 s 3 s 5 f4 I f4 I f4 Q f4 Q
14 Control Logic Successive approximation search for the 7 bits that control the VCO tuning capacitors Coarse digital alignment ofthe feedback clock with the reference clock Optimize for the control voltage value Take corrective action when the control voltage drifts out of the acceptable range or when no-lock is detected
15 Measurement Setup a Transmitter DC Input BB I BB Q GHz RF output f VCO /2 I Q f VCO 40MHz Synthesizer Measured Phase Noise at RF output is ~3.5 db higher than at the VCO frequency.
16 Output Spectrum (1) F o =5.44GHz, F ref =13.3MHz, (S=0) Power (dbm) MHz, <-75 dbc Frequency (GHz) 40MHz, <-70 dbc
17 Output Spectrum (2) F o =5.30GHz, F ref =13.3MHz, (S=9) 20 Power (dbm) F ref /2, <-64 dbc Frequency (GHz)
18 Measured Phase Noise (1) F out =5240MHz, F ref =13.3MHz Phase Noise (dbc/hz) dbc/hz -107 dbc/hz -115 dbc/hz 1K 10K 100K 1M 10M Frequency Offset (Hz)
19 Measured Phase Noise (2) F out =5240MHz, F ref =13.3MHz Phase Noise (dbc/hz) Low Loop BW dbc/hz K 10K 100K 1M 10M Frequency Offset (Hz) VCO Phase Noise: MHz offset, 5.24 GHz carrier
20 Measured Phase Noise (3) Phase Noise (dbc/hz) -90 F out =5745M, F ref =3.33M F out =5250M, F -120 ref =6.66M -130 F out =5240M, F ref =13.3M 1K 10K 100K 1M 10M Frequency Offset (Hz)
21 Technology Power Dissipation Performance Summary 0.25 µm CMOS, 1P5M, MIM capacitors 93 mw Area 1.7 mm 2 Spot Phase Noise F out = 5240MHz, F ref =13.3 MHz Integrated PN (from 1K to 10M) F out = 5240MHz, F ref =13.3 MHz F out = 5250MHz, F ref =6.66 MHz F out = 5745MHz, F ref =3.33 MHz Spurs Settling Time -105/-107/ K/100K/1M dbc (0.31 o ) dbc (0.40 o ) dbc (0.54 o ) <-64dBc <150µs
22 Synthesizer Micrograph High Freq 8/8.5 Div-by-2 Div VCO Regulator VCO CP LPF Control Logic CP Regulator
23 Conclusions Fully integrated, wideband, 0.25µm CMOS synthesizer Excellent phase noise, spur performance and settling time Design highlights: On-chip voltage regulation Tuning with switching inductors Low noise VCO Charge pump topology
24 Acknowledgment Support of the wireless team at Atheros. In particular D. Weber, S. Mehta, W. Si, B. Kaczynski, H. Dieh and J. Lu.
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