Gert Veale / Christo Nel Grintek Ewation

Transcription

1 Phase noise in RF synthesizers Gert Veale / Christo Nel Grintek Ewation

2 Introduction & Overview Where are RF synthesizers used? What is phase noise? Phase noise eects Classic RF synthesizer architecture VCO phase noise modiication In-band phase noise loor Optimum PLL loop bandwidth Conclusions Phase noise in RF synthesizers Page 2

3 Where are RF synthesizers used? BPF LNA BPF LPF ADC DSP 1 st IF 2 nd IF LO1 LO2 ADC Clock DSP Clock Local oscillators (LOs) in receiver or transmitter architectures Digital it clocks or analogue to digital it converters (ADCs), digital it to analogue converters (DACs) and other digital circuitry. Phase noise in RF synthesizers Page 3

4 What is phase noise? In the time domain it can be seen as jitter on a signal: t-jitter T-period In the requency domain it presents itsel as noise sidebands: Phase noise in RF synthesizers Page 4

5 Mathematical Deinition: What is phase noise? L noise1hz 10log (dbc/hz) P carrier RMS L 10 d (rad) t RMS RMS 2 o (s) Phase noise in RF synthesizers Page 5

6 Phase noise eects Receiver reciprocal mixing with a noisy LO: Large signal weak signal Large signal Masked weak signal c RX IF BPF LNA BPF IF Noisy LO LO Eect: Reduced receiver sensitivity in the presence o strong signals LO Phase noise in RF synthesizers Page 6

7 ADC clock with jitter: Phase noise eects analogue ADC SNR FS 2 t (db) 20log analogue RMS ADC Clock with jitter Result: Reduced ull scale dynamic range Digital communication systems: Result: Increased bit error rates (BERs) in phase modulated d systems (QPSK, QAM etc.) Phase noise in RF synthesizers Page 7

8 RF synthesizer architecture Consist o a classic phase locked loop (PLL) architecture: out re N Phase requency detector (PFD) Loop ilter Voltage controlled oscillator (VCO) Divider (N) Phase noise in RF synthesizers Page 8

9 VCO phase noise in a PLL VCO ree running phase noise proile is altered by a PLL: Power (dbm) L( ) VCO L( ) In-band noise loor PLL p out Frequency (Hz) An in-band noise loor L in band is ormed within the PLL loop bandwidth p You can clean up a noisy VCO with a well designed PLL Phase noise in RF synthesizers Page 9

10 In-band PLL phase noise loor Consider the PLL linear model where each component has an associated noise source: Common Conclusion: L 20logN in-band Phase noise in RF synthesizers Page 10

11 In-band PLL phase noise loor More exact: Lin-band 20log N L 20log N L in-band PFD 20log N 10log re FOM out re N Interesting: L PFD () increases with PFD operating requency re PFD Figure o merit (FOM) or normalized noise loor (L 1Hz ) is device speciic FOM is mainly determined by the random noise or time jitter inside the PFD: re FOM L 20log 2t 1Hz PFD The speciic IC semiconductor process (CMOS, SiGe, GaAs etc.) has a huge impact on the FOM Phase noise in RF synthesizers Page 11

12 In-band PLL phase noise loor Commercial RF synthesizer IC FOM comparison: Device Max Freq. N-Divider IC Process FOM L 1Hz Power Manuacturer ADF GHz µm BiCMOS -119 dbc/hz 0.08 W Analog Devices HMC700 8 GHz µm SiGe HBT -226 dbc/hz 0.36 W Hittite Microwave HMC GHz 2-32 GaAs HBT -233 dbc/hz 1.25 W Hittite Microwave HMC698 7 GHz GaAs HBT -233 dbc/hz 1.55 W Hittite Microwave Heterojunction bipolar transistor (HBT) designs tend to have better FOMs (Why?) Devices with low N-Divider values and good FOMs normally dissipate a lot o power (Why?) Phase noise in RF synthesizers Page 12

13 In-band PLL phase noise loor FOM dependant on PFD noise, In a typical tri-state CP PFD we have: V DD V DD DFF I CP UP D Q re t delay is inserted to C Q R div V DD D C R DFF Q Q t delay DN I CP icp avoid the dead zone in the PFD Dead zone occurs when the current switches are not ast enough Charge pump noise current: i 2 CP t T I designing a PFD, reduce t delay or less PFD jitter and hence a better FOM: PFD Phase noise in RF synthesizers Page 13 delay re I CP FOM 20log 2t A 2

14 Optimum PLL loop bandwidth Calculate L in band rom device FOM and average N-divider etc. Compare with VCO datasheet and set PLL loop bandwidth p to the VCO phase noise oset requency that intersects with L in band L( ) VCO L( ) PLL Optimum loop bandwidth In-band noise loor limit Excessive loop band width L In-band p p out out An incorrect loop bandwidth will cost you unnecessary phase noise Too small a loop bandwidth will also increase the PLL lock time Phase noise in RF synthesizers Page 14

15 Conclusions Phase noise in synthesizers and its eects were shown The concept o PLL in-band phase noise was demonstrated To minimize PLL in-band phase noise, the ollowing can be done: Use low N-divider values Use a high reerence or PFD requency re (This will reduce the N-divider) Use a device with a good FOM Optimize the PLL loop bandwidth or a given VCO phase noise proile Phase noise in RF synthesizers Page 15