60 GHz Receiver (Rx) Waveguide Module

Transcription

1 The PEM is a highly integrated millimeter wave receiver that covers the GHz global unlicensed spectrum allocations packaged in a standard waveguide module. Receiver architecture is a double conversion, sliding IF with wide bandwidth capability through the conversion chain down to baseband. The I/Q analog interface along with built-in AM and FM detectors provides for flexibility in design and applications. The receiver incorporates a complete waveguide interface with low-loss transition between the chip and the WR waveguide port. The integrated package is small and lightweight, with a simple to use multi-pin ST connector for power, reference clock, digital control port and baseband signals. Either of two reference clocks can be used for setting MHz or MHz channel spacing. Features: Complete millimeter wave receiver WR-, UG-8/U flange Operates in the to GHz unlicensed band db noise figure Up to.8 GHz modulation bandwidth I/Q analog baseband interface Integrated AM/ASK and FM/FSK detectors On chip synthesizer covers to.8 GHz MHz or MHz step size 8. MHz clock for MHz step size 8. MHz clock for MHz step size Power, control, signals on ST connector Temperature sensor Applications 8.ad: 8.,.8,.,.8 GHz 8.aj: 9.9,.,.,.8 GHz Any Channel ( MHz or MHz) -.8 GHz Multi-Gbps Digital Communications HD Video Transmission Millimeter Wave Radar Millimeter Wave Radiometry Millimeter Wave Imaging Microwave Temperature Profiling (MTP) Development for 8.ad and 8.aj ATE Equipment for GHz Manufacturing Test

2 G G WR- UG-8/U Flange Samtec ST- Connector Pin G Figure PEM Mechanical Dimensions

3 G Samtec ST- Pin.V.V.V.V.V.V.V.V.V VCC VDD VCC VCC VCC VCC VCC VCC VDD CLOCK DATA SCANOUT OUT_QM OUT_QP OUT_IM OUT_IP REFCLKM REFCLKP Q_E Q_B_C RESET ENABLE Mating Connector: Samtec SS--.-L-D-K-TR Figure PEM Interface Connector Pinout

4 Table Performance Specifications* Parameter Min Typ Max Unit Comment Frequency Range..8 GHz Channel Spacing MHz 8. MHz Reference Channel Spacing MHz 8. MHz Reference Modulation Bandwidth.8 GHz Max BW setting, double-sided at db Gain, Max db Gain, Range db Gain, Step Size. db Image Rejection > db Input IP - dbm At Max Gain Input PdB - dbm At Min Gain Sideband Suppression dbc Noise Figure db At Max Gain Phase khz - dbc/hz Phase MHz -8 dbc/hz Phase MHz - dbc/hz Phase MHz - dbc/hz Phase GHz - dbc/hz PLL Loop Bandwidth khz I/Q Balance Phase ± degrees I/Q Balance Amplitude ± db *Test Conditions: Reference Frequency 8. MHz Temperature C Input Signal Level - dbm IF Bandwidth Max Output Impedance ohms, output ports: I +/- and Q +/- ( ohm differential) Output Signal Level Referenced to single ohm output for gain specifications

5 Table Recommended Operating Conditions Description Power Supplies Name Vcc Vdd ST Pin # 8,,,, 8,,, Min Typ Max...8 Unit... V V Serial Control Port Logic High DATA CLOCK 8 ENABLE 9... V RESET SCANOUT Serial Control Port Logic Low DATA CLOCK 8 ENABLE V RESET SCANOUT Serial Control Port Speed MHz Reference Clock REFCLKM REFCLKP - dbm OUT_QM I and Q Baseband OUT_QP OUT_IM mvpp OUT_QP 9 Temperature Sensor Q_E Q_B_C Vcc.V Supply Current Icc ma Vdd.V Supply Current Idd 8 ma Operating Temperature T A - 8 C Reference clock power level specified at ohms differential Baseband voltage at each of the baseband outputs (I +/-, Q +/-) Temperature sensor is a N9 NPN transistor die connected as a diode junction

6 Table Absolute Maximum Ratings Description Power Supplies Name Vcc Vdd ST Pin # 8,,,, 8,,, MAX.8 V. V Serial Control Port Logic High DATA CLOCK 8 ENABLE 9. RESET SCANOUT Serial Control Port Logic Low DATA CLOCK 8 ENABLE 9 -. RESET SCANOUT Reference Clock REFCLKM REFCLKP dbm OUT_QM I and Q Baseband OUT_QP OUT_IM mvpp OUT_QP 9 GND,,,,9, ± mv Power Dissipation P D mw Storage Temperature T S - to C Operating Temperature T A - to 8 C Assertion of RESET, active high, asynchronously resets all registers

7 Receiver Architecture The PEM receiver uses a double conversion superheterodyne architecture with a sliding IF. The IF frequency is at / the RF carrier frequency, and the VCO is at / the RF carrier frequency. The LO is x the VCO frequency. The LO and IF are generated from a built-in synthesizer that has a step size at the RF carrier frequency of either MHz or MHz depending upon which reference clock frequency is used. The MHz step size uses a 8. MHz reference, and the MHz step uses a 8. MHz frequency. The IEEE channels for 8.ad and 8.aj are supported when the MHz step size is used. An RF signal in the range of to.8 GHz is coupled to the LNA via the low-loss WR waveguide port. The LO is mixed with the RF signal after the LNA and down converted the IF signal in the 8 to 9 GHz range. A notch filter attenuates the image frequency. The IF signal is filtered with a variable gain amplifier and filter with approximately db range, which is then fed into the quadrature mixers which down converts directly to baseband. There are also selectable AM and FM detectors for non-coherent modulation schemes. Additional variable gain and filtering are available in the baseband amplifier section which follows the I/Q mixers and detectors. The overall phase noise and I/Q balance specifications are sufficient for up to QAM operation. Configuration and settings are controlled through a digital serial interface port. The block diagram below shows the various stages and circuits in the module. Synthesizer. to.8 GHz. or. GHz step REFCLKP REFCLKM x Div WR- Waveguide UG-8/U Flange LNA AM DET Var BB Filter BB VGA OUT_IP OUT_IM º 9º IF VGA Var IF Filter OUT_QP OUT_QM FM DET Var BB Filter BB VGA Serial Control Registers RESET ENABLE CLOCK DATA SCANOUT Figure PEM Block Diagram

8 Synthesizer Design The PEM receiver uses a double conversion superheterodyne architecture with a sliding IF. The IF frequency is at / the RF carrier frequency, and the VCO is at / the RF carrier frequency. The LO is x the VCO frequency. The tables below show the RF carrier, IF, VCO and LO for the frequency range from GHz to.8 GHz at MHz and MHz channel spacing respectively. The reference clock for the synthesizer at MHz spacing is 8. MHz; for MHz spacing it is 8. MHz. The loop bandwidth of the synthesizer phase lock loop is khz. MHz Spacing MHz Spacing frf IF VCO LO frf IF VCO LO Figure Synthesizer RF, IF, VCO and LO Frequencies 8

9 Digital Control Registers and Serial Interface Protocol - Write Operation The PEM is configured via the serial control port which transfers data synchronously to or from (write or read operation) a register location. Register locations are organized into, byte-wide (8-bit) locations. The register locations are written to or read from one byte at a time as shown in Figures and respectively. Figure shows the sequence of the digital control signals for the ENABLE, CLOCK and DATA input pins (ST connector, pins 9, and 8 respectively) to write a single byte into the control register. After the ENABLE signal goes low, the first of 8 data bits (bit ) is placed on the data pin, and ns or more after the DATA signal stabilizes, the CLOCK signal goes high which clocks in data bit. The DATA signal must remain stable for at least ns after the rising edge of the CLOCK. The signal levels are.v CMOS, kω impedance, with a maximum clock rate of MHz. A write operation requires an 8 bit field associated with 8 clock pulses as shown in Figure. The 8 bit field contains the 8-bit data (LSB is clocked in first), followed by the byte address (BYTE through BYTE, to, LSB first, only of the bits are used with the two MSBs set to ), the read/write (R/W) bit (write = ), and the module address which distinguishes between a transmitter module and receiver module (for the PEM receiver, RX module = ). After clock pulse (8 total pulses), the ENABLE signal is returned to a high state to load the register byte into the module. The CLOCK signal must be stable in the low state at least ns prior to the rising edge of the ENABLE signal. ENABLE CLOCK DATA 8 9 Data Byte Address R/W TX/RX Module LSB MSB LSB MSB LSB MSB Figure Write Operation Timing Diagram 9

10 Digital Control Registers and Serial Interface Protocol - Read Operation Figure shows the sequence of control signals at the ENABLE, CLOCK and DATA pins to read a single byte at a register location. A read operation requires a bit field: The first 8 bits are used to clock in the bits on the DATA input pin. The first 8 bits during a read operation are don t care bits as they are placeholders for the 8-bit byte data which would be present during a write operation. The following bits are composed of the byte address (BYTE through BYTE, to, LSB first, only of the bits are used with the two MSBs set to ), the read/write (R/W) bit (read = ), and the module address which distinguishes between a transmitter module and receiver module (for the PEM receiver, RX module = ). After clock pulse (8 total pulses), the ENABLE signal is returned to a high state while the clock signal is low, then a single clock pulse (pulse 8) is sent during the ENABLE signal high period. The ENABLE signal then returns to the low state while the CLOCK signal is low. At each of the subsequent 8 CLOCK pulses, the 8-bit data from the specified register location is available at the SCANOUT pin, LSB first. Note that the DATA signal must remain in the low state during the period from clock pulse 8 through. Following clock pulse, the ENABLE signal goes high while the CLOCK signal is low to end the read operation. ENABLE 8 CLOCK DATA 8 9 Data Byte Address R/W TX/RX Module SCAN OUT LSB MSB LSB MSB LSB MSB Read Data LSB MSB Figure Read Operation Timing Diagram

11 Table. Register Byte Functions Bit Name BYTE ask_pwrdn BYTE BYTE bbamp_pwrdn_i bbamp_pwrdn_q divider_pwrdn if_bgmux_pwrdn ifmix_pwrdn_i ifmix_pwrdn_q ifvga_pwrdn ipc_pwrdn lna_pwrdn rfmix_pwrdn tripler_pwrdn bbamp_atten_ bbamp_atten_ bbamp_atten_ bbamp_atten_ bbamp_attenfi_ bbamp_attenfi_ bbamp_attenfi_ bbamp_attenfq_ bbamp_attenfq_ bbamp_attenfq_ bbamp_selask bbamp_sigshort Function Active high to power down ASK demodulator Active high to power down I-channel baseband amplifier Active high to power down Q-channel baseband amplifier Active high to power down local oscillator divider Active high to power down one of three on-chip refs (IF) and associated mux Active high to power down I-channel IF to baseband mixer Active high to power down Q-channel IF to baseband mixer Active high to power down IF variable gain amplifier Active high to power down module current reference generator Active high to power down low noise amplifier and reference Active high to power down RF to IF mixer Active high to power down frequency tripler First baseband attenuator: bits <:> = 8 db; = db; = db; = db Second baseband attenuator: bits <:> = 8 db; = db; = db; = db I Channel baseband fine attenuator: bits <:> = db; = db; = db; = db; = db; = db Q Channel baseband fine attenuator: bits <:> = db; = db; = db; = db; = db; = db Active high to switch the ASK detector into the I channel baseband amplifier Active high to short the inputs to the I and Q channel baseband amplifiers

12 Table. Register Byte Functions Bit Name BYTE bbamp_selbw_ bbamp_selbw_ bbamp_selhp_ bbamp_selhp_ bg_monitor_sel_ bg_monitor_sel_ If_refsel lna_refsel BYTE ifvga_bias_ ifvga_bias_ ifvga_bias_ ifvga_tune_ ifvga_tune_ ifvga_tune_ ifvga_tune_ not used BYTE ifvga_vga_adj_ ifvga_vga_adj_ ifvga_vga_adj_ ifvga_vga_adj_ rfmix_tune_ rfmix_tune_ rfmix_tune_ rfmix_tune_ Function Baseband amplifiers low pass filter corner: bits <:> =. GHz; = MHz ; = MHz; = MHz Baseband amplifiers high pass filter corner: bits <:> = khz; = khz ; =. MHz Reserved: bits <:> = for normal operation IF VGA bias and IF filter alignment; bits <:> = x for normal operation IF VGA gain control bits; bits <:> = highest gain, lowest gain Attenuation. db/step, db maximum IF filter alignment in the RF mixer; bits <:> = for normal operation

13 Table. Register Byte Functions Bit Name BYTE tripler_bias_ BYTE BYTE 8 tripler_bias_ tripler_bias_ tripler_bias_ tripler_bias_9 tripler_bias_8 tripler_bias_ tripler_bias_ tripler_bias_ tripler_bias_ tripler_bias_ tripler_bias_ tripler_bias_ tripler_bias_ bbamp_sel_fm fm_pwrdn lna_bias_ lna_bias_ lna_bias_ not used not used ifvga_q_cntrl_ ifvga_q_cntrl_ ifvga_q_cntrl_ Function Frequency tripler bias (upper 8 bit portion): bits <:> = default Frequency tripler bias (lower bit portion): bits <:> = default Active high to switch the FM detector into the Q channel baseband amplifier Active high to power down FM detector IF VGA gain control bits; bits <:> = highest gain, lowest gain Not used; bits <:> = xx IF filter Q in the VGA amplifier; bits <:> = for highest Q and gain For reduced Q and wider bandwidth, bits <:> =,,, in sequence

14 Table. Register Byte Functions Bit Name BYTE 9 not used not used not used not used not used not used not used not used BYTE rdacin_ rdacin_ rdacin_ rdacin_ rdacin_ rdacin_ synreset divratio_ BYTE divratio_ divratio_ divratio_ divratio_ band_ band_ band_ rfseldiv Function Not used: bits <:> = xxxxxxxx VCO amplitude DAC; bits<:> = for normal operation Synthesizer reset; bit <> = for normal operation Synthesizer divider ratio bit (see Tables. and.) Synthesizer divider ratio bits : (see Tables. and.) VCO band tuning bits : (see Tables. and.) Reserved; bit <> = for normal operation

15 Table. Register Byte Functions Bit Name BYTE BYTE BYTE cpbias_ cpbias_ cpbias_ vrsel_ vrsel_ vrsel_ vrsel_ refselvco muxref div_ en_dc ini pd_div_ pd_div_ pd_qp pd_vco pd_cal muxout pdcalc pload wide_ wide_ slew_ slew_ Function Synthesizer charge pump bias; bits <:> = for normal operation Synthesizer lock detector window width; bits <:> = for normal operation Reserved; bit <> = for normal operation Reserved; bit <> = for normal operation Enable synthesizer divider bit ; bit <> = for normal operation Synthesizer reference input DC coupling; bit <> = for normal operation Reserved; bit <> = for normal operation Active high to power down.v circuits in synthesizer divider Active high to power down.v circuits in synthesizer divider Active high to power down synthesizer charge pump Active high to power down synthesizer VCO Active high to power down VCO calibration; bit <> = for normal operation Multiplexer control for ability to read byte ; bit <> = for normal operation Active high to power down VCO ALC; bit <> = for normal operation Active high to load adjustment of VCO; bit <> = for normal operation Control for VCO ALC loop; bits <:> = for normal operation Slew rate control of sub-integer N divider; bits <:> = for normal operation

16 . Register Byte Functions Table. Register Byte Functions Bit Name BYTE comp_p comp_n rdacmsb_ rdacmsb_ rdacmsb_ rdacmux_ rdacmux_ rdacmux_ Reserved (read only) Function Synthesizer lock indication (read only): bits <:> = locked, = above window, = below window, = disallowed indicating error Table. MHz Channels Channel Divider Band Byte Byte Reference: 8. MHz Note : Band setting typical, may change from module to module and temperature. Note : Operation above GHz not guaranteed over full operating temperature range.

17 Table. MHz Channels Channel Divider Band Byte Byte Reference: 8. MHz Note : Band setting typical, may change from module to module and temperature. GHz Receiver (Rx) Waveguide Module from Pasternack Enterprises has same day shipment for domestic and International orders. Our RF, microwave and fiber optic products maintain a 99% availability and are part of the broadest selection in the industry. URL:

18 PEM CAD Drawing Millimeter Wave Receiver Module Operating From GHz To GHz REV 8