Intermediate Frequency Receiver, 800 MHz to 4000 MHz HMC8100LP6JE

Transcription

1 FEATURES High linearity: supports modulations to QAM Rx IF range: MHz to MHz Rx RF range: MHz to MHz Rx power control: db SPI programmable bandpass filters SPI controlled interface -lead, 6 mm 6 mm LFCSP package APPLICATIONS Point to point communications Satellite communications Wireless microwave backhaul systems Intermediate Frequency Receiver, MHz to MHz HMCLP6JE GENERAL DESCRIPTION The HMCLP6JE is a highly integrated intermediate frequency (IF) receiver chip that converts radio frequency (RF) input signals ranging from MHz to MHz down to a single-ended intermediate frequency (IF) signal of MHz at its output. The IF receiver chip is housed in a compact 6 mm 6 mm LFCSP package and supports complex modulations up to QAM. The HMCLP6JE device includes two variable gain amplifiers (VGAs), three power detectors, a programmable automatic gain control (AGC) block, and selected integrated band-pass filters with MHz, MHz, 6 MHz, and MHz bandwidth. The HMCLP6JE also supports baseband IQ interfaces after the mixer so that the chips can be used in the full outdoor units (ODU) configuration. The HMCLP6JE supports all standard microwave frequency bands from 6 GHz to GHz. FUTIONAL BLOCK DIAGRAM REF_CLK_P RST 9 HMC SDO 7 SDI 6 SCLK SEN LON LOP IRM_Q_N IRM_Q_P DVDD AMP_P SPI OTP VDD 9 IRM_I_N AMP_N IRM_I_P VCC_FILTER FILTERP VCC_AMP 6 FILTER MHz MHz 6MHz MHz 7 VCC_IRM 6 VCC_VGA_BALUN VCC_VGA GND VCC_BB 7 AGC FILTERP VCC_AMP GND 9 AMP VGA_EXT_CAP GND RX_OUT VCC_VGA AUX_OUT PD_IN PD_OUT_RSSI VC_VGA_IF_CAP 6 VC_VGA_RF_CAP 7 VCC_PD 9 PD_OUT RFIN PACKAGE BASE GND 67- Figure. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 HMCLP6JE TABLE OF CONTENTS Features... Applications... General Description... Functional Block Diagram... Revision History... Specifications... Electrical Characteristics: MHz to MHz RF Frequency Range... Electrical Characteristics: MHz to MHz RF Frequency Range... Electrical Characteristics: MHz to MHz RF Frequency Range... Absolute Maximum Ratings... 6 ESD Caution... 6 Pin Configuration and Function Descriptions... 7 REVISION HISTORY 9/7 Rev. A to Reb. B Changes to Figure... Changes to Figure and Table... 7 Changes to Theory of Operation Section and Register Array Assignment and Serial Interface Section... Changes to Figure and Figure... 9 Changes to Figure... Changes to Ordering Guide... 7 Data Sheet Typical Performance Characteristics...9 External AGC Configuration...9 Internal AGC Configuration... 6 Theory of Operation... Register Array Assignments and Serial Interface... Register Descriptions... Register Array Assignments... Applications Information... Schematic/Typical Application Circuit... Evaluation Printed Circuit Board (PCB)... Outline Dimensions... 7 Ordering Guide... 7 /6 v.6 to Rev. A This Hittite Microwave Products data sheet has been reformatted to meet the styles and standards of Analog Devices, Inc. Updated Format... Universal Added Pin Configuration Diagram, Renumbered Sequentially... 7 Added Ordering Guide... /6 v.6: Initial Version Rev. B Page of 7

3 HMCLP6JE SPECIFICATIONS TA = C, IF frequency = MHz, local oscillator (LO) input signal level = dbm, RF input signal level = dbm per tone, filter bandwidth = 6 MHz, IF gain limit (decimal) = 7, sideband select = lower sideband, AGC select = external AGC, unless otherwise noted, see the Typical Performance Characteristics section. ELECTRICAL CHARACTERISTICS: MHz TO MHz RF FREQUEY RANGE Table. Parameter Min Typ Max Unit OPERATING CONDITIONS LO Frequency Range 6 MHz IF Frequency Range MHz RF INPUT INTERFACE Input Impedance Ω Return Loss db IF OUTPUT INTERFACE Input Impedance Ω Return Loss db LO INPUT INTERFACE Input Impedance Ω Return Loss 9 db DYNAMIC PERFORMAE Power Conversion Gain 6 db RF VGA Dynamic Range db IF VGA Dynamic Range 9 db Image Rejection 6 dbc Noise Figure at PIN (One Tone) db Output Third-Order Intercept (OIP) 6 dbm Output db Compression Point (OPdB) 7 dbm LO Leakage at the IF Input 6 dbm LO Leakage at the RF Input 7 7 dbm RF Leakage at the IF Output 6 6 dbm POWER SUPPLY Supply Voltage VCCX. V VCC VGA. V Supply Current VCCX 6 ma VCC VGA μa VCC VGA = VC_VGA_IF + VC_VGA_RF can be adjusted from. V (minimum ATTEN) to V (maximum ATTEN) to control the IF and RF VGA in external AGC mode. Rev. B Page of 7

4 HMCLP6JE Data Sheet ELECTRICAL CHARACTERISTICS: MHz TO MHz RF FREQUEY RANGE Table. Parameter Min Typ Max Unit OPERATING CONDITIONS LO Frequency Range 6 MHz IF Frequency Range MHz RF INPUT INTERFACE Input Impedance Ω Return Loss db IF OUTPUT INTERFACE Input Impedance Ω Return Loss db LO INPUT INTERFACE Input Impedance Ω Return Loss 7 db DYNAMIC PERFORMAE Power Conversion Gain 77 db RF VGA Dynamic Range 7 db IF VGA Dynamic Range 9 db Image Rejection 6 dbc Noise Figure at PIN (One Tone) 7 db Output Third-Order Intercept (OIP) dbm Output db Compression Point (OPdB) 7 dbm LO Leakage at the IF Input dbm LO Leakage at the RF Input 7 66 dbm RF Leakage at the IF Output 7 6 dbm POWER SUPPLY Supply Voltage VCCX. V VCC VGA. V Supply Current VCCX 6 ma VCC VGA μa VCC VGA = VC_VGA_IF + VC_VGA_RF can be adjusted from. V (minimum ATTEN) to V (maximum ATTEN) to control the IF and RF VGA in external AGC mode. Rev. B Page of 7

5 HMCLP6JE ELECTRICAL CHARACTERISTICS: MHz TO MHz RF FREQUEY RANGE Table. Parameter Min Typ Max Unit OPERATING CONDITIONS LO Frequency Range 6 MHz IF Frequency Range MHz RF INPUT INTERFACE Input Impedance Ω Return Loss db IF OUTPUT INTERFACE Input Impedance Ω Return Loss db LO INPUT INTERFACE Input Impedance Ω Return Loss 7 db DYNAMIC PERFORMAE Power Conversion Gain 7 db RF VGA Dynamic Range 7 db IF VGA Dynamic Range 9 db Image Rejection dbc Noise Figure at PIN (One Tone) db Output Third-Order Intercept (OIP) dbm Output db Compression Point (OPdB) 7 dbm LO Leakage at the IF Input 6 dbm LO Leakage at the RF Input 66 6 dbm RF Leakage at the IF Output 7 6 dbm POWER SUPPLY Supply Voltage VCCX. V VCC VGA. V Supply Current VCCX 6 ma VCC VGA μa VCC VGA = VC_VGA_IF + VC_VGA_RF can be adjusted from. V (minimum ATTEN) to V (maximum ATTEN) to control the IF and RF VGA in external AGC mode. Rev. B Page of 7

6 HMCLP6JE ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating RF Input dbm LO Input dbm VCCX. V to +. V. V to +.6 V Maximum Junction Temperature to C Maintain Million Hour MTTF Thermal Resistance (RTH), Junction to. C/W Ground Paddle Temperature Operating C to Storage 6 C to + C Maximum Peak Reflow Temperature 6 C (MSL) ESD Sensitivity (Human Body Model) V (Class ) Data Sheet Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. B Page 6 of 7

7 HMCLP6JE PIN CONFIGURATION AND FUTION DESCRIPTIONS REF_CLK_P RST SDO SDI SCLK SEN LON LOP IRM_Q_N IRM_Q_P DVDD AMP_P AMP_N VCC_FILTER FILTERP VCC_AMP 6 GND 7 VCC_BB GND 9 VGA_EXT_CAP VDD 9 IRM_I_N IRM_I_P 7 VCC_IRM 6 VCC_VGA_BALUN VCC_VGA FILTERP VCC_AMP AMP GND HMC TOP VIEW (Not to Scale) RX_OUT VCC_VGA AUX_OUT PD_IN PD_OUT_RSSI VC_VGA_IF_CAP VC_VGA_RF_CAP VCC_PD PD_OUT RFIN NOTES. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A LOW IMPEDAE THERMAL AND ELECTRICAL GROUND PLANE. Figure. Pin Configuration Table. Pin Function Descriptions Pin No. Mnemonic Description DVDD SPI Digital Power Supply (. V dc). See Figure for the required components. AMPT_P Second Differential Amplifier Output (Positive). AMP_N Second Differential Amplifier Output (Negative). VCC_FILTER Power Supply for the Filter (. V dc). See Figure for the required components. FILTERP Input of the Third External Filter Amplifier. 6 VCC_AMP Power Supply for the Third External Filter Amplifier (. V dc). See Figure for the required components. 7, 9, GND, GND, GND Ground Connect. VCC_BB Power Supply for the Baseband Blocks (. V dc). See Figure for the required components. VGA_EXT_CAP External Capacitor for VGA. See Figure for the required components. RX_OUT Receiver Output. VCC_VGA Power Supply for VGA (. V dc). See Figure for the required components. AUX_OUT Receiver Auxiliary Output. PD_IN Receive AGC Loop Input. PD_OUT/RSSI Third Power Detector Output. 6 VC_VGA_IF/CAP Control Voltage of IFVGA/AGC Integrator Capacitor. See Figure for the required components. 7 VC_VGA_RF/CAP+ Control Voltage of RFVGA/AGC Integrator Capacitor. See Figure for the required components. VCC_PD Power Supply for the First Power Detector (. V dc). See Figure for the required components. 9 PD_OUT First Power Detector Output. RFIN Radio Frequency Input. This pin is matched to Ω. AMP Single-Ended Output of Amplifier (. V dc). See Figure for the required components. VCC_AMP Power Supply for AMP (. V dc). See Figure for the required components. FILTERP RFVGA Input. VCC_VGA Power Supply for the RFVGA (. V dc). See Figure for the required components. 6 VCC_VGA_BALUN Power Supply for RFVGA Balun(. V dc). See Figure for the required components. 7 VCC_IRM Power Supply for the Image Reject Mixer (. V dc). See Figure for the required components. IRM_I_P Positive In-Phase IF Output for the Image Reject Mixer. 9 IRM_I_N Negative In-Phase IF Output for the Image Reject Mixer. VDD Power Supply for Logic Circuitry (. V dc). See Figure for the required components. IRM_Q_P Positive Quadrature IF Output for the Image Reject Mixer. IRM_Q_N Negative Quadrature IF Output for the Image Reject Mixer. LOP Local Oscillator Input (Positive). This pin is ac-coupled and matched to Ω. Rev. B Page 7 of 7 67-

8 HMCLP6JE Data Sheet LON Local Oscillator Input (Negative). This pin is ac-coupled and matched to Ω. SEN SPI Serial Enable. 6 SCLK SPI Clock Digital Input. 7 SDI SPI Serial Data Input. SDO SPI Serial Data Output. 9 RST SPI Reset. RESET must be held low (Logic ) during power on. This is critical for proper programming and reliable operation. Refer to the Theory of Operation section. REF_CLK_P Filter Calibration Clock. EPAD Exposed Pad. Connect the exposed pad to a low impedance thermal and electrical ground plane. Rev. B Page of 7

9 HMCLP6JE TYPICAL PERFORMAE CHARACTERISTICS EXTERNAL AGC CONFIGURATION Lower sideband selected, maximum gain MHz MHz 6MHz MHz EXT RF FREQUEY (GHz) Figure. Conversion Gain vs. RF Frequency over Internal and External Filters RF FREQUEY (GHz) Figure 6. Conversion Gain vs. RF Frequency over Temperature, 6 MHz Filter dbm dbm 6 dbm +dbm +dbm RF FREQUEY (GHz) Figure. Conversion Gain vs. RF Frequency at Various Local Oscillator (LO) Powers, 6 MHz Filter V.V.97V RF FREQUEY (GHz) Figure 7. Conversion Gain vs. RF Frequency at Various VCCx, 6 MHz Filter VC_VGA_RF (V) Figure. Conversion Gain vs. VC_VGA_RF at RF = GHz, 6 MHz Filter (RF Input Power = dbm, VC_VGA_IF = V) VC_VGA_RF (V) Figure. Conversion Gain vs. VC_VGA_RF at RF = GHz, 6 MHz Filter (RF Input Power = dbm, VC_VGA_IF = V) 67- Rev. B Page 9 of 7

10 HMCLP6JE Data Sheet Lower sideband selected, maximum gain VC_VGA_RF (V) Figure 9. Conversion Gain vs. VC_VGA_RF at RF = GHz, 6 MHz Filter (RF Input Power = dbm, VC_VGA_IF = V) VC_VGA_IF (V) Figure. Conversion Gain vs. VC_VGA_IF at RF = GHz, 6 MHz Filter (VC_VGA_RF =. V) VC_VGA_IF (V) Figure. Conversion Gain vs. VC_VGA_IF at RF = GHz, 6 MHz Filter (VC_VGA_RF =. V) VC_VGA_IF (V) Figure. Conversion Gain vs. VC_VGA_IF at RF = GHz, 6 MHz Filter, (VC_VGA_RF =. V) 67-9 MHz MHz 6MHz MHz 9 NOISE FIGURE (db) 7 6 NOISE FIGURE (db) RF FREQUEY (GHz) Figure. Noise Figure vs. RF Frequency over Internal Filters RF FREQUEY (GHz) Figure. Noise Figure vs. RF Frequency over Temperature, 6 MHz Filter 67- Rev. B Page of 7

11 HMCLP6JE Lower sideband selected, maximum gain. NOISE FIGURE (db) dbm dbm dbm +dbm +dbm NOISE FIGURE (db) V.V.97V RF FREQUEY (GHz) Figure. Noise Figure vs. RF Frequency at Various LO Powers, 6 MHz Filter RF FREQUEY (GHz) Figure. Noise Figure vs. RF Frequency at Various VCCx, 6 MHz Filter 67- IMAGE REJECTION (dbc) IMAGE REJECTION (dbc) MHz MHz 6MHz MHz RF FREQUEY (GHz) Figure 6. Image Rejection vs. RF Frequency over Internal Filters RF FREQUEY (GHz) Figure 9. Image Rejection vs. RF Frequency over Temperature, 6 MHz Filter 67-9 IMAGE REJECTION (dbc) dbm dbm dbm +dbm +dbm RF FREQUEY (GHz) Figure 7. Image Rejection vs. RF Frequency at Various LO Powers, 6 MHz Filter 67-7 IMAGE REJECTION (dbc).6v.v.97v RF FREQUEY (GHz) Figure. Image vs. RF Frequency at Various VCCx, 6 MHz Filter 67- Rev. B Page of 7

12 HMCLP6JE Data Sheet Lower sideband selected, maximum gain. MHz MHz 6MHz MHz IP (dbm) 6 IP (dbm) RF FREQUEY (GHz) Figure. Output IP vs. RF Frequency over Internal Filters RF FREQUEY (GHz) Figure. Output IP vs. RF Frequency over Temperature, 6 MHz Filter 67- dbm dbm dbm +dbm +dbm.6v.v.97v IP (dbm) 6 IP (dbm) RF FREQUEY (GHz) Figure. Output IP vs. RF Frequency at Various LO Powers, 6 MHz Filter RF FREQUEY (GHz) Figure. Output IP vs. RF Frequency at Various VCCx, 6 MHz Filter 67- RETURN LOSS (db) RETURN LOSS (db) RF FREQUEY (GHz) Figure. RF Return Loss vs. RF Frequency over Temperature (Optimize RF Return Loss by Adjusting Capacitor C, see Figure ) LO FREQUEY (GHz) Figure 6. LO Return Loss vs. LO Frequency over Temperature 67-6 Rev. B Page of 7

13 HMCLP6JE Lower sideband selected, maximum gain. LO TO RF LEAKAGE LO TO IF LEAKAGE RETURN LOSS (db) LEAKAGE (dbm) IF FREQUEY (GHz) Figure 7. IF Return Loss vs. IF Frequency over Temperature LO FREQUEY (GHz) Figure. LO Leakage vs. LO Frequency at RF and IF Ports with 6 MHz Filter 67- RF TO IF LEAKAGE RF TO (AMP_P + AMP_N) LEAKAGE LO TO (AMP_P + AMP_N) LEAKAGE LEAKAGE (dbm) LEAKAGE (dbm) RF FREQUEY (GHz) Figure. RF Leakage vs. RF Frequency at IF Port with 6 MHz Filter and at (AMP_P + AMP_N) Pins LO FREQUEY (GHz) Figure. LO Leakage vs. LO Frequency at (AMP_P + AMP_N) Pins IF FREQUEY (GHz) Figure 9. MHz Internal Filter Response vs. IF Frequency at RF = GHz (RF Input Power = dbm, Adjusted VC_VGA_IF and VC_VGA_RF to Achieve db of Gain) IF FREQUEY (GHz) Figure. MHz Internal Filter Response vs. IF Frequency at RF = GHz (RF Input Power = dbm, Adjusted VC_VGA_IF and VC_VGA_RF to Achieve db of Gain) 67- Rev. B Page of 7

14 HMCLP6JE Data Sheet Lower sideband selected, maximum gain IF FREQUEY (GHz) Figure. 6 MHz Internal Filter Response vs. IF Frequency at RF = GHz (RF Input Power = dbm, Adjusted VC_VGA_IF and VC_VGA_RF to Achieve db of Gain) PD OUTPUT VOLTAGE (V) PD OUTPUT VOLTAGE (V) IF OUTPUT POWER (dbm) Figure. PD Output Voltage vs. IF Power Output at RF = GHz, 6 MHz Filter IF OUTPUT POWER (dbm) Figure. PD Output Voltage vs. IF Power Output at RF = GHz, 6 MHz Filter IF FREQUEY (GHz) Figure 6. MHz Internal Filter Response vs. IF Frequency at RF = GHz PD OUTPUT VOLTAGE (V) PdB (dbm) IF OUTPUT POWER (dbm) Figure 7. PD Output Voltage vs. IF Power Output at RF = GHz, 6 MHz Filter RF FREQUEY (GHz) Figure. Output PdB vs. RF Frequency over Temperature, 6 MHz Filter Rev. B Page of 7

15 HMCLP6JE Lower sideband selected, maximum gain. PdB (dbm) RF FREQUEY (GHz) Figure 9. Output PdB vs. RF Frequency over IF Gain Limit, 6 MHz Filter 67-9 Rev. B Page of 7

16 HMCLP6JE Data Sheet INTERNAL AGC CONFIGURATION POUT = 9 dbm per tone, lower sideband, and 6 MHz filter selected IM (dbc) IM (dbc) INPUT POWER (dbm) Figure. IM vs. Input Power over Temperature, RF = GHz INPUT POWER (dbm) Figure. IM vs. Input Power over Temperature, RF = GHz IM (dbc) 6 NOISE FIGURE (db) INPUT POWER (dbm) Figure. IM vs. Input Power over Temperature, RF = GHz INPUT POWER (dbm) Figure. Noise Figure vs. Input Power over Temperature, RF = GHz NOISE FIGURE (db) NOISE FIGURE (db) INPUT POWER (dbm) Figure. Noise Figure vs. Input Power over Temperature, RF = GHz INPUT POWER (dbm) Figure. Noise Figure vs. Input Power over Temperature, RF = GHz 67- Rev. B Page 6 of 7

17 HMCLP6JE POUT = 9 dbm per tone, lower sideband, and 6 MHz filter selected. 6 6 OUTPUT POWER (dbm) OUTPUT POWER (dbm) INPUT POWER (dbm) Figure 6. Output Power vs. Input Power over Temperature, RF = GHz INPUT POWER (dbm) Figure. Output Power vs. Input Power over Temperature, RF = GHz 67-6 OUTPUT POWER (dbm) INPUT POWER (dbm) Figure 7. Output Power vs. Input Power over Temperature, RF = GHz 67-7 Rev. B Page 7 of 7

18 HMCLP6JE THEORY OF OPERATION The HMCLP6JE is a highly integrated intermediate frequency (IF) receiver chip that converts radio frequency (RF) to a single-ended IF signal at its output. The internal active gain circuit (AGC) of the HMCLP6JE is able to actively level the output power at the IF output via SPI control. The gain control of the HMCLP6JE can be controlled externally as an alternative option via the VC_VGA_RF and VC_VGA_IF pins with voltages ranging from. V (minimum attenuation) to V (maximum attenuation). The HMCLP6JE utilizes an input low noise amplifier (LNA) cascaded with a variable gain amplifier (VGA), which can either be controlled by the internal AGC or external voltages, that feeds the RF signals to an image reject mixer. The local oscillator port can either be driven single ended through LON or differentially through the combination of LON and LOP. The radio frequency is then converted to intermediate frequencies, which can either feed off chip via baseband differential outputs or feed on chip into a programmable bandpass filter. It is recommended during IF mode operation that the baseband outputs be unconnected. The programmable band-pass filter on chip has four programmable bandwidths ( MHz, MHz, 6MHz, and MHz). The programmable band-pass filter has the capability to adjust the center frequency. From the factory, a filter calibration is conducted and the center frequency of the filter is set to MHz. This calibration can be recalled via SPI control or the customer can adjust the center frequency, but the calibration value must be stored off chip (see the Register Array Assignments section). An external filter option can be utilized to allow the customer to select other filter bandwidths/responses that are not available on chip. The external filter path coming from the image reject mixer feeds into an amplifier that has differential outputs. The output of the external filter can be fed back into the chip, which is then connected to another amplifier. A VGA follows immediately after the band-pass filter. Control the IF VGA either by the AGC or external voltages. The output of the variable gain amplifier is the output of the device. The SPI RESET pin on the HMCLP6JE must be held low (Logic ) during power on. This is critical for proper programming and reliable operation. Apply a RESET low before the bias voltage is applied to the device or use a pull-down resistor on the RESET pin. Data Sheet REGISTER ARRAY ASSIGNMENTS AND SERIAL INTERFACE The register arrays for the HMCLP6JE are organized into nine registers of 6 bits. Using the serial interface, the arrays are written or read one row at a time, as shown in Figure and Figure. Figure shows the sequence of signals on the enable (SEN), CLK, and data (SDI) lines to write one 6-bit array of data to a single register. The enable line goes low, the first of data bits is placed on the data line, and the data is sampled on the rising edge of the clock. The data line should remain stable for at least ns after the rising edge of CLK. The device supports a serial interface running up to MHz, the interface is. V CMOS logic. A write operation requires data bits and clock pulses, as shown in Figure. The data bits contain the -bit chip address, followed by the -bit register array number, and finally the 6-bit register data. After the th clock pulses of the write operation, the enable line returns high to load the register array on the IC. A read operation requires data bits and clock pulses, as shown in Figure. For every register read operation you must first write to Register 7. The data written should contain the -bit chip address, followed by the -bit register number for Register 7, and finally the -bit number of the register to be read. The remaining bits should be logic zeroes. When the read operation is initiated, the data is available on the data output (SDO) pin. The output data bits are placed on the data line during the rising edge of the clock. Read Example If reading Register, the following bits should be written to initiate the read operation. ZERO BITS ( BITS) REGISTER 7 ADDRESS ( BITS) REGISTER TO BE READ ( BITS) CHIP ADDRESS ( BITS) Figure 9. Sample Bits to Initiate Read 67-9 Rev. B Page of 7

19 HMCLP6JE SEN CLOCK CYCLES CLK SDI WRITE DATA REGISTER ADDRESS CHIP ADDRESS MSB LSB MSB LSB MSB LSB 67- Figure. Timing Diagram, SPI Register Write SEN CLOCK CYCLES CLOCK CYCLES CLK SDI SDO MSB ALL ZEROS LSB MSB READ REGISTER ADDRESS LSB MSB REG 7 ADDRESS CHIP ADDRESS LSB MSB LSB MSB READ DATA LSB 67- Figure. Timing Diagram, SPI Register Read Rev. B Page 9 of 7

20 HMCLP6JE Data Sheet REGISTER DESCRIPTIONS REGISTER ARRAY ASSIGNMENTS In the Access columns (Table 6 through Table ), R means read, W means write, and R/W means read/write. Enable Bits Table 6. Enable Register, (Address x) Bit No. Bit Name Description Reset Access PD_EN Power Detector enable x R/W = disable = enable Factory diagnostics Logic for normal operation x R/W PD_AMP_EN Auxiliary output (Pin ) enable x R/W = disable = enable Reserved Logic for normal operation x R/W AMP_EN LNA enable x R/W = disable = enable RF_VGA_EN RF VGA enable x R/W = disable = enable 9 IRM_EN Image reject mixer enable x R/W = disable = enable FIL_EN Filter enable x R/W = disable = enable 7 IF_VGA_EN Filter enable x R/W = disable = enable 6 Factory diagnostics Logic for normal operation x R/W PD_EN Power Detector enable x = disable = enable PD_EN Power Detector enable x R/W = disable = enable AGC_EN Available gain control (AGC) enable x R/W = enable = disable AMP_PDWN Amplifier power-down x R/W = enable = disable AMP_PDWN Amplifier power-down x R/W = enable = disable IQ_BUF_EN IQ buffer enable x R/W = disable = enable Rev. B Page of 7

21 HMCLP6JE Image Reject and Band-Pass Filter Bits Table 7. Image Reject and Band-Pass Filter Register, (Address x) Bit No. Bit Name Description Reset Access IRM_IS Image sideband select x R/W = lower sideband = upper sideband [:] FIL_SEL Internal band-pass filter select x R/W = MHz = MHz = 6 MHz = MHz SEL_EXT_FIL Select external filter x R/W = internal = external Reserved Not used x R/W FIL_CAL_OVR Override on-chip calibration and use -bit word from SPI x R/W = use on-chip calibration word = use FIL_FREQ_SET word from SPI 9 FIL_CAL_EN Enable filter center frequency calibration x R/W = disable = enable (transition from to ) Reserved Not used x R/W [7:] FIL_FREQ_SET Internal band-pass filter center frequency setting x R/W Band-Pass Filter Bits: OTP and SPI Table. Band-Pass Filter Register, (Address x) Bit No. Bit Name Description Reset Access [:] Reserved Logic for normal operation x R/W FIL_OPT_MUX_SEL Override SPI FIL_FRQ_SET and use -bit word from OTP x R/W = select OTP setting = select SPI setting [:] Reserved Logic for normal operation x69f R/W AGC Table 9. AGC Register, (Address x) Bit No. Bit Name Description Reset Access [:] AGC_SELECT Active gain control (AGC) select x R/W x = internal AGC mode xc = external AGC mode AGC_EXT_CAP_SEL Active gain control external capacitor select x R/W = no external capacitor = external capacitor [:] AGC_BW AGC bandwidth x R/W = 7 Hz = Hz = Hz = 67 Hz = Hz = Hz (recommended setting) = 67 Hz = Hz Rev. B Page of 7

22 HMCLP6JE Data Sheet Bit No. Bit Name Description Reset Access [7:6] VGA_GAIN VGA attentuation x R/W = db (recommended setting) = db = db = db [:] POUT_CTRL Power output control x R/W x = dbm x = dbm x = xe = + dbm xf = +9 dbm AGC: IF Gain Limit Bits Table. AGC Register, (Address x) Bit No. Bit Name Description Reset Access [:] Reserved Not used xa R/W [:9] IF_GAIN_LIMIT IF gain limit x R/W = db = 6 db = db = db = db = db = 6 db = db [:] Reserved Logic for normal operation x R/W Band-Pass Filter Bits: Calibration and -Bit Word Frequency Table. Band-Pass Filter Register, (Address x6) Bit No. Bit Name Description Reset Access [:] Reserved Not used x R 9 FIL_CAL_OVFL FIL calibration overflow signal x R FIL_VCAL_END FIL calibration end signal x R [7:] FL_FC_CAL FIL -bit word frequency setting, read only x R Rev. B Page of 7

23 HMCLP6JE AGC: Blocker Power Detector Bits Table. AGC Register, (Address x) Bit No. Bit Name Description Reset Access [:] Reserved Not used xf R/W 7 Reserved Not used x R/W 6 AGC_BLOCKER_MODE_EN AGC blocker mode enable x R/W = off = on [:] AGC_BLOCKER_PD_REF AGC blocker power detector reference level x R/W = dbm = dbm = dbm = dbm = dbm = 6 dbm = dbm = dbm [:] AGC_BLOCKER_PD_LOOP_BW AGC blocker power detector loop bandwidth control x R/W = 7 Hz = Hz = Hz = 67 Hz = Hz = Hz = 67 Hz = Hz Phase I Bits Table. Phase I Register, (Address x) Bit No. Bit Name Description Reset Access [:] Reserved Not used xf R/W [:9] Reserved Not used x R/W [:] I_PHASE_ADJ I phase adjust x R/W Phase Q Bits Table. Phase Q Register, (Address x) Bit No. Bit Name Description Reset Access [:] Reserved Not used xf R/W [:9] Reserved Not used x R/W [:] Q_PHASE_ADJ Q phase adjust x R/W Rev. B Page of 7

24 HMCLP6JE APPLICATIONS INFORMATION During operation at PdB, the IF gain limit of the HMCLP6JE, as described in the Register Array Assignments and Serial Interface section, needs to be limited by the radio frequency (RF), as listed in Table. There is a recommended IF gain limit setting and maximum allowed IF gain limit setting that is to be used. Data Sheet SCHEMATIC/TYPICAL APPLICATION CIRCUIT Table. Recommended IF Gain Limit Settings by RF Frequency RF Frequency (GHz) Maximum Setting Recommended Setting. to.. to. 6. to. 7 6 Rev. B Page of 7

25 HMCLP6JE Rev. B Page of 7 EVALUATION PRINTED CIRCUIT BOARD (PCB) C UF J uf C C7 nf C PF : T - MHz MABAES6 R 6 R6 6 C9 UF uf C C nf C PF C PF C nf uf C6 C nf R7 9.9 F 9 MHz C PF C6 nf uf C7 C7 PF C nf uf C L.UH R 7 C9 NF J6 J SSW-6--F-D-VS J7 J : T - MHz MABAES6 J9 C UF : T MABAES6 - MHz J C UF uf C C nf C PF C PF C nf uf C uf C6 C nf C6 PF F LFCN- DC - MHz C7 PF C nf uf C7 C9 PF L NH C PF C PF J C nf C PF C6 nf uf C9 C PF C nf uf C J TSM---L-SV J TSM---L-SV R.99 DVDD DVDD VCC_AMP VCC_AMP VCC_BB VCC_VGA VCC_IRM VCC_BALUN VCC_VGA VCC_AMP VCC_AMP VCC_PD PD_OUT VC_VGA_EXT PD_OUT VC_VGA_EXT C6 PF C6 nf uf C67 VCC_AMP uf C6 C6 nf C66 PF VCC_OTP VCC_PV VCC_OTP J J J J6 J7 J RFIN IFOUT LON LOP BBOUT_Q BBOUT_I REF_CLK_N VCC_PV U AMPP AMPN VCC_FILTER FILTERP DVDD VCC_AMP GND VCC_BB RST SDO SDI SCLK FILTERP VCC_AMP VCC_VGA IRM_IN AMP RX_OUT Vcc_VGA Aux_out PD_in PD_out/RSSI Vc_VGA_IF/Cap- VCC_PD Vc_VGA_RF/Cap+ VCC_VGA_BALUN LOP VCC_IRM LON REF_CLK_P SEN GND VGA_ext_cap PD_OUT RFIN IRM_IP IRM_QN IRM_QP VDDV GND HMCLP6JE R 9.9 VC_VGA_EXT VC_VGA_EXT C69 nf F 6 RBP-+ -HMz 9.9 R6 J J VCC_AMP VCC_AMP VCC_PD DVDD VCC_AMP VCC_VGA C7 NF DEPOP VCC_BB VCC_VGA VCC_BALUN VCC_IRM PD_OUT PD_OUT 67- Figure. PCB Schematic/Typical Applications Circuit

26 HMCLP6JE Data Sheet 67- Figure. Evaluation PCB Rev. B Page 6 of 7

27 HMCLP6JE OUTLINE DIMENSIONS DETAIL A (JEDEC 9) PIN INDICATOR SQ.9. SQ.... BSC PIN INDIC ATOR AREA OPTIONS (SEE DETAIL A). BSC EXPOSED PAD.6. SQ SEATING PLANE TOP VIEW SIDE VIEW.... MAX. NOM COPLANARITY.. REF BOTTOM VIEW. MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUTION DESCRIPTIONS SECTION OF THIS DATA SHEET. ORDERING GUIDE PKG- COMPLIANT TOJEDEC STANDARDS MO--VJJD-. Figure. -Lead Lead Frame Chip Scale Package [LFCSP] 6 mm 6 mm Body and.9 mm Package Height (CP--) Dimensions shown in millimeters Temperature MSL Package Model, Range Rating Package Description Option HMCLP6JE C to MSL -Lead Lead Frame Chip Scale Package [LFCSP] CP-- HMCLP6JETR C to MSL -Lead Lead Frame Chip Scale Package [LFCSP] CP-- EKHMCLP6J Evaluation Kit --6-A Package Marking H XXXX H XXXX All models are RoHS compliant. The HMCLP6JE and HMCLP6JETR lead finishes are NiPdAu. See the Absolute Maximum Ratings section. XXXX is the -digit lot number. 6 7 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D67--9/7(B) Rev. B Page 7 of 7