400 MHz to 4000 MHz Low Noise Amplifier ADL5523

Transcription

1 FEATURES Operation from MHz to MHz Noise figure of. db at 9 MHz Requires few external components Integrated active bias control circuit Integrated dc blocking capacitors Adjustable bias for low power applications Single-supply operation from 3 V to V Gain of. db at 9 MHz of 3. dbm at 9 MHz of. dbm at 9 MHz Small footprint LFCSP Pin-compatible version with. db gain available GENERAL DESCRIPTION The ADL3 is a high performance GaAs phemt low noise amplifier. It provides high gain and low noise figure for singledownconversion IF sampling receiver architectures as well as direct-downconversion receivers. The ADL3 provides a high level of integration by incorporating the active bias and the dc blocking capacitors, making it very easy to use while not sacrificing design flexibility. MHz to MHz Low Noise Amplifier ADL3 FUTIONAL BLOCK DIAGRAM VBIAS RFIN 3 ACTIVE BIAS ADL3 = NO CONNECT Figure. 7 VPOS RFOUT The ADL3 is easy to tune, requiring only a few external components. The device can support operation from 3 V to V, and the current draw can be adjusted with the external bias resistor for applications requiring very low power consumption. The ADL3 comes in a compact, thermally enhanced, 3 mm 3 mm LFCSP and operates over the temperature range of C to + C. A fully populated evaluation board is also available. 9- Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 ADL3 TABLE OF CONTENTS Features... Functional Block Diagram... General Description... Revision History... Specifications... 3 AC Specifications... 3 DC Specifications... De-Embedded S-Parameters, VPOS = 3 V to V, RFIN = Port, VPOS = Port, RFOUT = Port 3... Absolute Maximum Ratings... ESD Caution... Pin Configuration And Function Descriptions... Typical Performance Characteristics MHz, VPOS = V MHz, VPOS = V... MHz, VPOS = V MHz, VPOS = V... REVISION HISTORY 9/7 Rev. B to Rev. C Change to Figure... Changes to Figure and Table... Change to Figure 3... Change to Figure... 7 Updated Outline Dimensions... Changes to Ordering Guide... Data Sheet 9 MHz, VPOS = 3 V... 9 MHz, VPOS = 3 V... MHz, VPOS = 3 V MHz, VPOS = 3 V... DC Characteristics... Basic Connections... Evaluation Board... 7 Soldering Information and Recommended PCB Land Pattern... 7 Tuning the ADL3 for Optimal Noise Figure... Tuning S... Tuning the LNA Input for Optimal Gain... 9 Tuning the LNA Input for Optimal Noise Figure... 9 of the LNA with S Matched... Outline Dimensions... Ordering Guide... /3 Rev. A to Rev. B Added Figure, Renumbered Sequentially... 9/9 Rev. to Rev. A Updated Maximum Junction Temperature Unit (Table )... / Revision : Initial Version Rev. C Page of

3 ADL3 SPECIFICATIONS AC SPECIFICATIONS TA = C, R =.3 kω; parameters include matching circuit, matched for optimal noise, unless otherwise noted. Table. 3 V V Parameter Conditions Min Typ Max Min Typ Max Unit FREQUEY = 9 MHz Gain (S).. db vs. Frequency ± MHz ±.3 ±.37 db vs. Temperature C TA ±. ±. db Noise Figure.. db Output Third-Order Intercept () Δf = MHz, POUT = dbm per tone. 3. dbm Output db Compression Point () 7.. dbm Input Return Loss () 7.. db Output Return Loss (S).. db Isolation (S).. db FREQUEY = 9 MHz Gain (S). 7.. db vs. Frequency ±3 MHz ±. ±. db vs. Temperature C TA ±. ±.7 db Noise Figure.9. db Output Third-Order Intercept () Δf = MHz, POUT = dbm per tone. 3. dbm Output db Compression Point () 7.7 dbm Input Return Loss () 9.. db Output Return Loss (S) 7.. db Isolation (S).. db FREQUEY = MHz Gain (S). 3. db vs. Frequency ± MHz ±.3 ±.3 db vs. Temperature C TA ±. ±. db Noise Figure.9.9 db Output Third-Order Intercept () Δf = MHz, POUT = dbm per tone dbm Output db Compression Point () 7. dbm Input Return Loss ().. db Output Return Loss (S).. db Isolation (S).. db FREQUEY = 3 MHz Gain (S). db vs. Frequency ± MHz ±.73 ±.7 db vs. Temperature C TA ±.7 ±.77 db Noise Figure.. db Output Third-Order Intercept () Δf = MHz, POUT = dbm per tone dbm Output db Compression Point () 7.3. dbm Input Return Loss ().. db Output Return Loss (S).. db Isolation (S) db Noise figure de-embedded to first matching component on input side. Rev. C Page 3 of

4 ADL3 Data Sheet DC SPECIFICATIONS Table. 3 V V Parameter Conditions Min Typ Max Min Typ Max Unit Supply Current 3 ma vs. Temperature C TA ± ±7 ma DE-EMBEDDED S-PARAMETERS, VPOS = 3 V TO V, RFIN = PORT, VPOS = PORT, RFOUT = PORT 3 Table 3. Frequency (GHz) (db/ang) S (db/ang) S3 (db/ang) S (db/ang) S (db/ang) S3 (db/ang) S3 (db/ang) S (db/ang) S33 (db/ang)../.9 37./.9./ /+./+9. / /./ 9../ 3.../../ /+. +/+.3/+. 3./ /+7 3./ 33.9./ /../ /+3. +/+7.9./+3../. +./+../ 3..3/+.. 9./. 3.9/. 3.7/+. +7./+77../ /.9 +.9/+7 9./..7/+.. /../ 7. 3./ /+7..3/+..7/. +3./+.7/.7./ / 7../. 3./+. +./+.3./+../+. +./+3./../ /+.3./ /+7../+../+. 7./. +/+ 7./../+3.../+3.9./ 7. 3./+. 9.7/+.7 +./+..3/.3 +.9/+9./. 3./+.3../+7.3./ 3./ / /+7. / 3. +./+7 / 3. 3./+. 9.3/+.3./ 73 3./+.7./ +./+../+ +9.3/+./+9 3./ /+7../+ 3./+. 3./ 7 +.3/ /+3 +./+ 33./+ 3.9/+77.../+7../ /+3. / 7 +./+. 3./ /+ 9./+33./+.3./+.7 9./+ 33./+../ +./+. 7./ /+ 7./+3./+9..7./+9..7/+ 33.3/ / 9 +./+..9/+37 +./+./+3./ /+.3/+7.9/+7../ +./+7../ /+./+39./ /+7./+73./+7../ 7 +./ /+ +./+ 3.3/+3./+. 9./+3 3./+7./+7../ +.7/+.7.7/+ +./+./+.7/+. 9.3/+.3/ 3.7/+../ +.7/+93.9./+ +./+ /+./ /+7 / 7 3./+3..9/ 3 +.7/+7.3/+ +.7/+./+./+33../+7 / 3./+.7.7/ 9 +.7/+./+9 +.3/+./+9./+../+./ 3./+.7./ +.7/+39./+7 +./+ 9./+7./+.7 7./ / 3./+9../ +.7/+ 9.3/ /+ 9./ 7.7/+.7./+ 3./ 3 3.3/+9../ +./+7./+ +3.3/+./.7/+ 3..9/+7 37./ 3./+9.7./ /./ +.9/+ 7./.7/+ 3..9/+ 37./ 9./+9..9/. +.7/ 3 7./ +./+ 7.3/./ /+ 3./ 9./+9.3.9/ /./ 9 +./+3.7/ 3./ /+ 3./ /+9..7/ 7 +./ 9..3/ +.7/+././ 7 3../+ 3./.7 9.3/+9.3./..3/ 7.7 / +/+.3/ 3./ 3..3/ /. 9./+9 3./ 3../../ +./+././ 3.7.7/+3 3/.9 3./+9..9/ 7..7/ 7../.9/+.9/ 3 / 3.7 /+3./ / / 3..9/ 3..9/ 9 3.9/+./ 9 7.9/ /+ 7.3/ 3 3.9/+ +.3/.3/+.3 7./ /+ 7.7/./ Rev. C Page of

5 ADL3 ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Supply Voltage, VPOS. V RF Input Level 7 dbm RF Input Level (with Ω Series Resistor on VPOS) dbm Internal Power Dissipation mw θja (Junction to Air) C/W Maximum Junction Temperature C Operating Temperature Range C to Storage Temperature Range C to + C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. C Page of

6 ADL3 Data Sheet PIN CONFIGURATION AND FUTION DESCRIPTIONS VBIAS VPOS RFIN 3 ADL3 TOP VIEW (Not to Scale) 7 RFOUT NOTES. = NO CONNECT.. CONNECT THE EXPOSED PAD TO A LOW IMPEDAE GROUND PLANE. Figure. Pin Configuration Table. Pin Function Descriptions Pin No. Mnemonic Description VBIAS Internal DC Bias. Connect this pin to VPOS through the R resistor. RFIN RF Input. This is the input to the LNA. 3,,, No Connection. No internal connection. 7 RFOUT RF Output. VPOS Supply Voltage. DC bias needs to be bypassed to ground using a low inductance capacitor. This pin is also used for output matching. See the Basic Connections section. EPAD Exposed Pad. Connect the exposed pad to a low impedance ground plane. 9- Rev. C Page of

7 ADL3 TYPICAL PERFORMAE CHARACTERISTICS 9 MHz, VPOS = V Matched for optimal noise figure, external matching circuit included.. S-PARAMETERS (db) 3 S S S Figure 3. Typical S-Parameters, Log Magnitude Figure. Noise Figure vs. Frequency at C, Multiple Devices 9- NOISE FIGURE AND (db) NOISE FIGURE Figure. Noise Figure, Gain,, and vs. Frequency 9- (db) Figure 7. Gain,, and vs. Temperature (dbm) Figure. Noise Figure vs. Temperature 9- P OUT PER TONE (dbm) Figure. vs. Output Power (POUT) and Temperature 9- Rev. C Page 7 of

8 ADL3 Data Sheet 9 MHZ, VPOS = V Matched for optimal noise figure, external matching circuit included.. S-PARAMETERS (db) 3 3 S S S Figure 9. Typical S-Parameters, Log Magnitude Figure. Noise Figure vs. Frequency at C, Multiple Devices NOISE FIGURE AND (db) 3 3 NOISE FIGURE (db) Figure. Noise Figure, Gain,, and vs. Frequency Figure 3. Gain,, and vs. Temperature (dbm) P OUT PER TONE (dbm) 9- Figure. Noise Figure vs. Temperature Figure. vs. Output Power (POUT) and Temperature Rev. C Page of

9 ADL3 MHz, VPOS = V Matched for optimal noise figure, external matching circuit included. S. S-PARAMETERS (db) S... S Figure. Typical S-Parameters, Log Magnitude 9-7 Figure. Noise Figure vs. Frequency at C, Multiple Devices 9- NOISE FIGURE AND (db) 3 3 NOISE FIGURE 7 9- (db) Figure. Noise Figure, Gain,, and vs. Frequency Figure 9. Gain,, and vs. Temperature (dbm) P OUT PER TONE (dbm) 9- Figure 7. Noise Figure vs. Temperature Figure. vs. Output Power (POUT) and Temperature Rev. C Page 9 of

10 ADL3 Data Sheet 3 MHz, VPOS = V Matched for optimal noise figure, external matching circuit included. S. S-PARAMETERS (db) S S Figure. Typical S-Parameters, Log Magnitude Figure. Noise Figure vs. Frequency at C, Multiple Devices 9- NOISE FIGURE AND (db) 3 3 NOISE FIGURE (db) Figure. Noise Figure, Gain,, and vs. Frequency Figure. Gain,, and vs. Temperature.... (dbm) Figure 3. Noise Figure vs. Temperature 9-3 P OUT PER TONE (dbm) Figure. vs. Output Power (POUT) and Temperature 9- Rev. C Page of

11 ADL3 9 MHz, VPOS = 3 V Matched for optimal noise figure, external matching circuit included. S-PARAMETERS (db) 3 S S S Figure 7. Typical S-Parameters, Log Magnitude Figure 3. Noise Figure vs. Frequency at C, Multiple Devices NOISE FIGURE AND (db) NOISE FIGURE 3 (db) Figure. Noise Figure, Gain,, and vs. Frequency Figure 3. Gain,, and vs. Temperature (dbm) P OUT PER TONE (dbm) 9- Figure 9. Noise Figure vs. Temperature Figure. vs. Output Power (POUT) and Temperature Rev. C Page of

12 ADL3 Data Sheet 9 MHz, VPOS = 3 V Matched for optimal noise figure, external matching circuit included. S. S-PARAMETERS (db) S S Figure 33. Typical S-Parameters, Log Magnitude Figure 3. Noise Figure vs. Frequency at C, Multiple Devices NOISE FIGURE AND (db) NOISE FIGURE (db) Figure 3. Noise Figure, Gain,, and vs. Frequency Figure 37. Gain,, and vs. Temperature (dbm) P OUT PER TONE (dbm) 9-3 Figure 3. Noise Figure vs. Temperature Figure 3. vs. Output Power (POUT) and Temperature Rev. C Page of

13 ADL3 MHz, VPOS = 3 V Matched for optimal noise figure, external matching circuit included.. S S-PARAMETERS (db) S... S Figure 39. Typical S-Parameters, Log Magnitude Figure. Noise Figure vs. Frequency at C, Multiple Devices NOISE FIGURE AND (db) NOISE FIGURE 7 9- (db) Figure. Noise Figure, Gain,, and vs. Frequency Figure 3. Gain,, and vs. Temperature (dbm) P OUT PER TONE (dbm) 9- Figure. Noise Figure vs. Temperature Figure. vs. Output Power (POUT) and Temperature Rev. C Page 3 of

14 ADL3 Data Sheet 3 MHz, VPOS = 3 V Matched for optimal noise figure, external matching circuit included. S. S-PARAMETERS (db) S S Figure. Typical S-Parameters, Log Magnitude Figure. Noise Figure vs. Frequency at C, Multiple Devices 9- NOISE FIGURE AND (db) 3 (db) NOISE FIGURE Figure. Noise Figure, Gain,, and vs. Frequency Figure 9. Gain,, and vs. Temperature (dbm) P OUT PER TONE (dbm) 9- Figure 7. Noise Figure vs. Temperature Figure. vs. Output Power (POUT) and Temperature Rev. C Page of

15 ADL3 DC CHARACTERISTICS SUPPLY CURRENT (ma) 7 7 VPOS = V 3 VPOS = 3V 3 SUPPLY CURRENT (ma) V, V, V, 3V, 3V, 3V, TEMPERATURE ( C) Figure. Supply Current vs. Temperature, 3 V and V 9- P OUT (dbm) Figure. Supply Current vs. POUT and Temperature, 3 V and V 9- Rev. C Page of

16 ADL3 BASIC CONNECTIONS The basic connections for operating the ADL3 are shown in Figure 3. Capacitor C provides the power supply decoupling. Inductor L (Coilcraft 3HQ or HP series) and Capacitor C (Murata High-Q GJM series or equivalent) provide the input impedance matching, and the output impedance matching is provided by either L or C3. Resistor R is used to set the supply current, and the value of R is indirectly proportional to the supply current (that is, increasing the value of R reduces the supply current). The recommended external components for selected frequencies are listed in Table 7. For V applications where the input power exceeds the input compression point of approximately 7 dbm, insert a series resistor (R) of at least Ω, with a high power rating (. W minimum), on the VPOS line to protect the device from the input power overdrive. In this case, reduce Resistor R from.3 kω to Ω to keep the supply current at around ma. With R =. Ω (Susumu RPS-R-F) and R = Ω, the gain and noise figure for the ADL3 are mostly unchanged. Table lists and at selected frequencies. For 3 V power supply applications, a series resistor is not necessary for the expected input overdrive powers up to dbm. RFIN C L 3 VBIAS RFIN R ADL3 Z VPOS RFOUT VPOS R L TR TR Data Sheet W C nf C3 Figure 3. ADL3 Basic Connections 7 RFOUT GND Table. ADL3 Performance at VPOS = V, C with R =. Ω and R = Ω Frequency (MHz) Noise Figure (db) Gain (db) (dbm) (dbm) (POUT = dbm) Rev. C Page of

17 ADL3 EVALUATION BOARD Figure shows the schematic of the ADL3 evaluation board. The board is powered by a single supply, and dc bias can be applied to the board through clip-on leads at VPOS and GND or through a -pin connector, W. The evaluation board comes optimized at 9 MHz from the factory, but it can be easily modified to work at any frequency between MHz and GHz. Table 7 lists the recommended components at various frequencies. VPOS R W GND Figure. Evaluation Board Layout (Bottom View) 9- RFIN C L 3 VBIAS RFIN R ADL3 VPOS RFOUT L TR TR C nf C DNP C3 C Ω Z Figure. Evaluation Board Schematic 7 RFOUT 9- SOLDERING INFORMATION AND RECOMMENDED PCB LAND PATTERN Figure 7 shows the recommended land pattern for ADL3. To minimize thermal impedance, the exposed pad on the package underside is soldered down to a ground plane. If multiple ground layers exist, they are stitched together using vias (a minimum of five vias is recommended). Pin 3 to Pin can be left unconnected or can be connected to ground. For more information on land pattern design and layout, refer to the AN-77 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP)..3mm.mm mm.7mm.7mm.3mm Figure 7. Recommended Land Pattern 9- Figure. Evaluation Board Layout (Top View) 9-3 Table 7. Recommended Components and Positions of Matching Components for Basic Connections Tuned for Optimal Noise Frequency (MHz) C (Size ) C (Size ) C3 (Size ) C (Size ) C (Size ) L (Size 3) L Size 3) R 3 (Size 3) R (Size 3) TR (mm) TR (mm) C Position Open Ω Open Open nf 9 nh nh.3 kω Ω C N/A 9. pf Ω Open Open nf. nh 3. nh.3 kω Ω C N/A 3.7 pf Ω. nf Open nf 3. nh Ω.3 kω Ω.. C 9 pf Ω. nf Open nf. nh Ω.3 kω Ω.... C pf Ω. nf Open nf. nh Ω.3 kω Ω C.7 pf Ω. nf Open nf. nh Ω.3 kω Ω.. C C3 3. pf Ω. nf Open nf. pf Ω.3 kω Ω 7... C The Murata GJM High-Q series capacitor is recommended for C. The Coilcraft High Q 3HQ or HP inductors are recommended for L and L. 3 If R = Ω, reduce R to Ω. If R = Ω, use a high power resistor (. W rating minimum). Note that at 3 MHz, a capacitor, not an inductor, is used at L. C3 Position Rev. C Page 7 of

18 ADL3 Data Sheet TUNING THE ADL3 FOR OPTIMAL NOISE FIGURE The ADL3 is a monolithic low noise amplifier (LNA) in a 3 mm 3 mm LFCSP. The evaluation board, as shipped from the factory, gives a noise figure of.9 db over a bandwidth of several hundred megahertz. The specific frequency where optimal noise is reached depends on the tuning. The bandwidth of the ADL3 is MHz to GHz, although noise figure degrades above. GHz as the gain begins to roll off. This section is based on Analog Devices, Inc., lab measurements. Although there are plots in which the Agilent Advanced Design System (ADS) environment is used, the data in these plots come entirely from Analog Devices lab measurements. TUNING S Tuning of the LNA begins with S (output tuning). Tuning of the LNA output is done by placing reactive components on the bias line, referred to in the schematic in Figure as VPOS. On the LNA evaluation board, S tuning is achieved by either the use of an inductor (L) on the bias line or a shunt capacitor (C3) on the bias line to ground. Typically, either L is required or C3 but not both. The evaluation board uses a slider on the bias line to make tuning for S as easy as possible. The slider is an area of ground etch adjacent to the bias line that is clear of solder mask. The bias line in this area is also free of solder mask. This allows a capacitor (C3) to be placed anywhere on the bias line to ground, which provides easy and accurate tuning for S. Note that the PCB layout shows two capacitors, C3 and C. Typically, only one of these capacitors is needed for good S tuning. The slider is seen in the LNA PCB layout in Figure as the area near the red arrows to the right of the bias line. With a Ω resistor in place of L, moving a nf capacitor from the top to the bottom effectively tunes S from MHz to 3 MHz. Table shows the component values and placement required for S tuning from MHz to MHz. For lower frequencies, higher values of L can be used to tune S, and for frequencies from 3. GHz to. GHz, smaller values of capacitors can be used on the slider. Table. Capacitor and Inductor Tuning and Placement for LNA S Tuning Frequency (MHz) L (nh) C3 (nf) C3 Placement 3. Open N/A Ω nf Ω nf Ω nf 3 Ω nf Ω nf Figure. PCB Layout for LNA Evaluation Board (Note Slider on Bias Line with Capacitor Placement for S Tuning Noted by Arrows) 9- Rev. C Page of

19 TUNING THE LNA INPUT FOR OPTIMAL LNAs are generally tuned for either gain or noise optimization, or some trade-off between the two. One figure of merit of an LNA is how much trade-off must be made for one of these parameters to optimize the other. With the ADL3, an of db to db at the input to the matching network can still be achieved typically when optimizing for noise. For optimal gain matching, the goal is to use a matching network that converts the input impedance of the LNA to the characteristic impedance of the system, typically Ω. Correct tuning for gain matching results in a conjugate match. That is, the impedance of the matching network at the LNA input, looking back toward the generator, is always the complex conjugate of the LNA input impedance when matched for gain. Once *, the complex conjugate of, is known, a matching circuit must be found that transforms the Ω system impedance into the conjugate impedance. To do this, the designer starts at the origin of the Smith Chart circle and finds components that move the Ω match to *. The related impedances for gain matching are shown in Figure 9. A Smith Chart representation of the conjugate match is shown in Figure. Ω Ω MATCHING NETWORK * LNA Figure 9. Matching LNA Input for Gain 9-7 ADL3 TUNING THE LNA INPUT FOR OPTIMAL NOISE FIGURE The point in the Smith Chart at which matching for optimal noise occurs is typically referred to as gamma optimal or ΓOPT. Typically, it is significantly different from the gain matching point; finding ΓOPT is not as obvious as the gain match. ΓOPT is a function of the semiconductor structure and characteristics of the LNA. The fabrication facility that produces the LNA typically has this information. ΓOPT can also be determined by doing source pull testing in the lab. Noise matching for the ADL3 is actually very easy because the area of the Smith Chart where the noise figure is optimal or near optimal is not confined to a narrow area around ΓOPT. This is very advantageous because it means that component variations play a smaller part in the board-to-board variation of noise figure. The matching area for optimal noise for the ADL3 is shown in Figure. Note that textbooks usually define noise circles as a conjugate match. However, for the purpose of this data sheet, the circle is a direct match. To find the correct matching circuit, the designer must start with the of the LNA and select components that move the to within this circle. An important aspect of the overall ADL3 ease of tuning is that as long as S is matched for a particular frequency, the noise matching area remains very consistent in its placement for that frequency. If S is matched, take the measured and move it into the red circle shown in Figure for optimal noise matching.. *.... Figure. Smith Chart Representation of Conjugate Match 9-. Figure. Area of Optimal Noise Matching for ADL3 9-9 Rev. C Page 9 of

20 ADL3 Data Sheet OF THE LNA WITH S MATCHED To determine the correct matching circuit for optimal noise, look at the results of for the various frequencies at which S was tuned earlier in the Tuning S section. Once is determined for a particular frequency, find the matching components that provided that match. Figure 3 and Figure show for the various frequencies. Again, these measurements are all based on S being matched at that particular frequency. Note that, for the examples shown in Figure 3 and Figure, is either in the lower left quadrant of the Smith Chart or slightly into the upper left. To move the impedance in the given noise circle, a series L component at the LNA input is required. The L values in the examples differ but a correct L value moves the match along the constant R circle up into the upper left quadrant of the Smith Chart. A shunt capacitor can then be added to move the match along a constant admittance line, down and to the right, directly into the center of the noise circle given in Figure. The solution for the structure of the match for the examples in Figure 3 and Figure is a series L to the input of the LNA and a shunt capacitor at the generator end of this inductor. The recommended components for matching at various frequencies are shown in Table 7. An example of the effect of the series L, shunt C match, based on the MHz example, is given in Figure. This example uses the output from the Agilent ADS Smith Chart tool. M M FREQUEY MHz =.77/.39 IMPEDAE = Z (.3 j.3) M FREQUEY GHz =./ 7.9 IMPEDAE = Z (. j.7) FREQUEY (MHz TO GHz) Figure 3. of ADL3 with S Matched at GHz M M FREQUEY MHz =./. IMPEDAE = Z (.9 j.) M FREQUEY 3.GHz =.9/3. IMPEDAE = Z (.9 + j.3) M 9- M 9- FREQUEY (MHz TO GHz) Figure. of ADL3 with S Matched at 3. GHz 9- Figure. Example of Series L, Shunt C Matching Network for ΓOPT Rev. C Page of

21 ADL3 OUTLINE DIMENSIONS SQ.9. BSC.7 DETAIL A (JEDEC 9) PIN INDEX AREA TOP VIEW...3 EXPOSED PAD BOTTOM VIEW..3 PIN INDIC ATOR AREA OPTIONS (SEE DETAIL A) PKG SEATING PLANE SIDE VIEW.3... MAX. NOM COPLANARITY..3 REF COMPLIANT TOJEDEC STANDARDS MO-9-WEED- Figure. -Lead Lead Frame Chip Scale Package [LFCSP] 3 mm 3 mm Body and.7 mm Package Height (CP--3) Dimensions shown in millimeters FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUTION DESCRIPTIONS SECTION OF THIS DATA SHEET. --7-A ORDERING GUIDE Model Temperature Range Package Description Package Option Branding ADL3ACPZ-R7 C to -Lead LFCSP, 7 Tape and Reel CP--3 QJ ADL3-EVALZ Evaluation Board Z = RoHS Compliant Part. 7 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D9--9/7(C) Rev. C Page of