1 Ω Typical On Resistance, ±5 V, +12 V, +5 V, and +3.3 V Dual SPDT Switches ADG1636

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1 FEATURES Ω typical on resistance.2 Ω on resistance flatness ±3.3 V to ±8 V dual supply operation 3.3 V to 6 V single supply operation No VL supply required 3 V logic-compatible inputs Rail-to-rail operation Continuous current per channel LFCSP: 385 ma TSSOP: 238 ma 6-lead TSSOP and 6-lead, 4 mm 4 mm LFCSP Ω Typical On Resistance, ±5 V, +2 V, +5 V, and +3.3 V Dual SPDT Switches FUNCTIONAL BLOCK DIAGRAMS SA D SB IN IN2 S2A D2 S2B APPLICATIONS Communication systems Medical systems Audio signal routing Video signal routing Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Relay replacements GENERAL DESCRIPTION The is a monolithic CMOS device containing two independently selectable single-pole/double-throw (SPDT) switches. An EN input is used to enable or disable the device. When disabled, all channels are switched off. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. Both switches exhibit break-before-make switching action for use in multiplexer applications. The ultralow on resistance of these switches make them ideal solutions for data acquisition and gain switching applications where low on resistance and distortion is critical. The on resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching audio signals. NOTES. SWITCHES SHOWN FOR A LOGIC INPUT. Figure. 6-Lead TSSOP SA D SB LOGIC IN IN2 EN S2A D2 S2B NOTES. SWITCHES SHOWN FOR A INPUT LOGIC. Figure 2. 6-Lead LFCSP The CMOS construction ensures ultralow power dissipation, making the devices ideally suited for portable and batterypowered instruments. PRODUCT HIGHLIGHTS..6 Ω maximum on resistance over temperature. 2. Minimum distortion: THD + N =.7% V logic-compatible digital inputs: VINH = 2. V, VINL =.8 V. 4. No VL logic power supply required. 5. Ultralow power dissipation: <6 nw lead TSSOP and 6-lead 4 mm 4 mm LFCSP Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 TABLE OF CONTENTS Features... Applications... General Description... Functional Block Diagrams... Product Highlights... Revision History... 2 Specifications... 3 ±5 V Dual Supply ingle Supply ingle Supply ingle Supply...6 Continuous Current per Channel, S or D...7 Absolute Maximum Ratings...8 ESD Caution...8 Pin Configurations and Function Descriptions...9 Typical Performance Characteristics... Test Circuits... 3 Terminology... 5 Outline Dimensions... 6 Ordering Guide... 6 REVISION HISTORY 3/6 Rev. A to Rev. B Changed CP-6-3 to CP Throughout Changes to Figure 3, Figure 4, and Table Updated Outline Dimensions... 6 Changes to Ordering Guide /9 Rev. to Rev. A Changes to Table /9 Revision : Initial Version Rev. B Page 2 of 6

3 SPECIFICATIONS ±5 V DUAL SUPPLY VDD = +5 V ± %, VSS = 5 V ± %, GND = V, unless otherwise noted. Table. Parameter 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range VDD to VSS V On Resistance (RON) Ω typ VS = ±4.5 V, IS = ma; see Figure Ω max VDD = ±4.5 V, VSS = ±4.5 V On Resistance Match Between Channels ( RON).4 Ω typ VS = ±4.5 V, IS = ma.8.9. Ω max On Resistance Flatness (RFLAT(ON)).2 Ω typ VS = ±4.5 V, IS = ma Ω max LEAKAGE CURRENTS VDD = +5.5 V, VSS = 5.5 V Source Off Leakage, IS (Off ) ±. na typ VS = ±4.5 V, VD = 4.5 V; see Figure 24 ±.25 ± ±4 na max Drain Off Leakage, ID (Off ) ±. na typ VS = ±4.5V, VD = 4.5 V; see Figure 24 ±.25 ±2 ± na max Channel On Leakage, ID, IS (On) ±.3 na typ VS = VD = ±4.5 V; see Figure 25 ±.6 ±2 ±2 na max DIGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH.5 µa typ VIN = VGND or VDD ±. µa max Digital Input Capacitance, CIN 5 pf typ DYNAMIC CHARACTERISTICS Transition Time, ttransition 3 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 2.5 V; see Figure 3 ton (EN) 9 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 2.5 V; see Figure 3 toff (EN) 82 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 2.5 V; see Figure 3 Break-Before-Make Time Delay, td 3 ns typ RL = 3 Ω, CL = 35 pf 7 ns min VS = VS2 = 2.5 V; see Figure 3 Charge Injection 3 pc typ VS = V, RS = Ω, CL = nf; see Figure 32 Off Isolation 7 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 26 Channel-to-Channel Crosstalk 9 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 28 Total Harmonic Distortion + Noise (THD + N).7 % typ RL = Ω, 5 V p-p, f = 2 Hz to 2 khz; see Figure 29 3 db Bandwidth 25 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 27 CS (Off ) 68 pf typ VS = V, f = MHz CD (Off ) 27 pf typ VS = V, f = MHz CD, CS (On) 22 pf typ VS = V, f = MHz POWER REQUIREMENTS VDD = +5.5 V, VSS = 5.5 V IDD. µa typ Digital inputs = V or VDD. µa max VDD/VSS ±3.3/±8 V min/max Guaranteed by design, not subject to production test. Rev. B Page 3 of 6

4 2 INGLE SUPPLY VDD = 2 V ± %, VSS = V, GND = V, unless otherwise noted. Table 2. Parameter 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to VDD V On Resistance (RON).95 Ω typ VS = V to V, IS = ma; see Figure Ω max VDD =.8 V, VSS = V On Resistance Match Between Channels ( RON).3 Ω typ VS = V, IS = ma Ω max On Resistance Flatness (RFLAT(ON)).2 Ω typ VS = V to V, IS = ma Ω max LEAKAGE CURRENTS VDD = 3.2 V, VSS = V Source Off Leakage, IS (Off ) ±. na typ VS = V/ V, VS = V/ V; see Figure 24 ±.25 ± ±4 na max Drain Off Leakage, ID (Off ) ±. na typ VS = V/ V, VS = V/ V; see Figure 24 ±.25 ±2 ± na max Channel On Leakage, ID, IS (On) ±.3 na typ VS = VD = V or V; see Figure 25 ±.6 ±2 ±2 na max DIGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH. µa typ VIN = VGND or VDD ±. µa max Digital Input Capacitance, CIN 5 pf typ DYNAMIC CHARACTERISTICS Transition Time, ttransition ns typ RL = 3 Ω, CL = 35 pf ns max VS = 8 V; see Figure 3 ton (EN) 8 ns typ RL = 3 Ω, CL = 35 pf 95 3 ns max VS = 8 V; see Figure 3 toff (EN) 33 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 8 V; see Figure 3 Break-Before-Make Time Delay, td 25 ns typ RL = 3 Ω, CL = 35 pf 7 ns min VS = VS2 = 8 V; see Figure 3 Charge Injection 5 pc typ VS = 6 V, RS = Ω, CL = nf; see Figure 32 Off Isolation 7 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 26 Channel-to-Channel Crosstalk 9 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 28 Total Harmonic Distortion + Noise (THD + N).3 % typ RL = Ω, 5 V p-p, f = 2 Hz to 2 khz; see Figure 29 3 db Bandwidth 27 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 27 CS (Off ) 65 pf typ VS = 6 V, f = MHz CD (Off ) 2 pf typ VS = 6 V, f = MHz CD, CS (On) 26 pf typ VS = 6 V, f = MHz POWER REQUIREMENTS VDD = 2 V IDD. µa typ Digital inputs = V or VDD µa max IDD 23 µa typ Digital inputs = 5 V 36 µa max VDD 3.3/6 V min/max Guaranteed by design, not subject to production test. Rev. B Page 4 of 6

5 5 INGLE SUPPLY VDD = 5 V ± %, VSS = V, GND = V, unless otherwise noted. Table 3. Parameter 25 C 4 C to +85 C 4 C to 25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to VDD V On Resistance (RON).7 Ω typ VS = V to 4.5 V, IS = ma; see Figure Ω max VDD = 4.5 V, VSS = V On Resistance Match Between Channels ( RON).5 Ω typ VS = V to 4.5 V, IS = ma Ω max On Resistance Flatness (RFLAT(ON)).4 Ω typ VS = V to 4.5 V, IS = ma Ω max LEAKAGE CURRENTS VDD = 5.5 V, VSS = V Source Off Leakage, IS (Off ) ±.5 na typ VS = V/4.5 V, VD = 4.5 V/ V; see Figure 24 ±.25 ± ±4 na max Drain Off Leakage, ID (Off ) ±.5 na typ VS = V/4.5 V, VD = 4.5 V/ V; see Figure 24 ±.25 ±2 ± na max Channel On Leakage, ID, IS (On) ±. na typ VS = VD = V or 4.5 V; see Figure 25 ±.6 ±2 ±2 na max DIGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH. µa typ VIN = VGND or VDD ±. µa max Digital Input Capacitance, CIN 5 pf typ DYNAMIC CHARACTERISTICS Transition Time, ttransition 6 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 2.5 V; see Figure 3 ton (EN) 32 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 2.5 V; see Figure 3 toff (EN) 2 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 2.5 V; see Figure 3 Break-Before-Make Time Delay, td 3 ns typ RL = 3 Ω, CL = 35 pf 7 ns min VS = VS2 = 2.5 V; see Figure 3 Charge Injection 7 pc typ VS = 2.5 V, RS = Ω, CL = nf; see Figure 32 Off Isolation 7 db typ RL = 5 Ω, CL = 5 pf, f = khz; see Figure 26 Channel-to-Channel Crosstalk 9 db typ RL = 5 Ω, CL = 5 pf, f = khz; see Figure 28 Total Harmonic Distortion + Noise (THD + N).9 % typ RL = Ω, f = 2 Hz to 2 khz, VS = 3.5 V p-p; see Figure 29 3 db Bandwidth 26 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 27 CS (Off ) 76 pf typ VS = 2.5 V, f = MHz CD (Off ) 45 pf typ VS = 2.5 V, f = MHz CD, CS (On) 237 pf typ VS = 2.5 V, f = MHz POWER REQUIREMENTS VDD = 5.5 V IDD. µa typ Digital inputs = V or VDD.. µa max VDD 3.3/6 V min/max Guaranteed by design, not subject to production test. Rev. B Page 5 of 6

6 3.3 INGLE SUPPLY VDD = 3.3 V, VSS = V, GND = V, unless otherwise noted. Table 4. Parameter 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to VDD V On Resistance (RON) Ω typ VS = V to VDD, IS = ma; see Figure 23 VDD = 3.3 V, VSS = V On Resistance Match Between Channels ( RON) Ω typ VS = V to VDD, IS = ma On Resistance Flatness (RFLAT(ON)) Ω typ VS = V to VDD, IS = ma LEAKAGE CURRENTS VDD = 3.6 V, VSS = V Source Off Leakage, IS (Off) ±.2 na typ VS =.6 V/3 V, VD = 3 V/.6 V; see Figure 24 ±.25 ± ±4 na max Drain Off Leakage, ID (Off ) ±.2 na typ VS =.6 V/3 V, VD = 3 V/.6 V; see Figure 24 ±.25 ±2 ± na max Channel On Leakage, ID, IS (On) ±.5 na typ VS = VD =.6 V or 3 V; see Figure 25 ±.6 ±2 ±2 na max DIGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH. µa typ VIN = VGND or VDD ±. µa max Digital Input Capacitance, CIN 5 pf typ DYNAMIC CHARACTERISTICS Transition Time, ttransition 275 ns typ RL = 3 Ω, CL = 35 pf ns max VS =.5 V; see Figure 3 ton (EN) 225 ns typ RL = 3 Ω, CL = 35 pf ns max VS =.5 V; see Figure 3 toff (EN) 34 ns typ RL = 3 Ω, CL = 35 pf ns max VS =.5 V; see Figure 3 Break-Before-Make Time Delay, td 5 ns typ RL = 3 Ω, CL = 35 pf 28 ns min VS = VS2 =.5 V; see Figure 3 Charge Injection 5 pc typ VS =.5 V, RS = Ω, CL = nf; see Figure 32 Off Isolation 7 db typ RL = 5 Ω, CL = 5 pf, f = khz; see Figure 26 Channel-to-Channel Crosstalk 9 db typ RL = 5 Ω, CL = 5 pf, f = khz; see Figure 28 Total Harmonic Distortion + Noise (THD + N).9 % typ RL = 33 Ω, f = 2 Hz to 2 khz, VS = 2 V p-p; see Figure 29 3 db Bandwidth 26 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 27 CS (Off ) 8 pf typ VS =.5 V, f = MHz CD (Off ) 53 pf typ VS =.5 V, f = MHz CD, CS (On) 243 pf typ VS =.5 V, f = MHz POWER REQUIREMENTS VDD = 3.6 V IDD. µa typ Digital inputs = V or VDD.. µa max VDD 3.3/6 V min/max Guaranteed by design, not subject to production test. Rev. B Page 6 of 6

7 CONTINUOUS CURRENT PER CHANNEL, S OR D Table 5. Parameter 25 C 85 C 25 C Unit CONTINUOUS CURRENT, S OR D VDD = +5 V, VSS = 5 V TSSOP (θja = 5.4 C/W) ma maximum LFCSP (θja = 48.7 C/W) ma maximum VDD = 2 V, VSS = V TSSOP (θja = 5.4 C/W) ma maximum LFCSP (θja = 48.7 C/W) ma maximum VDD = 5 V, VSS = V TSSOP (θja = 5.4 C/W) ma maximum LFCSP (θja = 48.7 C/W) ma maximum VDD = 3.3 V, VSS = V TSSOP (θja = 5.4 C/W) ma maximum LFCSP (θja = 48.7 C/W) ma maximum Rev. B Page 7 of 6

8 ABSOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise noted. Table 6. Parameter Rating VDD to VSS 8 V VDD to GND.3 V to +8 V VSS to GND +.3 V to 8 V Analog Inputs VSS.3 V to VDD +.3 V or 3 ma, whichever occurs first Digital Inputs GND.3 V to VDD +.3 V or 3 ma, whichever occurs first Peak Current, S or D 85 ma (pulsed at ms, % duty cycle maximum) Continuous Current, S or D 2 Data + 5% Operating Temperature Range Industrial (Y Version) 4 C to +25 C Storage Temperature Range 65 C to +5 C Junction Temperature 5 C θja Thermal Impedance 6-Lead TSSOP (2-Layer Board) 5.4 C/W 6-Lead LFCSP (4-Layer Board) 48.7 C/W Reflow Soldering Peak 26 C Temperature, Pb free Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Overvoltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. 2 See Table 5. Rev. B Page 8 of 6

9 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS IN SA D SB S GND TOP VIEW (Not to Scale) EN 3 2 S2B D2 S2A 9 IN2 NOTES. = NO INTERNAL CONNECTION. Figure 3. 6-Lead TSSOP Pin Configuration D SA IN IN2 S2A 2 EN SB 2 S 3 TOP VIEW (Not to Scale) S2B GND 4 9 D2 NOTES. = NO INTERNAL CONNECTION. 2. TIE THE EXPOSED PAD TO THE SUBSTRATE, S. Figure 4. 6-Lead LFCSP Pin Configuration Table 7. Pin Function Descriptions Pin No. TSSOP LFCSP Mnemonic Description 5 IN Logic Control Input. 2 6 SA Source Terminal. This pin can be an input or output. 3 D Drain Terminal. This pin can be an input or output. 4 2 SB Source Terminal. This pin can be an input or output. 5 3 VSS Most Negative Power Supply Potential. 6 4 GND Ground ( V) Reference. 7, 8, 5, 6 5, 7, 3, 4 No Internal Connection. 9 6 IN2 Logic Control Input. 8 S2A Source Terminal. This pin can be an input or output. 9 D2 Drain Terminal. This pin can be an input or output. 2 S2B Source Terminal. This pin can be an input or output. 3 VDD Most Positive Power Supply Potential. 4 2 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are off. When this pin is high, the Ax logic inputs determine the on switches. N/A EPAD Exposed Pad. Tie the exposed pad to the substrate, VSS. N/A means not applicable. Table 8. TSSOP Truth Table EN INx SxA SxB X Off Off Off On On Off Table 9. LFCSP Truth Table EN INx SxA SxB X Off Off Off On On Off Rev. B Page 9 of 6

10 TYPICAL PERFORMANCE CHARACTERISTICS ON RESISTANCE (Ω) T A = 25 C = +3.3V S = 3.3V S = 5V = +8V S = 8V ON RESISTANCE (Ω) T A = +25 C T A = +85 C T A = +25 C T A = 4 C = 2V S = V OR V D VOLTAGE (V) Figure 5. On Resistance as a Function of VD (VS) for Dual Supply OR V D VOLTAGE (V) Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures, 2 ingle Supply ON RESISTANCE (Ω) T A = 25 C = 3.3V S = V = 5V S = V ON RESISTANCE (Ω) T A = +25 C T A = +85 C T A = +25 C T A = 4 C = 5V S = V. = 2V S = V = 6V S = V OR V D VOLTAGE (V) Figure 6. On Resistance as a Function of VD (VS) for Single Supply OR V D VOLTAGE (V) Figure 9. On Resistance as a Function of VD (VS) for Different Temperatures, 5 ingle Supply = 3.3V S = V ON RESISTANCE (Ω)..8.6 T A = +25 C T A = +85 C T A = +25 C S = 5V T A = 4 C OR V D VOLTAGE (V) Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures, ±5 V Dual Supply ON RESISTANCE (Ω) T A = +25 C T A = +85 C T A = +25 C T A = 4 C OR V D VOLTAGE (V) Figure. On Resistance as a Function of VD (VS) for Different Temperatures, 3.3 ingle Supply Rev. B Page of 6

11 5 I D, I S (ON) +, + I D (OFF), LEAKAGE CURRENT (na) 5 I S (OFF) +, I S (OFF), + 5 I D, I S (ON), I D (OFF) +, TEMPERATURE ( C) LEAKAGE CURRENT (na) I S (OFF) +, I S (OFF), + 2 I D (OFF) +, TEMPERATURE ( C) I D, I S (OFF) +, + I D, I S (OFF), I D (OFF), Figure. Leakage Currents as a Function of Temperature, ±5 V Dual Supply Figure 4. Leakage Currents as a Function of Temperature, 3.3 ingle Supply LEAKAGE CURRENT (na) TEMPERATURE ( C) I D, I S (ON) +, + I D (OFF), + I S (OFF) +, I D, I S (ON), I S (OFF), + I D (OFF) +, I DD (µa) I DD = +2V I SS = V I DD = +5V I SS = 5V I DD = +5V I SS = V I DD = +3.3V I SS = V LOGIC (V) I DD PER CHANNEL T A = 25 C Figure 2. Leakage Currents as a Function of Temperature, 2 ingle Supply Figure 5. IDD vs. Logic Level 2 3 LEAKAGE CURRENT (na) 5 5 I S (OFF) +, I S (OFF), + I D (OFF) +, TEMPERATURE ( C) I D, I S (OFF) +, + I D, I S (OFF), I D (OFF), CHARGE INJECTION (pc) = +3.3V S = V (V) S = 5V S = V = +2V S = V Figure 3. Leakage Currents as a Function of Temperature, 5 ingle Supply Figure 6. Charge Injection vs. Source Voltage Rev. B Page of 6

12 TIME (ns) = +3.3V, S = V, S = V INSERTION LOSS (db) T A = 25 C S = 5V, S = 5V = +2V, S = V TEMPERATURE ( C) k k k M M M G FREQUENCY (Hz) Figure 7. ton/toff Times vs. Temperature Figure 2. On Response vs. Frequency OFF ISOLATION (db) k T A = 25 C S = 5V k k M M M G FREQUENCY (Hz) ACPSRR (db) k T A = 25 C S = 5V k NO DECOUPLING CAPACITORS DECOUPLING CAPACITORS k M M FREQUENCY (Hz) Figure 8. Off Isolation vs. Frequency Figure 2. ACPSRR vs. Frequency 2 4 T A = 25 C S = 5V ADJACENT R L = Ω T A = 25 C = +3.3V = 2V p-p CROSSTALK (db) NON-ADJACENT THD + N (%) = +2V = 5V p-p = 3.5V p-p S = 5V = 5V p-p 4 k k k M M M G FREQUENCY (Hz) k k 5k FREQUENCY (Hz) 2k 25k Figure 9. Crosstalk vs. Frequency Figure 22. THD + N vs. Frequency Rev. B Page 2 of 6

13 TEST CIRCUITS DD S.µFV.µF S NETWORK ANALYZER 5Ω INx SxA SxB 5Ω SxA/SxB V GND R L 5Ω I DS Figure 23. On Resistance OFF ISOLATION = 2 log Figure 26. Off Isolation DD S.µFV.µF S NETWORK ANALYZER 5Ω INx SxA SxB 5Ω I S (OFF) A SxA/SxB I D (OFF) A GND R L 5Ω V D WITH SWITCH INSERTION LOSS = 2 log WITHOUT SWITCH Figure 24. Off Leakage Figure 27. Bandwidth DD S.µFV.µF NETWORK ANALYZER R L 5Ω SxA SxB S R L 5Ω INx SxA/SxB I D (ON) A GND V D = NO INTERNAL CONNECTTION. Figure 25. On Leakage CHANNEL-TO-CHANNEL CROSSTALK = 2 log Figure 28. Channel-to-Channel Crosstalk Rev. B Page 3 of 6

14 DD S.µFV.µF INx SxA/SxB GND S R L Ω Figure 29. THD + Noise AUDIO PRECISION R S V p-p µF S.µF 5% 5% SxB SxA S 5% 5% INx R L 3Ω C L 35pF 9% 9% GND t ON t OFF Figure 3. Switching Times.µF S.µF S SxB SxA INx R L 3Ω C L 35pF 8% GND t BBM t BBM Figure 3. Break-Before-Make Time Delay.µF S.µF S SxB SxA INx GND C L nf NC (NORMALLY CLOSED SWITCH) (NORMALLY OPEN SWITCH) Δ ON Q INJ = C L Δ OFF Figure 32. Charge Injection Rev. B Page 4 of 6

15 TERMINOLOGY IDD The positive supply current. ISS The negative supply current. VD (VS) The analog voltage on Terminal D and Terminal S. RON The ohmic resistance between Terminal D and Terminal S. RFLAT(ON) Flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. ID (Off) The drain leakage current with the switch off. ID, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic. VINH The minimum input voltage for Logic. IINL (IINH) The input current of the digital input. CS (Off) The off switch source capacitance, which is measured with reference to ground. CD (Off) The off switch drain capacitance, which is measured with reference to ground. CD, CS (On) The on switch capacitance, which is measured with reference to ground. ttransition The delay time between the 5% and 9% points of the digital input and switch on condition when switching from one address state to another. ton (EN) The delay between applying the digital control input and the output switching on. See Figure 3. toff (EN) The delay between applying the digital control input and the output switching off. See Figure 3. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3 db. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitude plus noise of the signal to the fundamental. AC Power Supply Rejection Ratio (ACPSRR) The ratio of the amplitude of signal on the output to the amplitude of the modulation. This is a measure of the ability of the device to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of.62 V p-p. CIN The digital input capacitance. Rev. B Page 5 of 6

16 OUTLINE DIMENSIONS BSC 8 PIN INDICATOR.5.5 PIN.65 BSC.3.9 COPLANARITY..2 MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-53-AB Figure Lead Thin Shrink Small Outline Package [TSSOP] (RU-6) Dimensions shown in millimeters SQ BSC EXPOSED PAD 6 PIN INDICATOR SQ SEATING PLANE TOP VIEW MAX.2 NOM COPLANARITY.8.2 REF BOTTOM VIEW COMPLIANT TO JEDEC STANDARDS MO-22-WGGC. Figure Lead Lead Frame Chip Scale Package [LFCSP] 4 mm 4 mm Body and.75 mm Package Height (CP-6-26) Dimensions shown in millimeters FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. ORDERING GUIDE Model Temperature Range Package Description Package Option BRUZ 4 C to +25 C 6-Lead Thin Shrink Small Outline Package [TSSOP] RU-6 BRUZ-REEL 4 C to +25 C 6-Lead Thin Shrink Small Outline Package [TSSOP] RU-6 BRUZ-REEL7 4 C to +25 C 6-Lead Thin Shrink Small Outline Package [TSSOP] RU-6 BCPZ-REEL 4 C to +25 C 6-Lead Lead Frame Chip Scale Package [LFCSP] CP-6-26 BCPZ-REEL7 4 C to +25 C 6-Lead Lead Frame Chip Scale Package [LFCSP] CP-6-26 Z = RoHS Compliant Part A Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D /6(B) Rev. B Page 6 of 6

1.5 Ω On Resistance, ±15 V/12 V/±5 V, icmos, Dual SPDT Switch ADG1436

1.5 Ω On Resistance, ±15 V/12 V/±5 V, icmos, Dual SPDT Switch ADG1436 Data Sheet.5 Ω On Resistance, ±5 V/2 V/±5 V, icmos, Dual SPDT Switch ADG436 FEATURES.5 Ω on resistance.3 Ω on-resistance flatness. Ω on-resistance match between channels Continuous current per channel