1200 MHz to 2500 MHz Balanced Mixer, LO Buffer, IF Amplifier, and RF Balun ADL5355

Transcription

1 MHz to MHz Balanced Mixer, LO Buffer, IF Amplifier, and RF Balun ADL3 FEATURES FUNCTIONAL BLOCK DIAGRAM RF frequency range of MHz to MHz IF frequency range of 3 MHz to MHz Power conversion gain:. db SSB noise figure of 9. db SSB noise figure with dbm blocker of db Input IP3 of 7 dbm Input P1dB of. dbm Typical LO drive of dbm Single-ended, Ω RF and LO input ports High isolation SPDT LO input switch Single-supply operation: 3.3 V to V Exposed paddle mm mm, -lead LFCSP 1 V HBM/ V FICDM ESD performance VPIF RFIN RFCT COMM 1 3 IFGM IFOP IFON PWDN LEXT BIAS GENERATOR ADL LOI VPSW VGS1 VGS APPLICATIONS Cellular base station receivers Transmit observation receivers Radio link downconverters GENERAL DESCRIPTION The ADL3 uses a highly linear, doubly balanced passive mixer core along with integrated RF and LO balancing circuitry to allow for single-ended operation. The ADL3 incorporates an RF balun, allowing for optimal performance over a MHz to MHz RF input frequency range using low-side LO injection for RF frequencies from 17 MHz to MHz and high-side LO injection for RF frequencies from MHz to 17 MHz. The balanced passive mixer arrangement provides good LO-to-RF leakage, typically better than 39 dbm, and excellent intermodulation performance. The balanced mixer core also provides extremely high input linearity, allowing the device to be used in demanding cellular applications where inband blocking signals may otherwise result in the degradation of dynamic performance. A high linearity IF buffer amplifier follows the passive mixer core to yield a typical power conversion gain of. db and can be used with a wide range of output impedances. COMM NC = NO CONNECT 7 9 VLO3 LGM3 VLO LOSW NC Figure LOI1 The ADL3 provides two switched LO paths that can be used in TDD applications where it is desirable to rapidly switch between two local oscillators. LO current can be externally set using a resistor to minimize dc current commensurate with the desired level of performance. For low voltage applications, the ADL3 is capable of operation at voltages down to 3.3 V with substantially reduced current. Under low voltage operation, an additional logic pin is provided to power down (< µa) the circuit when desired. The ADL3 is fabricated using a BiCMOS high performance IC process. The device is available in a mm mm, -lead LFCSP and operates over a C to + C temperature range. An evaluation board is also available. Table 1. Passive Mixers Single RF Frequency (MHz) Mixer Single Mixer and IF Amp Dual Mixer and IF Amp to 17 ADL37 ADL37 ADL3 to ADL3 ADL3 ADL3 3 to 9 ADL33 ADL33 ADL3-1 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 ADL3 TABLE OF CONTENTS Features... 1 Applications... 1 General Description... 1 Functional Block Diagram... 1 Revision History... Specifications... 3 V Performance V Performance... Spur Tables... Absolute Maximum Ratings... ESD Caution... Pin Configuration and Function Descriptions... 7 Typical Performance Characteristics... V Performance V Performance... 1 Circuit Description... 1 RF Subsystem... 1 LO Subsystem Applications Information... 1 Basic Connections... 1 IF Port... 1 Bias Resistor Selection... 1 Mixer VGS Control DAC... 1 Evaluation Board... Outline Dimensions... 3 Ordering Guide... 3 REVISION HISTORY /1 Rev. to Rev. A Added Table 1; Renumbered Sequentially... 1 Changes to Figure... 7 Deleted R9 = 1.1 kω, V Performance Section... Deleted Figure 1; Renumbered Sequentially... 1 Changes to Figure... 1 Changes to Figure... Changed R9 = 1.1 kω to R9 = 1.7 kω, Table Updated Outline Dimensions... 3 Changes to Ordering Guide /9 Revision : Initial Version Rev. A Page of 3

3 ADL3 SPECIFICATIONS VS = V, I S = 19 ma, TA = C, frf = 19 MHz, flo = 17 MHz, LO power = dbm, ZO = Ω, unless otherwise noted. Table. Parameter Conditions Min Typ Max Unit RF INPUT INTERFACE Return Loss Tunable to > db over a limited bandwidth db Input Impedance Ω RF Frequency Range MHz OUTPUT INTERFACE Output Impedance Differential impedance, f = MHz 3.7 Ω pf IF Frequency Range 3 MHz DC Bias Voltage 1 Externally generated V LO INTERFACE LO Power + dbm Return Loss 1 db Input Impedance Ω LO Frequency Range 3 7 MHz POWER-DOWN (PWDN) INTERFACE PWDN Threshold 1. V Logic Level. V Logic 1 Level 1. V PWDN Response Time Device enabled, IF output to 9% of its final level 1 ns Device disabled, supply current < ma ns PWDN Input Bias Current Device enabled. µa Device disabled 7 µa 1 Apply the supply voltage from the external circuit through the choke inductors. PWDN function is intended for use with VS 3. V only. Rev. A Page 3 of 3

4 ADL3 V PERFORMANCE VS = V, IS = 19 ma, TA = C, frf = 19 MHz, flo = 17 MHz, LO power = dbm, VGS = VGS1 = V, and ZO = Ω, unless otherwise noted. Table 3. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE Power Conversion Gain Including :1 IF port transformer and PCB loss db Voltage Conversion Gain ZSOURCE = Ω, differential ZLOAD = Ω differential 1.7 db SSB Noise Figure 9. db SSB Noise Figure Under Blocking dbm blocker present ± MHz from wanted RF input, db LO source filtered Input Third-Order Intercept (IIP3) frf1 = 199. MHz, frf = 19. MHz, flo = 17 MHz, 7 dbm each RF tone at dbm Input Second-Order Intercept (IIP) frf1 = 19 MHz, frf = 19 MHz, flo = 17 MHz, dbm each RF tone at dbm Input 1 db Compression Point (IP1dB). dbm LO-to-IF Leakage Unfiltered IF output. dbm LO-to-RF Leakage 39 dbm RF-to-IF Isolation 33 dbc IF/ Spurious dbm input power 9 dbc IF/3 Spurious dbm input power 73 dbc POWER SUPPLY Positive Supply Voltage.. V Quiescent Current LO supply, resistor programmable ma IF supply, resistor programmable 9 ma Total Quiescent Current VS = V 19 ma 3.3 V PERFORMANCE VS = 3.3 V, IS = ma, TA = C, frf = 19 MHz, flo = 17 MHz, LO power = dbm, R9 = Ω, R1 = Ω, VGS = VGS1 = V, and ZO = Ω, unless otherwise noted. Table. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE Power Conversion Gain Including :1 IF port transformer and PCB loss 9 db Voltage Conversion Gain ZSOURCE = Ω, differential ZLOAD = Ω differential 1.3 db SSB Noise Figure.7 db Input Third-Order Intercept (IIP3) frf1 = 199. MHz, frf = 19. MHz, flo = 17 MHz, dbm each RF tone at dbm Input Second-Order Intercept (IIP) frf1 = 19 MHz, frf = 19 MHz, flo = 17 MHz, dbm each RF tone at dbm Input 1 db Compression Point (IP1dB) 7 dbm POWER INTERFACE Supply Voltage V Quiescent Current Resistor programmable ma Power-Down Current Device disabled 1 µa Rev. A Page of 3

5 ADL3 SPUR TABLES All spur tables are (N frf) (M flo) and were measured using the standard evaluation board. Mixer spurious products are measured in dbc from the IF output power level. Data was only measured for frequencies less than GHz. Typical noise floor of the measurement system = dbm. V Performance VS = V, I S = 19 ma, TA = C, frf = 19 MHz, flo = 197 MHz, LO power = dbm, VGS = VGS1 = V, and ZO = Ω, unless otherwise noted. Table. N < 3 < < < < < < < < 97.9 < < < < < < < < < < < < < < < < < < 7 < < < < < < < < < < < < < < 9 < < < < < < < < < < < < < < 11 < < < < < < < < < < < 13 < < < 1 < < 1 < M 3.3 V Performance VS = 3.3 V, IS = ma, TA = C, frf = 19 MHz, flo = 197 MHz, LO power = dbm, R9 = Ω, R1 = Ω, VGS = VGS1 = V, and ZO = Ω, unless otherwise noted. Table. N M < 3 < < 9.. < < < < < < 97. < < < < < < < < < < < < < < < < < < 7 < < < < < < < < < < < < < < 9 < < < < < < < < < < < < < < 11 < < < < < < < < < < < 13 < < < 1 < < 1 < Rev. A Page of 3

6 ADL3 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Rating Supply Voltage, VS. V RF Input Level dbm LO Input Level 13 dbm IFOP, IFON Bias Voltage. V VGS, VGS1, LOSW, PWDN. V Internal Power Dissipation 1. W θja C/W Maximum Junction Temperature 1 C Operating Temperature Range C to + C Storage Temperature Range C to +1 C Lead Temperature Range (Soldering, sec) C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. A Page of 3

7 VLO3 LGM3 VLO LOSW 9 NC 7 IFGM 19 IFOP 1 IFON 17 PWDN 1 LEXT ADL3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VPIF RFIN RFCT COMM COMM 1 3 ADL3 TOP VIEW (Not to Scale) 1 LOI 1 VPSW 13 VGS1 VGS 11 LOI1 NOTES 1. NC = NO CONNECT.. EXPOSED PAD. MUST BE SOLDERED TO GROUND. Figure. Pin Configuration - Table. Pin Function Descriptions Pin No. Mnemonic Description 1 VPIF Positive Supply Voltage for IF Amplifier. RFIN RF Input. Must be ac-coupled. 3 RFCT RF Balun Center Tap (AC Ground)., COMM Device Common (DC Ground)., VLO3, VLO Positive Supply Voltages for LO Amplifier. 7 LGM3 LO Amplifier Bias Control. 9 LOSW LO Switch. LOI1 selected for V, and LOI selected for 3 V. NC No Connect. 11, 1 LOI1, LOI LO Inputs. Must be ac-coupled., 13 VGS, VGS1 Mixer Gate Bias Controls. 3 V logic. Ground these pins for nominal setting. 1 VPSW Positive Supply Voltage for LO Switch. 1 LEXT IF Return. This pin must be grounded. 17 PWDN Power Down. Connect this pin to ground for normal operation and connect this pin to 3. V for disable mode. 1, 19 IFON, IFOP Differential IF Outputs (Open Collectors). Each requires an external dc bias. IFGM IF Amplifier Bias Control. EPAD (EP) Exposed pad. Must be soldered to ground. Rev. A Page 7 of 3

8 ADL3 TYPICAL PERFORMANCE CHARACTERISTICS V PERFORMANCE VS = V, IS = 19 ma, TA = C, frf = 19 MHz, flo = 17 MHz, LO power = dbm, R1 = 9 Ω, VGS = VGS1 = V, and ZO = Ω, unless otherwise noted. 7 T A = C SUPPLY CURRENT (ma) T A = C INPUT IP (dbm) Figure 3. Supply Current vs. RF Frequency Figure. Input IP vs. RF Frequency CONVERSION GAIN (db) 1 T A = C Figure. Power Conversion Gain vs. RF Frequency -11 INPUT P1dB (dbm) 11 9 T A = C Figure 7. Input P1dB vs. RF Frequency -3 3 T A = C INPUT IP3 (dbm) 1 SSB NOISE FIGURE (db) 1 T A = C Figure. Input IP3 vs. RF Frequency Figure. SSB Noise Figure vs. RF Frequency -33 Rev. A Page of 3

9 ADL3 V POS =.V V POS =.V V POS =.V SUPPLY CURRENT (ma) 1 V POS =.7V INPUT IP (dbm) 3 3 V POS =.7V V POS =.V 1 TEMPERATURE ( C) - TEMPERATURE ( C) -1 Figure 9. Supply Current vs. Temperature Figure. Input IP vs. Temperature CONVERSION GAIN (db) V POS =.7V V POS =.V V POS =.V INPUT P1dB (dbm) V POS =.V V POS =.7V V POS =.V TEMPERATURE ( C) Figure. Power Conversion Gain vs. Temperature - TEMPERATURE ( C) Figure 13. Input P1dB vs. Temperature - 3 V POS =.V 3 11 INPUT IP3 (dbm) 1 V POS =.7V V POS =.V SSB NOISE FIGURE (db) 9 V POS =.V V POS =.V V POS =.7V 7 TEMPERATURE ( C) Figure 11. Input IP3 vs. Temperature - TEMPERATURE ( C) Figure 1. SSB Noise Figure vs. Temperature -3 Rev. A Page 9 of 3

10 ADL3 3 7 T A = C SUPPLY CURRENT (ma) T A = C INPUT IP (dbm) IF FREQUENCY (MHz) IF FREQUENCY (MHz) -13 Figure 1. Supply Current vs. IF Frequency Figure 1. Input IP vs. IF Frequency CONVERSION GAIN (db) T A = C INPUT P1dB (dbm) T A = C IF FREQUENCY (MHz) Figure 1. Power Conversion Gain vs. IF Frequency IF FREQUENCY (MHz) Figure 19. Input P1dB vs. IF Frequency -1 3 T A = C INPUT IP3 (dbm) 1 SSB NOISE FIGURE (db) IF FREQUENCY (MHz) Figure 17. Input IP3 vs. IF Frequency IF FREQUENCY (MHz) Figure. SSB Noise Figure vs. IF Frequency -3 Rev. A Page of 3

11 ADL3 CONVERSION GAIN (db) T A = C INPUT P1dB (dbm) 1 T A = C 1 LO POWER (dbm) Figure 1. Power Conversion Gain vs. LO Power - LO POWER (dbm) Figure. Input P1dB vs. LO Power - 3 INPUT IP3 (dbm) 3 1 T A = C IF/ SPURIOUS (dbc) T A = C LO POWER (dbm) Figure. Input IP3 vs. LO Power Figure. IF/ Spurious vs. RF Frequency - INPUT IP (dbm) T A = C IF/3 SPURIOUS (dbc) 7 T A = C LO POWER (dbm) Figure 3. Input IP vs. LO Power Figure. IF/3 Spurious vs. RF Frequency -7 Rev. A Page 11 of 3

12 ADL3 9 DISTRIBUTION PERCENTAGE (%) 7 3 RESISTANCE (Ω) 3 CAPACITANCE (pf) CONVERSION GAIN (db) IF FREQUENCY (MHz) -3 Figure 7. Conversion Gain Distribution Figure 3. IF Port Return Loss DISTRIBUTION PERCENTAGE (%) RF RETURN LOSS (db) INPUT IP3 (dbm) Figure. Input IP3 Distribution Figure 31. RF Port Return Loss, Fixed IF -3 9 DISTRIBUTION PERCENTAGE (%) 7 3 LO RETURN LOSS (db) 1 SELECTED UNSELECTED INPUT P1dB (dbm) Figure 9. Input P1dB Distribution LO FREQUENCY (GHz) Figure 3. LO Return Loss, Selected and Unselected -37 Rev. A Page of 3

13 ADL3 7 LO SWITCH ISOLATION (db) T A = C LO FREQUENCY (GHz) Figure 33. LO Switch Isolation vs. LO Frequency -1 LO-TO-RF LEAKAGE (dbm) T A = C LO FREQUENCY (GHz) Figure 3. LO-to-RF Leakage vs. LO Frequency -3 RF-TO-IF ISOLATION (dbc) 3 T A = C LO LEAKAGE (dbm) 1 3 LO TO IF LO TO RF Figure 3. RF-to-IF Isolation vs. RF Frequency LO FREQUENCY (GHz) Figure 37. LO Leakage vs. LO Frequency - LO-TO-IF LEAKAGE (dbm) 1 T A = C 3LO LEAKAGE (dbm) 3 3LO TO RF 3LO TO IF LO FREQUENCY (GHz) Figure 3. LO-to-IF Leakage vs. LO Frequency LO FREQUENCY (GHz) Figure 3. 3LO Leakage vs. LO Frequency - Rev. A Page 13 of 3

14 ADL CONVERSION GAIN (db) 7 3 CONVERSION GAIN SSB NOISE FIGURE VGS = 7 VGS = 1 1 VGS = VGS = SSB NOISE FIGURE (db) -39 SUPPLY CURRENT (ma) R1 IF SET RESISTOR BIAS RESISTOR VALUE (Ω) - Figure 39. Power Conversion Gain and SSB Noise Figure vs. RF Frequency Figure. IF Supply Current vs. IF Bias Resistor Value INPUT P1dB (dbm) INPUT IP3 INPUT P1dB VGS = VGS = 1 1 VGS = VGS = Figure. Input IP3 and Input P1dB vs. RF Frequency 3 INPUT IP3 (dbm) -3 CONVERSION GAIN AND SSB NOISE FIGURE (db) IF BIAS RESISTOR VALUE (kω) INPUT IP3 SSB NOISE FIGURE CONVERSION GAIN Figure 3. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs. IF Bias Resistor Value 3 1 INPUT IP3 (dbm) - 3 SSB NOISE FIGURE (db) BLOCKER POWER (dbm) Figure 1. SSB Noise Figure vs. MHz Offset Blocker Level -31 Rev. A Page 1 of 3

15 ADL3 3.3 V PERFORMANCE VS = 3.3 V, IS = ma, TA = C, frf = 19 MHz, flo = 17 MHz, LO power = dbm, R9 = Ω, R1 = Ω, VGS = VGS1 = V, and ZO = Ω, unless otherwise noted T A = C SUPPLY CURRENT (ma) T A = C INPUT IP (dbm) Figure. Supply Current vs. RF Frequency at 3.3 V Figure 7. Input IP vs. RF Frequency at 3.3 V - 1 T A = C CONVERSION GAIN (db) INPUT P1dB (dbm) T A = C Figure. Power Conversion Gain vs. RF Frequency at 3.3 V Figure. Input P1dB vs. RF Frequency at 3.3 V T A = C INPUT IP3 (dbm) 1 SSB NOISE FIGURE (db) T A = C Figure. Input IP3 vs. RF Frequency at 3.3 V Figure 9. SSB Noise Figure vs. RF Frequency at 3.3 V - Rev. A Page 1 of 3

16 ADL3 CIRCUIT DESCRIPTION The ADL3 consists of two primary components: the radio frequency (RF) subsystem and the local oscillator (LO) subsystem. The combination of design, process, and packaging technology allows the functions of these subsystems to be integrated into a single die, using mature packaging and interconnection technologies to provide a high performance, low cost design with excellent electrical, mechanical, and thermal properties. In addition, the need for external components is minimized, optimizing cost and size. The RF subsystem consists of an integrated, low loss RF balun, passive MOSFET mixer, sum termination network, and IF amplifier. The LO subsystem consists of an SPDT-terminated FET switch and a three-stage limiting LO amplifier. The purpose of the LO subsystem is to provide a large, fixed amplitude, balanced signal to drive the mixer independent of the level of the LO input. A block diagram of the device is shown in Figure. VPIF RFIN RFCT COMM COMM 1 3 NC = NO CONNECT IFGM IFOP IFON PWDN LEXT BIAS GENERATOR ADL3 7 9 VLO3 LGM3 VLO LOSW NC Figure. Simplified Schematic 1 LOI 1 VPSW 13 VGS1 VGS 11 LOI1-1 RF SUBSYSTEM The single-ended, Ω RF input is internally transformed to a balanced signal using a low loss (<1 db) unbalanced-to-balanced (balun) transformer. This transformer is made possible by an extremely low loss metal stack, which provides both excellent balance and dc isolation for the RF port. Although the port can be dc connected, it is recommended that a blocking capacitor be used to avoid running excessive dc current through the part. The RF balun can easily support an RF input frequency range of MHz to MHz. The resulting balanced RF signal is applied to a passive mixer that commutates the RF input with the output of the LO subsystem. The passive mixer is essentially a balanced, low loss switch that adds minimum noise to the frequency translation. The only noise contribution from the mixer is due to the resistive loss of the switches, which is in the order of a few ohms. As the mixer is inherently broadband and bidirectional, it is necessary to properly terminate all the idler (M N product) frequencies generated by the mixing process. Terminating the mixer avoids the generation of unwanted intermodulation products and reduces the level of unwanted signals at the input of the IF amplifier, where high peak signal levels can compromise the compression and intermodulation performance of the system. This termination is accomplished by the addition of a sum network between the IF amplifier and the mixer and also in the feedback elements in the IF amplifier. The IF amplifier is a balanced feedback design that simultaneously provides the desired gain, noise figure, and input impedance that is required to achieve the overall performance. The balanced opencollector output of the IF amplifier, with impedance modified by the feedback within the amplifier, permits the output to be connected directly to a high impedance filter, differential amplifier, or an analog-to-digital input while providing optimum secondorder intermodulation suppression. The differential output impedance of the IF amplifier is approximately Ω. If operation in a Ω system is desired, the output can be transformed to Ω by using a :1 transformer. The intermodulation performance of the design is generally limited by the IF amplifier. The IP3 performance can be optimized by adjusting the IF current with an external resistor. Figure and Figure 3 illustrate how various IF and LO bias resistors affect the performance with a V supply. Additionally, dc current can be saved by increasing either or both resistors. It is permissible to reduce the dc supply voltage to as low as 3.3 V, further reducing the dissipated power of the part. (Note that no performance enhancement is obtained by reducing the value of these resistors and excessive dc power dissipation may result.) Rev. A Page 1 of 3

17 LO SUBSYSTEM The LO amplifier is designed to provide a large signal level to the mixer to obtain optimum intermodulation performance. The resulting amplifier provides extremely high performance centered on an operating frequency of 17 MHz. The best operation is achieved with either low-side LO injection for RF signals in the 17 MHz to MHz range or high-side injection for RF signals in the MHz to 17 MHz range. Operation outside these ranges is permissible, and conversion gain is extremely wideband, easily spanning MHz to MHz, but intermodulation is optimal over the aforementioned ranges. The ADL3 has two LO inputs permitting multiple synthesizers to be rapidly switched with extremely short switching times (< ns) for frequency agile applications. The two inputs are applied to a high isolation SPDT switch that provides a constant input impedance, regardless of whether the port is selected, to avoid pulling the LO sources. This multiple section switch also ensures high isolation to the off input, minimizing any leakage from the unwanted LO input that may result in undesired IF responses. The single-ended LO input is converted to a fixed amplitude differential signal using a multistage, limiting LO amplifier. This results in consistent performance over a range of LO input power. Optimum performance is achieved from dbm to + dbm, but the circuit continues to function at considerably lower levels of LO input power. ADL3 The performance of this amplifier is critical in achieving a high intercept passive mixer without degrading the noise floor of the system. This is a critical requirement in an interferer rich environment, such as cellular infrastructure, where blocking interferers can limit mixer performance. The bandwidth of the intermodulation performance is somewhat influenced by the current in the LO amplifier chain. For dc current sensitive applications, it is permissible to reduce the current in the LO amplifier by raising the value of the external bias control resistor. For dc current critical applications, the LO chain can operate with a supply voltage as low as 3.3 V, resulting in substantial dc power savings. In addition, when operating with supply voltages below 3. V, the ADL3 has a power-down mode that permits the dc current to drop to < µa. All of the logic inputs are designed to work with any logic family that provides a Logic input level of less than. V and a Logic 1 input level that exceeds 1. V. All logic inputs are high impedance up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection circuitry permits operation up to. V, although a small bias current is drawn. All pins, including the RF pins, are ESD protected and have been tested up to a level of 1 V HBM and V CDM. Rev. A Page 17 of 3

18 ADL3 APPLICATIONS INFORMATION BASIC CONNECTIONS The ADL3 mixer is designed to downconvert radio frequencies (RF) primarily between MHz and MHz to lower intermediate frequencies (IF) between 3 MHz and MHz. Figure 1 depicts the basic connections of the mixer. It is recommended to ac-couple RF and LO input ports to prevent non-zero dc voltages from damaging the RF balun or LO input circuit. The RFIN capacitor value of 3 pf is recommended to provide the optimized RF input return loss for the desired frequency band. IF PORT The mixer differential IF interface requires pull-up choke inductors to bias the open-collector outputs and to set the output match. The shunting impedance of the choke inductors used to couple dc current into the IF amplifier should be selected to provide the desired output return loss. The real part of the output impedance is approximately Ω, as seen in Figure 3, which matches many commonly used SAW filters without the need for a transformer. This results in a voltage conversion gain that is approximately db higher than the power conversion gain, as shown in Table 3. When a Ω output impedance is needed, use a :1 impedance transformer, as shown in Figure 1. BIAS RESISTOR SELECTION Two external resistors, RBIAS IF and RBIAS LO, are used to adjust the bias current of the integrated amplifiers at the IF and LO terminals. It is necessary to have a sufficient amount of current to bias both the internal IF and LO amplifiers to optimize dc current vs. optimum IIP3 performance. Figure and Figure 3 provide the reference for the bias resistor selection when lower power consumption is considered at the expense of conversion gain and IP3 performance. MIXER VGS CONTROL DAC The ADL3 features two logic control pins, VGS (Pin ) and VGS1 (Pin 13), that allow programmability for internal gate-tosource voltages for optimizing mixer performance over desired frequency bands. The evaluation board defaults both VGS and VGS1 to ground. Power conversion gain, IIP3, NF, and IP1dB can be optimized, as is shown in Figure 39 and Figure. Rev. A Page 1 of 3

19 ADL3 +V pf 1pF 7nH 7nH :1 IF OUT R BIAS IF kω +V µF pf ADL3 pf +V 1 1 LO IN 3pF RF IN 1 +V pf 3 13 pf.1µf BIAS GENERATOR pf 11 LO1 IN 7 9 +V R BIAS LO kω pf pf - Figure 1. Typical Application Circuit Rev. A Page 19 of 3

20 VLO3 LGM3 VLO LOSW NC IFGM IFOP IFON PWDN LEXT ADL3 EVALUATION BOARD An evaluation board is available for the family of double balanced mixers. The standard evaluation board schematic is shown in Figure. The evaluation board is fabricated using Rogers RO33 material. Table 9 describes the various configuration options of the evaluation board. The evaluation board layout is shown in Figure 3 to Figure. VPOS C1 pf L 7nH T1 IF1-OUT C19 pf L 7nH C17 1pF R1 Ω R1 9Ω R Ω R Ω L3 Ω R1 kω PWR_UP C pf LO_IN VPOS RF-IN VPOS C1 3pF C µf C.1µF C1 pf C pf VPIF RFIN RFCT COMM ADL3 LOI VPSW VGS1 VGS VGS VGS1 C pf C 1nF R kω R3 1kΩ COMM LOI1 LO1_IN C nf VPOS C pf R9 1.7kΩ C pf VPOS Figure. Evaluation Board Schematic R kω LOSEL - Rev. A Page of 3

21 ADL3 Table 9. Evaluation Board Configuration Components Description Default Conditions C, C, C, C1, C19, C, C1 Power Supply Decoupling. Nominal supply decoupling consists of a µf capacitor to ground in parallel with a pf capacitor to ground positioned as close to the device as possible. C1, C, C RF Input Interface. The input channels are ac-coupled through C1. C and C provide bypassing for the center taps of the RF input baluns. T1, C17, L, L, R1, R, R IF Output Interface. The open-collector IF output interfaces are biased through pull-up choke inductors L and L. T1is a :1 impedance transformer used to provide a single-ended IF output interface, with C17 providing center-tap bypassing. Remove R1 for balanced output operation. C, C, R LO Interface. C and C provide ac coupling for the LO1_IN and LO_IN local oscillator inputs. LOSEL selects the appropriate LO input for both mixer cores. R provides a pull-down to ensure that LO1_IN is enabled when the LOSEL test point is logic low. LO_IN is enabled when LOSEL is pulled to logic high. R1 PWDN Interface. R1 pulls the PWDN logic low and enables the device. The PWR_UP test point allows the PWDN interface to be exercised using the external logic generator. Grounding the PWDN pin for nominal operation is allowed. Using the PWDN pin when supply voltages exceed 3.3 V is not allowed. C, L3, R9, R1, R, R3, VGS, VGS1 Bias Control. R and R3 form a voltage divider to provide 3 V for logic control, bypassed to ground through C. VGS and VGS1 jumpers provide programmability at the VGS and VGS1 pins. It is recommended to pull these two pins to ground for nominal operation. R9 sets the bias point for the internal LO buffers. R1 sets the bias point for the internal IF amplifier. C = µf (size 3), C, C, C, C1 = pf (size ), C1, C19 = pf (size ) C1 = 3 pf (size ), C = pf (size ), C =.1 µf (size ) T1 = TC-1W+ (Mini-Circuits), C17 = 1 pf (size ), L, L = 7 nh (size ), R1, R, R = Ω (size ) C, C = pf (size ), R = kω (size ) R1 = kω (size ) C = 1 nf (size ), L3 = Ω (size 3), R9 = 1.7 kω (size ), R1 = 9 Ω (size ), R = kω (size ), R3 = 1 kω (size ), VGS = VGS1 = 3-pin shunt Rev. A Page 1 of 3

22 ADL3 Figure 3. Evaluation Board Top Layer - Figure. Evaluation Board Power Plane, Internal Layer -7 Figure. Evaluation Board Ground Plane, Internal Layer 1 - Figure. Evaluation Board Bottom Layer - Rev. A Page of 3

23 ADL3 OUTLINE DIMENSIONS PIN 1 INDICATOR..7.7 SEATING PLANE.. SQ.9 TOP VIEW. BSC MAX. NOM COPLANARITY.. REF EXPOSED PAD BOTTOM VIEW COMPLIANT TO JEDEC STANDARDS MO--WHHC. 1 PIN 1 INDICATOR SQ.9. MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Figure 7. -Lead Lead Frame Chip Scale Package [LFCSP_WQ] mm mm Body, Very Very Thin Quad (CP--9) Dimensions shown in millimeters 1119-A ORDERING GUIDE Model 1 Temperature Range Package Description Package Option Ordering Quantity ADL3ACPZ-R7 C to + C -Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP--9 1, 7 Tape and Reel ADL3-EVALZ Evaluation Board 1 1 Z = RoHS Compliant Part. 9 1 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D--/1(A) Rev. A Page 3 of 3