24 GHz to 44 GHz, Wideband, Microwave Upconverter ADMV1013. Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS GENERAL DESCRIPTION

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1 GHz to GHz, Wideband, Microwave Upconverter FEATURES FUNCTIONAL BLOCK DIAGRAM Wideband RF input frequency range: GHz to GHz upconversion modes Direct conversion from baseband I/Q to RF Single-sideband upconversion from real IF LO input frequency range:. GHz to. GHz LO quadrupler for up to GHz Matched Ω single-ended RF output and IF inputs Option between matched Ω balanced or Ω singleended LO inputs Ω balanced baseband inputs Sideband suppression and carrier feedthrough optimization Variable attenuator for transceiver power control Programmable via -wire SPI interface -terminal land grid array package (LGA) RST DVDD SCLK SDI SDO BG_RBIAS VCC_DRV GND SEN GND LOP LON GND VCC_QUAD BG_RBIAS VCC_BG VCC_MIXER 9 NIC IF_I I_N I_P GND Q_N Q_P IF_Q VCC_BG APPLICATIONS RF VVA VVA VENV_P Point to point microwave radios Radar, electronic warfare systems Instrumentation, automatic test equipment (ATE) GND VCC_DRV NIC NIC VCC_VVA VCTRL VCTRL DET VCC_AMP SEN VCC_ENV VCC_AMP VENV_N 77- Figure. GENERAL DESCRIPTION The is a wideband, microwave upconverter optimized for point to point microwave radio designs operating in the GHz to GHz radio frequency (RF) range. The upconverter offers two modes of frequency translation. The device is capable of direct conversion to RF from baseband in-phase quadrature (I/Q) input signals, as well as single-sideband (SSB) upconversion from complex intermediate frequency (IF) inputs. The baseband I/Q input path can be disabled and modulated complex IF signals, anywhere from. GHz to. GHz, can be inserted in the IF path and upconverted to GHz to GHz while suppressing the unwanted sideband by typically better than dbc. The serial port interface (SPI) allows adjustment of the quadrature phase and mixer gate voltage to allow optimum sideband suppression and local oscillator (LO) nulling. In addition, the SPI interface allows powering down the output envelope detector to reduce power consumption. The upconverter comes in a -terminal land grid array package (LGA) package. The operates over the C to + C case temperature range. Rev. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... Revision History... Specifications... 3 Serial Port Register Timing... Absolute Maximum Ratings... Thermal Resistance... ESD Caution... Pin Configuration and Function Descriptions... 7 Typical Performance Characteristics... 9 I/Q Mode... 9 IF Mode... Envelope Detector Performance... 9 Return Loss... M N Spurious Performance... Theory of Operation... Start-Up Sequence... Baseband Quadrature Modulation (I/Q Mode)... Single-Sideband Upconversion (IF Mode)... LO Input Path... Sideband Suppression Optimization... Carrier Feedthrough Nulling... Envelope Detector... Power Down and Reset... Serial Port Interface (SPI)... Applications Information... Baseband Quadrature Modulation from Low Frequencies.. Performance at Different Quad Filter Settings... VVA Temperature Compensation... Performance Between Differential vs. Single-Ended LO Input... 9 Performance Across RF Frequency at Fixed Input Frequencies... Performance Across Common-Mode Voltage in I/Q Mode 3 Operating VCTRL and VCTRL Independently... 3 Recommended Land Pattern Evaluation Board Information Register Summary... 3 Register Details... 3 Outline Dimensions Ordering Guide REVISION HISTORY / Revision : Initial Version Rev. Page of 39

3 SPECIFICATIONS IF and I/Q amplitude = dbm, VCC_DRV = VCC_DRV = VCC_AMP = VCC_ENV = VCC_AMP = VCC_BG = VCC_MIXER = VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA =. V, TA = C, and set Register xa to xe7, unless otherwise noted. Measurements in IF mode performed with a 9 hybrid, Register x3, Bit 7 =, IF input frequency (fif) = 3. GHz. Measurements in I/Q mode are measured as a composite of the I and Q channel performance, common-mode voltage (VCM) = V, Register x3, Bit 7 =, and Register x, Bits[:] = x, unless otherwise noted. I/Q baseband frequency (fbb) = MHz. VCTRL = VCTRL. VCTRL is the attenuation voltage at the VCTRL and VCTRL pins. VCTRL = mv, unless otherwise specified. Table. Parameter Test Conditions/Comments Min Typ Max Unit FREQUENCY RANGES RF Input GHz LO Input.. GHz LO Quadrupler. GHz IF Output.. GHz Baseband (BB) I/Q Output DC. GHz LO AMPLITUDE RANGE + dbm I/Q MODULATOR PERFORMANCE Conversion Gain At maximum gain GHz to GHz fbb 3. GHz 3 db GHz > fbb > 3. GHz GHz to GHz 9 db Voltage Variable Attenuator (VVA) Control Range 3 db Single-Sideband (SSB) Noise Figure At maximum gain GHz to GHz db GHz to GHz 9 db Output Third-Order Intercept (IP3) At maximum gain GHz to GHz 3 dbm GHz to GHz dbm Output db Compression Point (PdB) At maximum gain GHz to GHz 3 dbm GHz to GHz dbm Sideband Rejection (SBR) GHz to GHz, at maximum gain Uncalibrated 3 dbc IF SINGLE-SIDEBAND UPCONVERSION PERFORMANCE Conversion Gain At maximum gain GHz to GHz fif 3. GHz 3 db GHz > fif > 3. GHz GHz to GHz db VVA Control Range 3 db SSB Noise Figure At maximum gain GHz to GHz db GHz to GHz db Output IP3 At maximum gain GHz to GHz 3 dbm GHz to GHz dbm Output PdB At maximum gain GHz to GHz 3 dbm GHz to GHz dbm SBR GHz to GHz, at maximum gain Uncalibrated dbc Calibrated Calibrated using LOAMP_PH_ADJ_ Q_FINE and LOAMP_PH_ADJ_I_FINE bits 3 dbc Rev. Page 3 of 39

4 Parameter Test Conditions/Comments Min Typ Max Unit ENVELOPE DETECTOR PERFORMANCE Output Level For optimum performance Minimum dbm Maximum dbm Envelope Bandwidth Measured with two tones with total power output (POUT) at RF = dbm 3 db RF frequency (frf) = GHz MHz db frf = GHz GHz RETURN LOSS RF Output Ω single-ended db LO Input Ω differential db IF Input Ω single-ended db BB Input Ω differential db BB I/Q Input Impedance Ω LEAKAGE At maximum gain Fundamental LO to RF dbm LO to RF. GHz to. GHz LO Uncalibrated dbm. GHz to. GHz LO Uncalibrated dbm. GHz to. GHz LO Calibrated using MXER_OFF_ADJ_I_N, dbm MXER_OFF_ADJ_I_P, MXER_OFF_ ADJ_Q_N, MXER_OFF_ADJ_Q_P bits at VCTRL = mv, IF mode LO to RF dbm Fundamental LO to IF 7 dbm Fundamental LO to I/Q 7 dbm LOGIC INPUTS Input Voltage Range High, VINH DVDD.. V Low, VINL. V Input Current, IINH/IINL μa Input Capacitance, CIN 3 pf LOGIC OUTPUTS Output Voltage Range High, VOH DVDD.. V Low, VOL. V Output High Current, IOH μa POWER INTERFACE VCC_DRV, VCC_DRV, VCC_AMP, VCC_ENV, V VCC_AMP, VCC_BG, VCC_MIXER, VCC_BG, VCC_QUAD 3.3 V Supply Current VCTRL =. V, no IF and I/Q or LO input ma signal DVDD, VCC_VVA.7..9 V. V Supply Current VCTRL =. V, no IF and I/Q or LO input 3 ma signal Total Power Consumption.9 W Power-Down 77 3 mw Rev. Page of 39

5 SERIAL PORT REGISTER TIMING Table. Parameter Description Min Typ Max Unit tsdi, SETUP Data to clock setup time ns tsdi, HOLD Data to clock hold time ns tsclk, HIGH Clock high duration to % tsclk, LOW Clock low duration to % tsclk, SEN/SEN_SETUP Clock to SEN/SEN setup time ns tsclk, DOT Clock to data out transition time ns tsclk, DOV Clock to data out valid time ns tsclk, SEN/SEN_INACTIVE Clock to SEN/SEN inactive ns t SEN/SEN_INACTIVE Inactive SEN/SEN (between two operations) ns Timing Diagram SCLK t SCLK, LOW t SCLK, HIGH t SCLK, SEN/SEN_SETU P t SEN/SEN_INACTIVE SEN/SEN t SCLK, DOT t SCLK, DOV t SCLK, SEN/SEN_INACTIVE SDO SDI t SDI, SETUP t SDI, HOLD 77- Figure. Serial Port Register Timing Diagram Rev. Page of 39

6 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Supply Voltage VCC_DRV, VCC_DRV, VCC_AMP,.3 V VCC_ENV, VCC_AMP, VCC_BG, VCC_BG, VCC_MIXER DVDD, VCC_VVA.3 V IF Input Power dbm I/Q Input Power dbm LO Input Power 9 dbm Maximum Junction Temperature C Maximum Power Dissipation.9 W Lifetime at Maximum Junction Temperature (TJ) hours Operating Case Temperature Range C to + C Storage Temperature Range C to + C Lead Temperature (Soldering sec) C Moisture Sensitivity Level (MSL) Rating MSL3 Electrostatic Discharge (ESD) Sensitivity Human Body Model (HBM) V Field Induced Charged Device Model 7 V (FICDM) THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. θja is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. θjc is the junction to case thermal resistance. Table. Thermal Resistance Package Type θja θjc_top 3 θjb ΨJT ΨJB Unit CC C/W The thermal resistance values specified in Table are simulated based on JEDEC specifications, unless specified otherwise, and must be used in compliance with JESD-. θja is the junction to ambient thermal resistance in a natural convection, JEDEC environment. 3 θjc_top is the junction to case (top) JEDEC thermal resistance. θjb is the junction to board JEDEC thermal resistance. ΨJT is the junction to top JEDEC thermal characterization parameter. ΨJB is the junction to board JEDEC thermal characterization parameter. ESD CAUTION The maximum power dissipation is a theoretical number calculated by (TJ C)/θJC_TOP. Based on IPC/JEDEC J-STD- MSL classifications. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. Page of 39

7 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TOP VIEW (Not to Scale) SEN GND LOP LON GND VCC_QUAD BG_RBIAS VCC_BG VCC_MIXER NIC RST DVDD SCLK 3 SDI SDO BG_RBIAS VCC_DRV 7 GND RF 9 GND IF_I 9 I_N I_P 7 GND Q_N Q_P IF_Q 3 VCC_BG VENV_P VENV_N VCC_DRV NIC NIC VCC_VVA VCTRL VCTRL VCC_AMP SEN VCC_ENV VCC_AMP NOTES. NIC = NOT INTERNALLY CONNECTED. THIS PIN IS NOT CONNECTED INTERNALLY.. EXPOSED PAD. SOLDER THE EXPOSED PAD TO A LOW IMPEDANCE GROUND PLANE. Figure 3. Pin Configuration 77- Table. Pin Function Descriptions Pin No. Mnemonic Description RST SPI Reset. Connect this pin to logic high for normal operation. The SPI logic is. V. DVDD. V SPI Digital Supply. 3 SCLK SPI Clock Digital Input. SDI SPI Serial Data Input. SDO SPI Serial Data Output. BG_RBIAS Voltage Gain Amplifier (VGA) Chip Band Gap Circuit, External High Precision Resistor. Place a. kω, high precision resistor shunt to ground close to this pin. 7 VCC_DRV 3.3 V Power Supply for RF Driver. Place a pf, a. μf, and a μf capacitor close to this pin.,, 7, 3, 39 GND Ground. 9 RF RF Output. This pin is dc-coupled internally to GND and matched to Ω single ended. VCC_DRV 3.3 V Power Supply for RF Predriver. Place a pf, a. μf, and a μf capacitor close to this pin., 3, 3 NIC Not Internally Connected. This pin is not connected internally. VCC_VVA. V Power Supply for VVA Control Circuit. Place a pf,. μf, and a μf capacitor close to this pin. VCTRL RF Voltage Variable Attenuator (VVA) Control Voltage. Place a kω series resistor with this pin. VCTRL RF Voltage Variable Attenuator (VVA) Control Voltage. Place a kω series resistor with this pin. 7 VCC_AMP 3.3 V Power Supply for RF Amplifier (AMP). Place a pf, a. μf, and a μf capacitor close to this pin. SEN SPI Serial Enable for VGA Chip. Connect this pin with Pin (SEN). 9 VCC_ENV 3.3 V Power Supply for Envelope Detector. Place a pf, a. μf, and a μf capacitor close to this pin. VCC_AMP 3.3 V Power Supply for RF Amplifier (AMP). Place a pf, a. μf, and a μf capacitor close to this pin. VENV_N Negative Differential Envelope Detector Output. VENV_P Positive Differential Envelope Detector Output. 3 VCC_BG 3.3 V Power Supply for VGA Chip Band Gap Circuit. Place a pf, a. μf, and a μf capacitor close to this pin., IF_Q, IF_I IF Single-Ended Complex Inputs. These pins are internally ac-coupled. When in IF mode, Pin (Q_P), Pin (Q_N), Pin (I_P), and Pin 9 (I_N) must be kept floating., Q_P, Q_N Differential Baseband Q Inputs. These pins are dc-coupled. Do not connect these pins in IF mode., 9 I_P, I_N Differential Baseband I Inputs. These pins are dc-coupled. Do not connect these pins in IF mode. Rev. Page 7 of 39

8 Pin No. Mnemonic Description 3 VCC_MIXER 3.3 V Power Supply for Mixer. Place a pf, a. μf, and a μf capacitor close to this pin. 33 VCC_BG 3.3 V Power Supply for Mixer Chip Band Gap Circuit. Place a pf, a. μf, and a μf capacitor close to this pin. 3 BG_RBIAS Mixer Chip Band Gap Circuit, External High Precision Resistor. Place a. kω, high precision resistor shunt to ground close to this pin. 3 VCC_QUAD 3.3 V Power Supply for Quadruppler. Place a pf, a. μf, and a μf capacitor close to this pin. 37, 3 LON, LOP Negative and Positive Differential Local Oscillator Input. This pin is dc-coupled internally to ground and matched to Ω differential or Ω single ended. SEN SPI Serial Enable for Mixer Chip. Connect this pin with Pin (SEN). EPAD Exposed Pad. Solder the exposed pad to a low impedance ground plane. Rev. Page of 39

9 TYPICAL PERFORMANCE CHARACTERISTICS I/Q MODE I/Q amplitude = dbm, VCC_DRV = VCC_DRV = VCC_AMP = VCC_ENV = VCC_AMP = VCC_BG = VCC_MIXER = VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA =. V, TA = C, and set Register xa to xe7, unless otherwise noted. VCTRL = VCTRL. VCTRL is the attenuation voltage at the VCTRL and VCTRL pins. VCTRL = mv, unless otherwise specified. Measurements in I/Q mode are measured as a composite of the I and Q channel performance, VCM = V, Register x3, Bit 7 =, and Register x, Bits[:] = x, unless otherwise noted. I/Q fbb = MHz. 3 + C AT.V UPPER SIDEBAND + C AT.V UPPER SIDEBAND C AT.V UPPER SIDEBAND + C AT.V UPPER SIDEBAND + C AT.V UPPER SIDEBAND C AT.V UPPER SIDEBAND + C AT V UPPER SIDEBAND + C AT V UPPER SIDEBAND 3 C AT V UPPER SIDEBAND Figure. Conversion Gain vs. RF Frequency (frf) at Three Different Gain Settings for Various Temperatures, fbb = MHz (Upper Sideband) 3.V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.V UPPER SIDEBAND Figure. Conversion Gain vs. RF Frequency at for Various Supply Voltages, fbb = MHz (Upper Sideband) +dbm UPPER SIDEBAND dbm UPPER SIDEBAND dbm UPPER SIDEBAND Figure. Conversion Gain vs. RF Frequency at for Various LO Inputs, fbb = MHz (Upper Sideband) Rev. Page 9 of V CTRL (V) + C AT 39GHz + C AT 39GHz C AT 9GHz + C AT GHz + C AT GHz C AT GHz Figure 7. Conversion Gain vs. VCTRL at Various Temperatures and frf = GHz and 39 GHz, fbb = MHz 39GHz UPPER SIDEBAND GHz UPPER SIDEBAND BASEBAND FREQUENCY (GHz) Figure. Conversion Gain vs. Baseband Frequency at frf = GHz and 39 GHz (Upper Sideband) 39GHz LOWER SIDEBAND GHz LOWER SIDEBAND BASEBAND FREQUENCY (GHz) Figure 9. Conversion Gain vs. Baseband Frequency at frf = GHz and 39 GHz (Lower Sideband)

10 OUTPUT IP3 (dbm) + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND Figure. Output IP3 vs. RF Frequency at Maximum Gain for Various Temperatures, RF Amplitude = dbm per Tone at MHz Spacing, fbb = MHz (Upper Sideband) OUTPUT IP3 (dbm) 3.V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.V UPPER SIDEBAND Figure. Output IP3 vs. RF Frequency at Maximum Gain for Supply Voltages, RF Amplitude = dbm per Tone at MHz Spacing, fbb = MHz (Upper Sideband) OUTPUT IP3 (dbm) V CTRL (V) 39GHz UPPER SIDEBAND GHz UPPER SIDEBAND Figure 3. Output IP3 vs. VCTRL, RF Amplitude = dbm per Tone at MHz Spacing, fbb = MHz at frf = GHz and 39 GHz (Upper Sideband) OUTPUT IP3 (dbm) 39GHz UPPER BASEBAND GHz UPPER BASEBAND 39GHz LOWER BASEBAND GHz LOWER BASEBAND BASEBAND FREQUENCY (GHz) Figure. Output IP3 vs. Baseband Frequency at frf = GHz and 39 GHz at Maximum Gain, RF Amplitude = dbm per Tone at MHz Spacing (Upper Sideband and Lower Sideband) OUTPUT IP3 (dbm) +dbm UPPER SIDEBAND dbm UPPER SIDEBAND dbm UPPER SIDEBAND Figure. Output IP3 vs. RF Frequency at Maximum Gain for Various LO Inputs, RF Amplitude = dbm per Tone at MHz Spacing, fbb = MHz (Upper Sideband) 77- OUTPUT IP3 (dbm) GHz UPPER SIDEBAND GHz UPPER SIDEBAND TOTAL INPUT POWER (dbm) Figure. Output IP3 vs. Total Input Power at MHz Spacing, fbb = MHz, frf = GHz and 39 GHz (Upper Sideband) 77- Rev. Page of 39

11 NOISE FIGURE (db) 3 + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND NOISE FIGURE (db) 3 + C AT 39GHz + C AT 39GHz C AT 39GHz + C AT GHz + C AT GHz C AT GHz Figure. Noise Figure vs. RF Frequency at Maximum Gain for Various Temperatures, fbb = MHz (Upper Sideband) V CTRL (V) Figure 9. Noise Figure vs. VCTRL for Various Temperatures at frf = GHz 39 GHz, fbb = MHz 77- NOISE FIGURE (db) 3 3.V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.V UPPER SIDEBAND NOISE FIGURE (db) 3 39GHz UPPER SIDEBAND GHz UPPER SIDEBAND Figure 7. Noise Figure vs. RF Frequency for Various Supply Voltages, fbb = MHz (Upper Sideband) BASEBAND FREQUENCY (GHz) Figure. Noise Figure vs. Baseband Frequency at frf = GHz and 39 GHz (Upper Sideband) 77-9 NOISE FIGURE (db) 3 +dbm UPPER SIDEBAND dbm UPPER SIDEBAND dbm UPPER SIDEBAND NOISE FIGURE (db) 3 39GHz LOWER SIDEBAND GHz LOWER SIDEBAND Figure. Noise Figure vs. RF Frequency for Various LO Inputs, fbb = MHz (Upper Sideband) BASEBAND FREQUENCY (GHz) Figure. Noise Figure vs. Baseband Frequency at frf = GHz and 39 GHz (Lower Sideband) 77- Rev. Page of 39

12 SIDEBAND REJECTION (dbc) 3 + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND SIDEBAND REJECTION (dbc) 3 + C AT 39GHz + C AT 39GHz C AT 39GHz + C AT GHz + C AT GHz C AT GHz V CTRL (V) 77- Figure. Sideband Rejection vs. RF Frequency at Maximum Gain for Various Temperatures, fbb = MHz (Upper Sideband) Figure. Sideband Rejection vs. VCTRL for Various Temperatures at frf = GHz and 39 GHz, fbb = MHz SIDEBAND REJECTION (dbc) 3 3.V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.V UPPER SIDEBAND SIDEBAND REJECTION (dbc) 3 39GHz UPPER SIDEBAND GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND GHz LOWER SIDEBAND Figure 3. Sideband Rejection vs. RF Frequency at for Various Supply Voltages, fbb = MHz (Upper Sideband) BASEBAND FREQUENCY (GHz) Figure. Sideband Rejection vs. Baseband Frequency at frf = GHz and 39 GHz (Upper Sideband and Lower Sideband) 77- SIDEBAND REJECTION (dbc) 3 +dbm UPPER SIDEBAND dbm UPPER SIDEBAND dbm UPPER SIDEBAND Figure. Sideband Rejection vs. RF Frequency for Various LO Inputs, fbb = MHz (Upper Sideband) 77- Rev. Page of 39

13 OUTPUT PdB (dbm) + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND OUTPUT PdB (dbm) + C AT 39GHz + C AT 39GHz C AT 39GHz + C AT GHz + C AT GHz C AT GHz Figure 7. Output PdB vs. RF Frequency at Maximum Gain for Various Temperatures, fbb = MHz (Upper Sideband) V CTRL (V) Figure. Output PdB vs. VCTRL for Various Temperatures at frf = GHz and 39 GHz, fbb = MHz 77- OUTPUT PdB (dbm) 3.V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.V UPPER SIDEBAND OUTPUT PdB (dbm) 39GHz UPPER SIDEBAND GHz UPPER SIDEBAND Figure. Output PdB vs. RF Frequency for Various Supply Voltages, fbb = MHz (Upper Sideband) BASEBAND FREQUENCY (GHz) Figure 3. Output PdB vs. Baseband Frequency at frf = GHz and 39 GHz (Upper Sideband) 77-3 OUTPUT PdB (dbm) OUTPUT PdB (dbm) 39GHz LOWER SIDEBAND GHz LOWER SIDEBAND +dbm UPPER SIDEBAND dbm UPPER SIDEBAND dbm UPPER SIDEBAND Figure 9. Output PdB vs. RF Frequency for Various LO Inputs, fbb = MHz (Upper Sideband) BASEBAND FREQUENCY (GHz) Figure 3. Output PdB vs. Baseband Frequency at frf = GHz and 39 GHz (Lower Sideband) 77-3 Rev. Page 3 of 39

14 IF MODE IF amplitude = dbm, VCC_DRV = VCC_DRV = VCC_AMP = VCC_ENV = VCC_AMP = VCC_BG = VCC_MIXER = VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA =. V, TA = C, and set Register xa to xe7, unless otherwise noted. VCTRL = VCTRL. VCTRL is the attenuation voltage at the VCTRL and VCTRL pins. VCTRL = mv, unless otherwise specified. Measurements in IF mode performed with a 9 hybrid, Register x3, Bit 7 =, and fif = 3. GHz. + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND + C LOWER SIDEBAND + C LOWER SIDEBAND C LOWER SIDEBAND Figure 33. Conversion Gain vs. RF Frequency at Maximum Gain for Various Temperatures, fif = 3. GHz (Upper Sideband and Lower Sideband) GHz UPPER SIDEBAND GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND GHz LOWER SIDEBAND IF FREQUENCY (GHz) Figure 3. Conversion Gain vs. IF Frequency at frf = GHz and 39 GHz at Maximum Gain (Upper Sideband and Lower Sideband) V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.V UPPER SIDEBAND 3.V LOWER SIDEBAND 3.3V LOWER SIDEBAND 3.V LOWER SIDEBAND C AT 39GHz + C AT 39GHz C AT 39GHz + C AT GHz + C AT GHz C AT GHz V CTRL (V) Figure 3. Conversion Gain vs. RF Frequency at Maximum Gain for Various Supply Voltages, fif = 3. GHz (Upper Sideband and Lower Sideband) +dbm UPPER SIDEBAND dbm UPPER SIDEBAND dbm UPPER SIDEBAND +dbm LOWER SIDEBAND dbm LOWER SIDEBAND dbm LOWER SIDEBAND Figure 3. Conversion Gain vs. RF Frequency at Maximum Gain for Various LO Inputs, fif = 3. GHz (Upper Sideband and Lower Sideband) Figure 37. Conversion Gain vs. VCTRL at Various Temperatures at frf = GHz and 39 GHz, fif = 3. GHz (Upper Sideband) + C AT 39GHz + C AT 39GHz C AT 39GHz + C AT GHz + C AT GHz C AT GHz V CTRL (V) Figure 3. Conversion Gain vs. VCTRL at Various Temperatures at frf = GHz and 39 GHz, fif = 3. GHz (Lower Sideband) 77- Rev. Page of 39

15 OUTPUT IP3 (dbm) + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND + C LOWER SIDEBAND + C LOWER SIDEBAND C LOWER SIDEBAND Figure 39. Output IP3 vs. RF Frequency at Maximum Gain for Various Temperatures, RF Amplitude = dbm per Tone at MHz Spacing, fif = 3. GHz (Upper Sideband and Lower Sideband) 77- OUTPUT IP3 (dbm) V CTRL (V) 39GHz UPPER SIDEBAND GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND GHz LOWER SIDEBAND Figure. Output IP3 vs. VCTRL at frf = GHz and 39 GHz, RF Amplitude = dbm per Tone at MHz Spacing, fif = 3. GHz (Upper Sideband and Lower Sideband) 77- OUTPUT IP3 (dbm) 3.V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.V UPPER SIDEBAND 3.V LOWER SIDEBAND 3.3V LOWER SIDEBAND 3.V LOWER SIDEBAND Figure. Output IP3 vs. RF Frequency at Maximum Gain for Various Supply Voltages, RF Amplitude = dbm per Tone at MHz Spacing, fif = 3. GHz (Upper Sideband and Lower Sideband) 77- OUTPUT IP3 (dbm) 39GHz UPPER SIDEBAND GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND GHz LOWER SIDEBAND IF FREQUENCY (GHz) Figure 3. Output IP3 vs. IF Frequency at frf = GHz and 39 GHz at Maximum Gain, RF Amplitude = dbm per Tone at MHz Spacing (Upper Sideband and Lower Sideband) 77-3 OUTPUT IP3 (dbm) +dbm UPPER SIDEBAND dbm UPPER SIDEBAND dbm UPPER SIDEBAND +dbm LOWER SIDEBAND dbm LOWER SIDEBAND dbm LOWER SIDEBAND OUTPUT IP3 (dbm) GHz UPPER SIDEBAND GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND GHz LOWER SIDEBAND TOTAL INPUT POWER (dbm) 77- Figure. Output IP3 vs. RF Frequency at Maximum Gain for Various LO Inputs, RF Amplitude = dbm per Tone at MHz Spacing, fif = 3. GHz (Upper Sideband and Lower Sideband) Figure. Output IP3 vs. Total Input Power at frf = GHz and 39 GHz at MHz Spacing, fif = 3. GHz (Upper Sideband and Lower Sideband) Rev. Page of 39

16 NOISE FIGURE (db) 3 + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND + C LOWER SIDEBAND + C LOWER SIDEBAND C LOWER SIDEBAND NOISE FIGURE (db) 3 39GHz UPPER SIDEBAND GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND GHz LOWER SIDEBAND Figure. Noise Figure vs. RF Frequency at Maximum Gain for Various Temperatures, fif = 3. GHz (Upper Sideband and Lower Sideband) IF FREQUENCY (GHz) Figure. Noise Figure vs. IF Frequency at frf = GHz and 39 GHz at Maximum Gain (Upper Sideband and Lower Sideband) 77- NOISE FIGURE (db) 3 3.V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.V UPPER SIDEBAND 3.V LOWER SIDEBAND 3.3V LOWER SIDEBAND 3.V LOWER SIDEBAND NOISE FIGURE (db) 3 + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND + C LOWER SIDEBAND + C LOWER SIDEBAND C LOWER SIDEBAND Figure. Noise Figure vs. RF Frequency at Maximum Gain for Various Supply Voltages, fif = 3. GHz (Upper Sideband and Lower Sideband) NOISE FIGURE (db) 3 +dbm UPPER SIDEBAND dbm UPPER SIDEBAND dbm UPPER SIDEBAND +dbm LOWER SIDEBAND dbm LOWER SIDEBAND dbm LOWER SIDEBAND Figure 7. Noise Figure vs. RF Frequency at Maximum Gain for Various LO Inputs, fif = 3. GHz (Upper Sideband and Lower Sideband) V CTRL (V) Figure 9. Noise Figure vs. VCTRL at Various Temperatures, fif = 3. GHz, (Upper Sideband and Lower Sideband) NOISE FIGURE (db) 3 + C AT 39GHz + C AT 39GHz C AT 39GHz + C AT GHz + C AT GHz C AT GHz V CTRL (V) Figure. Noise Figure vs. VCTRL at Temperatures at frf = GHz and 39 GHz, fif = 3. GHz (Lower Sideband) Rev. Page of 39

17 OUTPUT PdB (dbm) + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND + C LOWER SIDEBAND + C LOWER SIDEBAND C LOWER SIDEBAND OUTPUT PdB (dbm) 39GHz UPPER SIDEBAND GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND GHz LOWER SIDEBAND IF FREQUENCY (GHz) 77- Figure. Output PdB vs. RF Frequency at Maximum Gain for Various Temperatures, fif = 3. GHz (Upper Sideband and Lower Sideband) Figure. Output PdB vs. IF Frequency at frf = GHz and 39 GHz at Maximum Gain (Upper Sideband and Lower Sideband) OUTPUT PdB (dbm) 3.V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.V UPPER SIDEBAND 3.V LOWER SIDEBAND 3.3V LOWER SIDEBAND 3.V LOWER SIDEBAND OUTPUT PdB (dbm) + C AT 39GHz + C AT 39GHz C AT 39GHz + C AT GHz + C AT GHz C AT GHz V CTRL (V) 77-7 Figure. Output PdB vs. RF Frequency at Maximum Gain for Various Supply Voltages, fif = 3. GHz (Upper Sideband and Lower Sideband) Figure. Output PdB vs. VCTRL for Various Temperatures at frf = GHz and 39 GHz, fif = 3. GHz (Upper Sideband) OUTPUT PdB (dbm) +dbm UPPER SIDEBAND dbm UPPER SIDEBAND dbm UPPER SIDEBAND +dbm LOWER SIDEBAND dbm LOWER SIDEBAND dbm LOWER SIDEBAND OUTPUT PdB (dbm) + C AT 39GHz + C AT 39GHz C AT 39GHz + C AT GHz + C AT GHz C AT GHz V CTRL (V) 77- Figure 3. Output PdB vs. RF Frequency at Maximum Gain for Various LO Inputs, fif = 3. GHz (Upper Sideband and Lower Sideband) Figure. Output PdB vs. VCTRL for Various Temperatures at frf = GHz and 39 GHz, fif = 3. GHz (Lower Sideband) Rev. Page 7 of 39

18 SIDEBAND REJECTION (dbc) 3 + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND + C LOWER SIDEBAND + C LOWER SIDEBAND C LOWER SIDEBAND Figure 7. Sideband Rejection vs. RF Frequency at Maximum Gain for Various Temperatures, fif = 3. GHz, Uncalibrated (Upper Sideband and Lower Sideband) SIDEBAND REJECTION (dbc) 3 + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND Figure. Sideband Rejection vs. RF Frequency at Maximum Gain for Various Temperatures, fif = 3. GHz, Calibrated at C (Upper Sideband) SIDEBAND REJECTION (dbc) 3 +dbm UPPER SIDEBAND dbm UPPER SIDEBAND dbm UPPER SIDEBAND +dbm LOWER SIDEBAND dbm LOWER SIDEBAND dbm LOWER SIDEBAND Figure. Sideband Rejection vs. RF Frequency at Maximum Gain for Various LO Inputs, fif = 3. GHz (Upper Sideband and Lower Sideband) SIDEBAND REJECTION (dbc) IF FREQUENCY (GHz) 39GHz UPPER SIDEBAND GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND GHz LOWER SIDEBAND Figure. Sideband Rejection vs. IF Frequency at frf = GHz and 39 GHz at Maximum Gain (Upper Sideband and Lower Sideband) SIDEBAND REJECTION (dbc) 3.V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.V UPPER SIDEBAND 3.V LOWER SIDEBAND 3.3V LOWER SIDEBAND 3.V LOWER SIDEBAND SIDEBAND REJECTION (dbc) 39GHz UPPER SIDEBAND GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND GHz LOWER SIDEBAND Figure 9. Sideband Rejection vs. RF Frequency at Maximum Gain for Various Supply Voltages, fif = 3. GHz (Upper Sideband and Lower Sideband) V CTRL (V) Figure. Sideband Rejection vs. VCTRL at frf = GHz and 39 GHz, fif = 3. GHz (Upper Sideband and Lower Sideband) 77- Rev. Page of 39

19 ENVELOPE DETECTOR PERFORMANCE IF and I/Q amplitude = dbm, VCC_DRV = VCC_DRV = VCC_AMP = VCC_ENV = VCC_AMP = VCC_BG = VCC_MIXER = VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA =. V, TA = C, and set Register xa to xe7, unless otherwise noted. Measurements in IF mode performed with a 9 hybrid, Register x3, Bit 7 =, IF fif = 3. GHz. Measurements in I/Q mode are measured as a composite of the I and Q channel performance, VCM = V, Register x3, Bit 7 =, and Register x, Bits[:] = x, unless otherwise noted. I/Q fbb = MHz. VCTRL = VCTRL. VCTRL is the attenuation voltage at the VCTRL and VCTRL pins. VCTRL = mv, unless otherwise specified. Envelope detector measurements made with Register x3, Bit =. VENV_N/VENV_P DELTA (mv) 7 7 VENV_N/VENV_P DELTA, P OUT = 3dBm VENV_N/VENV_P DELTA, P OUT = dbm VENV_N/VENV_P DELTA, P OUT = dbm ENVELOPE P OUT, P OUT = 3dBm ENVELOPE P OUT, P OUT = dbm ENVELOPE P OUT, P OUT = dbm Figure 3. VENV_N/VENV_P Delta and Envelope POUT Delta vs. RF Frequency at Various Output Power Levels, Envelope Frequency = MHz, VCTRL = mv, TA = C, LO = dbm, IF = GHz (Upper Sideband) ENVELOPE P OUT DELTA (dbm) 77- P OUT (dbm) P OUT RF P OUT ENVELOPE AT HD P OUT ENVELOPE AT HD VENV_N/VENV_P DELTA 7 9 POWER IN TOTAL (dbm) Figure. POUT and VENV_N/VENV_P Delta vs. Power In Total for POUT RF, POUT Envelope HD, POUT Envelope HD, and VENV_N/VENV_P Delta, Measurements Performed with Two Tones with MHz Separation, frf = GHz, VCTRL = mv VENV_N/VENV_P DELTA (mv) 77-7 OUTPUT LEVEL (dbm) 3 7 NORMALIZED HD, NORMALIZED HD, ENVELOPE FREQUENCY (MHz) Figure. Output Level vs. Envelope Frequency for Normalized Harmonic Distortion (HD), and Normalized Harmonic Distortion(HD),, frf = GHz, LO = dbm at C, HD and HD Measurement Performed with Two Tones with Delta Equal to Envelope Frequency, HD Normalized to HD Level at MHz 77- Rev. Page 9 of 39

20 HD P OUT ENVELOPE (dbm) 3 P OUT ENVELOPE AT P IN = dbm P OUT ENVELOPE AT P IN = dbm VENV_N/VENV_P DELTA, P IN = dbm VENV_N/VENV_P DELTA, P IN = dbm 9 7 VENV_N/VENV_P DELTA (mv) P OUT ENVELOPE (dbm) P OUT ENVELOPE AT + C P OUT ENVELOPE AT + C P OUT ENVELOPE AT C V CTRL (V) Figure. HD POUT Envelope and VENV_N/VENV_P Delta vs. VCTRL at Various Total Input Power (PIN) Levels, Measurements Performed at GHz with Two Input Tones with Separation of MHz 77- P OUT RF PER TONE (dbm) Figure 7. POUT Envelope vs. POUT RF per Tone at Various Temperatures at frf = 33 GHz, Measurement Performed at 3. GHz IF with Two Tones at MHz Spacing, VCTRL = mv 77-9 Rev. Page of 39

21 RETURN LOSS IF and I/Q amplitude = dbm, VCC_DRV = VCC_DRV = VCC_AMP = VCC_ENV = VCC_AMP = VCC_BG = VCC_MIXER = VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA =. V, TA = C, and set Register xa to xe7, unless otherwise noted. Measurements in IF mode performed with a 9 hybrid, Register x3, Bit 7 =, and fif = 3. GHz. Measurements in I/Q mode are measured as a composite of the I and Q channel performance, VCM = V, Register x3, Bit 7 =, and Register x, Bits[:] = x, unless otherwise noted. I/Q fbb = MHz. VCTRL = VCTRL. VCTRL is the attenuation voltage at the VCTRL and VCTRL pins. VCTRL = mv, unless otherwise specified. Envelope detector measurements made with Register x3, Bit =. RF RETURN LOSS (dbm) V.9V.V Figure. RF Return Loss vs. RF Frequency at Various VCTRL Voltages 77-7 LO TO RF LEAKAGE (dbc) LO AT + C LO AT + C LO AT C 3 LO AT + C LO AT + C LO AT C LO AT + C 9 LO AT + C LO AT C LO FREQUENCY (GHz) Figure 7. LO to RF Leakage vs. LO Frequency for LO, LO, and LO at Various Temperatures (Uncalibrated) LO RETURN LOSS (db) LOP LON LO DIFFERENTIAL I/Q DIFFERENTIAL RETURN LOSS (db) I SIDE Q SIDE LO FREQUENCY (GHz) Figure 9. LO Return Loss vs. LO Frequency FREQUENCY (GHz) Figure 7. I/Q Differential Return Loss vs. Frequency (Taken Without Hybrids or Baluns) 77-7 Rev. Page of 39

22 IF RETURN LOSS (db) LO LEAKAGE (dbm) I SIDE Q SIDE IF FREQUENCY (GHz) Figure 7. IF Return Loss vs. IF Frequency (Taken Without Hybrid) LO LEAKAGE, V CTRL = mv LO LEAKAGE, V CTRL = mv LO LEAKAGE, V CTRL = mv LO LEAKAGE, V CTRL = 9mV LO LEAKAGE, V CTRL = mv LO LEAKAGE, V CTRL = mv LO LEAKAGE, V CTRL = mv 7 9 LO FREQUENCY (GHz) Figure 73. LO Leakage vs. LO Frequency at Different VCTRL Settings (Uncalibrated) LO LEAKAGE (dbm) LO LEAKAGE, V CTRL = mv LO LEAKAGE, V CTRL = mv LO LEAKAGE, V CTRL = mv LO LEAKAGE, V CTRL = 9mV LO LEAKAGE, V CTRL = mv LO LEAKAGE, V CTRL = mv LO LEAKAGE, V CTRL = mv 7 9 LO FREQUENCY (GHz) Figure 7. LO Leakage vs. LO Frequency at Different VCTRL Settings (Uncalibrated) LO LEAKAGE (dbm) LO LEAKAGE, V CTRL = mv LO LEAKAGE, V CTRL = mv LO LEAKAGE, V CTRL = mv LO LEAKAGE, V CTRL = 9mV LO LEAKAGE, V CTRL = mv LO LEAKAGE, V CTRL = mv LO LEAKAGE, V CTRL = mv 7 9 LO FREQUENCY (GHz) Figure 7. LO Leakage vs. LO Frequency at Different VCTRL Settings (Uncalibrated) x LO TO RF LEAKAGE (dbm) LO FREQUENCY (GHz) C + C + C Figure 7. LO to RF Leakage vs. LO Frequency at Various Temperatures (Calibrated) LO LEAKAGE (dbm) 7 9 C, IF_I + C, IF_I + C, IF_I C, IF_Q + C, IF_Q + C, IF_Q 7 9 LO FREQUENCY (GHz) Figure 77. LO Leakage vs. LO Frequency at Various Temperatures and IF_I and IF_Q (Taken Without Hybrid) Rev. Page of 39

23 LO LEAKAGE (dbm) C, I_N C, I_N + C, I_N + C, Q_N C, Q_N + C, Q_N + C, I_P C, I_P + C, I_P + C, Q_P C, Q_P + C, Q_P ENVELOPE DETECTOR DIFFERENTIAL RETURN LOSS (db) LO FREQUENCY (GHz) Figure 7. LO Leakage vs. LO Frequency at Various Temperatures and I_N, I_P, Q_N, and Q_P (Taken Without Hybrid(s)) FREQUENCY (GHz) Figure. Envelope Detector Differential Return Loss vs. Frequency 77- LO TO RF LEAKAGE (dbm) 7 9 V CTRL = V V CTRL =.V V CTRL =.V V CTRL =.V V CTRL =.V V CTRL =.V 7 9 LO FREQUENCY (GHz) Figure 79. LO to RF Leakage vs. LO Frequency at Various VCTRL (Calibrated) 77- Rev. Page 3 of 39

24 M N SPURIOUS PERFORMANCE Mixer spurious products are measured in dbc from the RF output power level. Spurious frequencies are calculated by (M IF) + (N LO) N/A means not applicable. Blank cells in the spurious performance tables indicate that the frequency is above GHz and is not measured. REF stands for reference RF output signal. The LO frequencies are referred from the frequencies applied to the. IF and I/Q amplitude = dbm. VCC_DRV = VCC_DRV = VCC_AMP = VCC_ENV = VCC_AMP = VCC_BG = VCC_MIXER = VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA =. V, T A = C, and set Register xa to xe7, unless otherwise noted. Measurements in IF mode performed with a 9 hybrid, Register x3, Bit 7 =, and fif = 3. GHz. Measurements in I/Q mode are measured as a composite of the I and Q channel performance, VCM = V, Register x3, Bit 7 =, and Register x, Bits[:] = x, unless otherwise noted. I/Q fbb = MHz. VCTRL = VCTRL. VCTRL is the attenuation voltage at the VCTRL and VCTRL pins. VCTRL = mv, unless otherwise specified. I/Q Mode fbb = MHz at dbm, LO =.97 GHz at + dbm. N LO M RF N/A REF fbb = MHz at dbm, LO = 9.7 GHz at + dbm, and frf = 39 GHz. M RF N LO N/A REF IF Mode fif = 3. GHz at dbm, LO =. GHz at + dbm, and frf = GHz. N LO M RF N/A REF fif = 3. GHz at dbm, LO =.7 GHz at + dbm, and frf = 39 GHz. M RF N LO N/A REF fif = 3. GHz at dbm, LO = 7.7 GHz at + dbm, and frf = GHz. N LO REF 7 M RF N/A fif = 3. GHz at dbm, LO =. GHz at + dbm, and frf = 39 GHz. M RF N LO REF N/A Rev. Page of 39

25 THEORY OF OPERATION The is a wideband microwave upconverter optimized for microwave radio designs operating in the GHz to GHz RF frequency range. See Figure for a functional block diagram of the device. The digital settings are controlled via the SPI. The has two modes of operation: Baseband quadrature modulation (I/Q mode) Single-sideband upconversion (IF mode) START-UP SEQUENCE To use the voltage control RF VVA and RF VVA (VCTRL and VCTRL), the VCC_VVA (. V) supply must be on. Similarly, to use the SPI control, it is necessary to turn on DVDD before using the SPI control pins. The SPI settings require the default settings to be changed during startup for optimum performance. Set Register xa to xe7 after each power-up or reset. BASEBAND QUADRATURE MODULATION (I/Q MODE) In I/Q mode, the input impedance of the baseband pins (I_P, I_N, Q_P, and Q_N) are Ω differential. These inputs can be loaded with a dc-coupled Ω differential load. I_P and I_N are the differential baseband I inputs, and Q_P and Q_N are the differential baseband Q inputs. These inputs can operate from a VCM of V to. V. The baseband I/Q ports can operate from dc to. GHz at each I and Q channel. To set the in I/Q mode, set MIXER_IF_EN bit (Register x3, Bit 7) to. When changing the external VCM, the internal mixer gate voltage also must be changed. To make this change, set the MIXER_VGATE bits (Register x, Bits[:]). The MIXER_ VGATE value follows the VCM such as, that for a V to. V VCM, MIXER_VGATE = 3.9 VCM +, and for a >. V to. V VCM, MIXER_VGATE = 3.7 VCM +.. SINGLE-SIDEBAND UPCONVERSION (IF MODE) The features the ability to upconvert a real IF input anywhere from. GHz to. GHz while suppressing the unwanted sideband by typically better than dbc. The IF inputs are quadrature to each other, Ω single ended, and are internally dc-coupled. IF_I and IF_Q are the quadrature IF inputs. An external 9 hybrid is required to select the appropriate sideband. To configure the in IF mode, set the MIXER_IF_EN bit (Register x3, Bit 7) to. The MIXER_IF_EN bit defaults to IF mode on SPI startup and reset. In addition, the baseband pins (I_P, I_N, Q_P, and Q_N) must see an open load for optimum performance in IF mode. LO INPUT PATH The LO input path operates from. GHz to. GHz with an LO amplitude range of dbm to + dbm. The LO has an internal quadrupler ( ) and a programmable band-pass filter. The LO band-pass filter is programmable using the QUAD_ FILTERS bits (Register x9, Bits[3:]). See the Performance at Different Quad Filter Settings section for more information on the QUAD_FILTERS settings. The LO path can operate either differentially or single ended. LOP and LON are the inputs to the LO path. The LO path can switch from differential to single-ended operation by setting the QUAD_SE_MODE bits (Register x9, Bits[9:]). See the Performance Between Differential vs. Single-Ended LO Input section for more information. When using the LO as single ended, the unused LO input pin must be terminated with a Ω load. Figure shows a block diagram of the LO path. LON LOP AMP Figure. LO Path Block Diagram LON LOP Enable the quadrupler by setting the QUAD_PD bits (Register x3, Bits[3:]) to x. To power down the quadrupler, set these bits to x7. SIDEBAND SUPPRESSION OPTIMIZATION Unwanted sideband can be upconverted from the quadrature error by generating the quadrature LO signals and the external quadrature inputs. Deviation from ideal quadrature (that is, total sideband rejection and no sideband tone upconverts) on these signals limits the amount of achievable sideband rejection. The offers approximately of quadrature phase adjustment in the LO path quadrature signals to suppress the sideband. Make these adjustments through the LOAMP_PH_ ADJ_I_FINE bits (Register x, Bits[3:7]) and the LOAMP_ PH_ADJ_Q_FINE bits (Register x, Bits[3:7]). These bits reject the unwanted sideband signal. To achieve the required sideband suppression, it may be necessary to adjust the amplitude difference between the quadrature inputs, as well externally. In I/Q mode, the recommendation is to adjust the sideband suppression through the external transceiver digital-to-analog converter (DAC). 77- Rev. Page of 39

26 CARRIER FEEDTHROUGH NULLING Carrier feedthrough results from minute dc offsets that occur on the internal mixer. In an I/Q modulator, nonzero differential offsets mix with the LO and result in carrier feedthrough to the RF output. In addition to this effect, some of the signal power at the LO input couples directly to the RF output (this may be because of the bond wire to bond wire coupling or coupling through the silicon substrate). The net carrier feedthrough at the RF output is the vector combination of the signals that appear at the output because of these two effects. The offers, in IF mode, LO feedthrough offset calibration adjustment in the LO path. Make these adjustments through the MXER_OFF_ADJ_I_N bits (Register x7, Bits[:], the MXER_OFF_ADJ_I_P bits (Register x7, Bits[:9]), the MXER_OFF_ADJ_Q_N bits (Register x, Bits[:]), and the MXER_OFF_ADJ_Q_P bits (Register x, Bits[:9] in order to reject the unwanted LO signal. For I/Q mode, the LO feedthrough offset amplitude and phase calibration optimization can be adjusted externally through a transceiver DAC. ENVELOPE DETECTOR The features an envelope detector with a pseudo differential voltage output. The envelope detector output pins are VENV_P and VENV_N. The turns on with the envelope detector turned off. To turn on the envelope detector, set the DET_EN bit (Bit, Register x3). The differential voltage output of the envelope detector rises linearly to the square of the input envelope voltage to the detector. The detector output ranges from dbm to dbm when the input two tone power ranges from dbm to dbm. The envelope detector has MHz, 3 db envelope bandwidth and GHz, db envelope bandwidth. The envelope detector precedes the VVA and the output driver of the. POWER DOWN AND RESET The SPI of the allows the user to power down the device circuits and reduce power consumption to typically 77 mw. To turn off the entire chip, set the BG_PD bit (Register x3, Bit ) to. In addition, individual blocks of the circuit can be powered down individually. To power down the quadrupler, set the QUAD_PD bits (Register x3, Bits[3:]) to x7. To power down the VGA, set the VGA_PD bit (Register x3, Bit ) to. To power down the mixer, set the MIXER_PD bit (Register x3, Bit ) to. To power down the detector, set the DET_EN bit (Register x3, Bit ) to. SERIAL PORT INTERFACE (SPI) The SPI of the allows the user to configure the device for specific functions or operations via a -wire SPI port. This interface provides users with added flexibility and customization. The SPI consists of four control lines: SCLK, SDI, SDO, and active low chip select lines, SEN/SEN. SEN and SEN must be connected together. The protocol consists of a write/read bit followed by six register address bits, data bits, and a parity bit. Both the address and data fields are organized MSB first and end with the LSB. For a write, set the first bit to. For a read, set the first bit to. The write cycle sampling must be performed on the rising edge. The bits of the serial write data are shifted in, MSB to lower sideband. The input logic level for the write cycle supports a. V interface. For a read cycle, up to bits of serial read data are shifted out, MSB first. After the bits of data shift out, the parity bit shifts out. The output logic level for a read cycle is. V. The parity bit always follows the direction of the data. If parity is not used, the transmitting end transmits zero instead of parity. The parity is odd, which means that the total number of ones transmitted during a command, including the read/write bit, the address bit, the data bit, and the parity bit, must be odd. Figure and Figure 3 show the SPI write and read protocol, respectively. SEN/SEN SCLK SDI R/W A A A3 A A A D D D3 D D D D9 D D7 D D D D3 D D D P Figure. SPI Write Timing Diagram 77-7 Rev. Page of 39

27 SEN/SEN SCLK SDI R/W A A A3 A A A SDO D D D3 D D D D9 D D7 D D D D3 D D D P 77- Figure 3. SPI Read Timing Diagram Rev. Page 7 of 39

28 APPLICATIONS INFORMATION BASEBAND QUADRATURE MODULATION FROM LOW FREQUENCIES Figure shows the I/Q mode performance at low baseband input frequencies. The measurements were performed at GHz, dbm input power, VCM = V, Register x3, Bit 7 =, dbm LO input power, and TA = C. AND SIDEBAND REJECTION (dbc) 3 SIDEBAND REJECTION CONVERSION GAIN k k k M M M BASEBAND FREQUENCY (Hz) Figure. Conversion Gain and Sideband Rejection vs. Baseband Frequency PERFORMANCE AT DIFFERENT QUAD FILTER SETTINGS Figure shows the conversion gain vs. RF frequency in IF mode at TA = C and LO input power = dbm for different QUAD_FILTERS settings. QUAD FILTERS = QUAD FILTERS = QUAD FILTERS = QUAD FILTERS = Figure. Conversion Gain vs. RF Frequency for Four Different QUAD_FILTERS Settings, fif = 3. GHz (Upper Sideband) Figure shows the LO to RF leakage vs. LO frequency at different quad filter settings. LO TO RF LEAKAGE (dbm) 3 QUAD FILTERS = QUAD FILTERS = QUAD FILTERS = QUAD FILTERS = LO FREQUENCY (GHz) Figure. LO to RF Leakage vs. LO Frequency for Four Different QUAD_FILTERS Settings VVA TEMPERATURE COMPENSATION Figure 7 shows the conversion gain vs. RF frequency at two different Register xa settings, the recommended setting (xe7) and a setting for higher gain, and three different temperatures for IF mode. The recommended value suggested in the Start-Up Sequence section provides the least variation in conversion gain over temperature. If the priority is to increase the conversion gain, Register xa can be set to xfa. However, at this value, the conversion gain variation over temperature can increase by db. C, xfa + C, xfa + C, xfa C, xe7 + C, xe7 + C, xe Figure 7. Conversion Gain vs. RF Frequency at Maximum Gain for Various Temperatures and Register xa Settings (Recommended and Higher Gain Setting), fif = 3. GHz Rev. Page of 39

29 Figure shows the conversion gain vs. RF frequency at two different Register xa settings, the recommended setting and the default setting, and three different temperatures for IF mode. The default values provides slightly less gain and a larger gain variation across temperature compared to the recommended setting. C, xe7 + C, xe7 + C, xe7 C, x + C, x + C, x Figure. Conversion Gain vs. RF Frequency at Maximum Gain for Various Temperatures and Register xa Settings (Default and Recommended Register xa Settings), fif = GHz PERFORMANCE BETWEEN DIFFERENTIAL vs. SINGLE-ENDED LO INPUT Figure 9 to Figure 9 show the conversion gain, output IP3, and sideband rejection performance for operating the LO input as differential vs. single ended. The measurements were performed with dbm LO input power, IF mode, with an IF frequency of 3. GHz, upper sideband, and TA = C. SINGLE-ENDED POSITIVE SIDE DISABLE SINGLE-ENDED NEGATIVE SIDE DISABLE DIFFERENTIAL Figure 9. Conversion Gain vs. RF Frequency for Three Different LO Mode Settings, fif = 3. GHz (Upper Sideband) SINGLE-ENDED POSITIVE SIDE DISABLE SINGLE-ENDED NEGATIVE SIDE DISABLE DIFFERENTIAL Figure 9. Output IP3 vs. RF Frequency for Three Different LO Mode Settings, RF Amplitude = dbm per Tone at MHz Spacing, fif = 3. GHz (Upper Sideband) OUTPUT IP3 (dbm) SIDEBAND REJECTION (dbc) 3 SINGLE-ENDED POSITIVE SIDE DISABLE SINGLE-ENDED NEGATIVE SIDE DISABLE DIFFERENTIAL Figure 9. Sideband Rejection vs. RF Frequency for Three Different LO Mode Settings, RF Amplitude = dbm per Tone at MHz Spacing, fif = 3. GHz (Upper Sideband) Rev. Page 9 of 39

30 PERFORMANCE ACROSS RF FREQUENCY AT FIXED INPUT FREQUENCIES The quadrupler operates from. GHz to GHz. When using the lower sideband, the conversion gain starts rolling off gradually after the quadrupler frequency reaches GHz. When using the upper sideband, the conversion gain starts rolling off when the quadrupler frequency is. GHz. Figure 9 and Figure 93 show the conversion gain vs. RF frequency in IF mode for fixed IF frequencies (TA = C, LO = dbm) for the upper sideband and lower sideband, respectively..ghz UPPER SIDEBAND GHz UPPER SIDEBAND GHz UPPER SIDEBAND 3GHz UPPER SIDEBAND GHz UPPER SIDEBAND GHz UPPER SIDEBAND GHz UPPER SIDEBAND 7GHz UPPER SIDEBAND Figure 9. Conversion Gain vs. RF Frequency for Multiple IF Frequency Settings (Upper Sideband).GHz LOWER SIDEBAND GHz LOWER SIDEBAND GHz LOWER SIDEBAND 3GHz LOWER SIDEBAND GHz LOWER SIDEBAND GHz LOWER SIDEBAND GHz LOWER SIDEBAND 7GHz LOWER SIDEBAND Figure 93. Conversion Gain vs. RF Frequency at Multiple IF Frequency Settings (Lower Sideband) Figure 9 and Figure 9 show the conversion gain vs. RF frequency in I/Q mode for multiple baseband (BB) frequencies (TA = C, LO = dbm) for upper sideband and lower sideband, respectively. I/Q,.GHz I/Q, GHz I/Q, GHz I/Q, 3GHz I/Q, GHz I/Q, GHz I/Q, GHz Figure 9. Conversion Gain vs. RF Frequency for Multiple Baseband Frequency Settings (Upper Sideband) I/Q,.GHz I/Q, GHz I/Q, GHz I/Q, 3GHz I/Q, GHz I/Q, GHz I/Q, GHz Figure 9. Conversion Gain vs. RF Frequency at Multiple Baseband Frequency Settings (Lower Sideband) Rev. Page of 39

31 PERFORMANCE ACROSS COMMON-MODE VOLTAGE IN I/Q MODE Figure 9, Figure 97, and Figure 9 show the performance at various common-mode voltages in I/Q mode. For each common-mode voltage, the mixer gate voltage was changed based on the equation described in the Baseband Quadrature Modulation (I/Q Mode) section. V.V.V.V.V.V.V.V.V Figure 9. Conversion Gain vs. RF Frequency at Multiple Common-Mode Voltages in I/Q Mode (fbb = MHz, LO = dbm, TA = C) V.V.V.V.V.V.V.V.V Figure 97. Output IP3 vs. RF Frequency at Multiple Common-Mode Voltages in I/Q Mode (fbb = MHz, LO = dbm, TA = C) OUTPUT IP3 (dbm) OPERATING VCTRL AND VCTRL INDEPENDENTLY The data shown in the Specifications section and the Typical Performance Characteristics section is based on the VCTRL and VCTRL voltages being equal. Finer gain regulation can be obtained if VCTRL and VCTRL are used separately. Operating VCTRL and VCTRL also allows either maintaining IP3 or noise figure performance while attenuating the RF output. Figure 99, Figure, and Figure show the conversion gain, input IP3, and noise figure vs. the RF frequency, respectively (IF = GHz, upper sideband, LO = dbm at TA = C), when VCTRL is equal to VCTRL. Figure, Figure 3, and Figure show the conversion gain, input IP3, and noise figure vs. the RF frequency, respectively (IF = GHz, upper sideband, LO = dbm at TA = C), when VCTRL is held at a minimum attenuation and VCTRL is changed. Figure, Figure, and Figure 7 show the conversion gain, input IP3, and noise figure vs. the RF frequency, respectively (IF = GHz, upper sideband, LO = dbm at TA = C), when VCTRL is held at minimum attenuation and VCTRL is changed. VCTRL = V, VCTRL = V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.3V, VCTRL =.3V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.7V, VCTRL =.7V VCTRL =.V, VCTRL =.V VCTRL =.9V, VCTRL =.9V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.3V, VCTRL =.3V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.7V, VCTRL =.7V VCTRL =.V, VCTRL =.V Figure 99. Conversion Gain vs. RF Frequency at Various VCTRL Voltages (VCTRL = VCTRL), IF Mode, IF Frequency = GHz, Upper Sideband 77- OUTPUT PdB (dbm) V.V.V.V.V.V.V.V.V.V.V.V.V.V Figure 9. Output PdB vs. RF Frequency at Multiple Common-Mode Figure. Conversion Gain vs. RF Frequency at Various VCTRL Voltages Voltages in I/Q Mode (fbb = MHz, LO = dbm, TA = C) (VCTRL =. V), IF Mode, IF Frequency = GHz, Upper Sideband Rev. Page 3 of 39 VCTRL = V VCTRL =.V VCTRL =.V VCTRL =.3V VCTRL =.V VCTRL =.V VCTRL =.V VCTRL =.7V VCTRL =.V VCTRL =.9V VCTRL =.V VCTRL =.V VCTRL =.V VCTRL =.3V VCTRL =.V VCTRL =.V VCTRL =.V VCTRL =.7V VCTRL =.V 77-3

32 VCTRL = V VCTRL =.V VCTRL =.V VCTRL =.3V VCTRL =.V VCTRL =.V VCTRL =.V VCTRL =.7V VCTRL =.V VCTRL =.9V VCTRL =.V VCTRL =.V VCTRL =.V VCTRL =.3V VCTRL =.V VCTRL =.V VCTRL =.V VCTRL =.7V VCTRL =.V INPUT IP3 (dbm) VCTRL = V VCTRL =.V VCTRL =.V VCTRL =.3V VCTRL =.V VCTRL =.V VCTRL =.V VCTRL =.7V VCTRL =.V VCTRL =.9V VCTRL =.V VCTRL =.V VCTRL =.V VCTRL =.3V VCTRL =.V VCTRL =.V VCTRL =.V VCTRL =.7V VCTRL =.V Figure. Conversion Gain vs. RF Frequency at Various VCTRL Voltages (VCTRL =. V), IF Mode, IF Frequency = GHz, Upper Sideband INPUT IP3 (dbm) VCTRL = V, VCTRL = V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.3V, VCTRL =.3V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.7V, VCTRL =.7V VCTRL =.V, VCTRL =.V VCTRL =.9V, VCTRL =.9V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.3V, VCTRL =.3V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.7V, VCTRL =.7V VCTRL =.V, VCTRL =.V Figure. Input IP3 vs. RF Frequency at Various VCTRL Voltages (VCTRL = VCTRL), I IF Mode, IF Frequency = GHz, Upper Sideband INPUT IP3 (dbm) VCTRL = V, VCTRL =.V VCTRL =.V VCTRL =.3V VCTRL =.V VCTRL =.V VCTRL =.V VCTRL =.7V VCTRL =.V VCTRL =.9V VCTRL =.V VCTRL =.V VCTRL =.V VCTRL =.3V VCTRL =.V VCTRL =.V VCTRL =.V VCTRL =.7V VCTRL =.V Figure 3. Input IP3 vs. RF Frequency at Various VCTRL Voltages (VCTRL =. V), IF Mode, IF Frequency = GHz, Upper Sideband Figure. Input IP3 vs. RF Frequency at Various VCTRL Voltages (VCTRL =. V), IF Mode, IF Frequency = GHz, Upper Sideband NOISE FIGURE (db) 3 VCTRL = V, VCTRL = V VCTRL =.9V, VCTRL =.9V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.3V, VCTRL =.3V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.3V, VCTRL =.3V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.7V, VCTRL =.7V VCTRL =.V, VCTRL =.V VCTRL =.V, VCTRL =.V VCTRL =.7V, VCTRL =.7V VCTRL =.V, VCTRL =.V Figure. Noise Figure vs. RF Frequency at Various VCTRL Voltages (VCTRL = VCTRL), IF Mode, IF Frequency = GHz, Upper Sideband NOISE FIGURE (db) 3 VCTRL = V VCTRL =.V VCTRL =.V VCTRL =.3V VCTRL =.V VCTRL =.V VCTRL =.V VCTRL =.7V VCTRL =.V VCTRL =.9V VCTRL =.V VCTRL =.V VCTRL =.V VCTRL =.3V VCTRL =.V VCTRL =.V VCTRL =.V VCTRL =.7V VCTRL =.V Figure. Noise Figure vs. RF Frequency at Various VCTRL Voltages (VCTRL =. V), IF Mode, IF Frequency = GHz, Upper Sideband Rev. Page 3 of 39

33 NOISE FIGURE (db) 3 VCTRL = V VCTRL =.V VCTRL =.V VCTRL =.3V VCTRL =.V VCTRL =.V VCTRL =.V VCTRL =.7V VCTRL =.V VCTRL =.9V VCTRL =.V VCTRL =.V VCTRL =.V VCTRL =.3V VCTRL =.V VCTRL =.V VCTRL =.V VCTRL =.7V VCTRL =.V Figure 7. Noise Figure vs. RF Frequency at Various VCTRL Voltages (VCTRL =. V), IF Mode, IF Frequency = GHz, Upper Sideband RECOMMENDED LAND PATTERN Solder the exposed pad on the underside of the to a low thermal and electrical impedance ground plane. This pad is typically soldered to an exposed opening in the solder mask on the evaluation board. Connect these ground vias to all other ground layers on the evaluation board to maximize heat dissipation from the device package. 77- Figure. Evaluation Board Layout for the LGA Package EVALUATION BOARD INFORMATION For more information about the evaluation board, refer to the -EVALZ user guide. 77- Rev. Page 33 of 39