<0.5 Ω CMOS, 1.65 V to 3.6 V, Quad SPST Switches ADG811/ADG812/ADG813

Transcription

1 <.5 Ω CMOS, 1.65 V to 3.6 V, Quad SPST Switches ADG811/ADG812/ADG813 FEATURES FUNCTIONAL BLOCK DIAGRAMS.5 Ω typical on resistance.8 Ω maximum on resistance at 125 C 1.65 V to 3.6 V operation Automotive temperature range: 4 C to +125 C High current carrying capability: 3 ma continuous Rail-to-rail switching operation Fast switching times: <25 ns Typical power consumption <.1 μw IN1 IN2 IN3 ADG811 S1 D1 S2 D2 S3 D3 IN1 IN2 IN3 ADG812 S1 D1 S2 D2 S3 D3 IN1 IN2 IN3 ADG813 S1 D1 S2 D2 S3 D3 APPLICATIONS Cellular phones MP3 players Power routing Battery-powered systems PCMCIA cards Modems Audio and video signal routing Communications systems IN4 S4 S4 IN4 IN4 D4 D4 SWITCHES SHOWN FOR A LOGIC 1 INPUT Figure 1. S4 D4 436-A-1 GENERAL DESCRIPTION The ADG811/ADG812/ADG813 are low voltage CMOS devices containing four independently selectable switches. These switches offer ultralow on resistance of less than.8 Ω over the full temperature range. The digital inputs can handle 1.8 V logic with a 2.7 V to 3.6 V supply. These devices contain four independent single-pole/singlethrow (SPST) switches. The ADG811 and ADG812 differ only in that the digital control logic is inverted. The ADG811 switches are turned on with a logic low on the appropriate control input, while a logic high is required to turn on the switches of the ADG812. The ADG813 contains two switches whose digital control logic is similar to the ADG811, while the logic is inverted on the other two switches. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. The ADG813 exhibits break-before-make switching action. The ADG811/ADG812/ADG813 are fully specified for 3.3 V, 2.5 V, and 1.8 V supply operation. The ADG811 is available in a 16-lead TSSOP package and a 16-lead LFCSP package, and the ADG812/ADG813 are available in a 16-lead TSSOP package. PRODUCT HIGHLIGHTS 1. <.8 Ω over full temperature range of 4 C to +125 C. 2. Single 1.65 V to 3.6 V operation. 3. Operational with 1.8 V CMOS logic. 4. High current handling capability (3 ma continuous current at 3.3 V). 5. Low THD + N (.2% typical). 6. Small 3 mm 3 mm LFCSP package and 16-lead TSSOP package. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 916, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... 1 Applications... 1 General Description... 1 Functional Block Diagrams... 1 Product Highlights... 1 Revision History... 2 Specifications... 3 Absolute Maximum Ratings... 6 ESD Caution... 6 Pin Configurations and Function Descriptions...7 Typical Performance Characteristics...8 Test Circuits Terminology Outline Dimensions Ordering Guide REVISION HISTORY 11/9 Rev. A to Rev. B Added 16-Lead LFCSP... Universal Changes to Table Changes to Pin Configurations and Function Description Section... 7 Moved Terminology Section Updated Outline Dimensions Changes to Ordering Guide /4 Rev. to Rev. A Updated Format... Universal Updated Package Choices... Universal 11/3 Revision : Initial Version Rev. B Page 2 of 16

3 SPECIFICATIONS VDD = 2.7 V to 3.6 V, GND = V, unless otherwise noted. Temperature range for the Y version is 4 C to +125 C. ADG811/ADG812/ADG813 Table 1. Parameter +25 C 4 C to +85 C 4 C to +125 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to VDD V On Resistance, RON.5 Ω typ VDD = 2.7 V, VS = V to VDD, IS = 1 ma; see Figure Ω max On Resistance Match Between.4 Ω typ VDD = 2.7 V, VS =.5 V, IS = 1 ma Channels, ΔRON.75.8 Ω max On Resistance Flatness, RFLAT (ON).1 Ω typ VDD = 2.7 V, VS = V to VDD, IS = 1 ma Ω max LEAKAGE CURRENTS VDD = 3.6 V Source Off Leakage, IS (Off) ±.2 na typ VS =.6 V/3.3 V, VD = 3.3 V/.6 V; see Figure 2 ±1 ±8 ±8 na max Drain Off Leakage, ID (Off) ±.2 na typ VS =.6 V/3.3 V, VD = 3.3 V/.6 V; see Figure 2 ±1 ±8 ±8 na max Channel On Leakage, ID, IS (On) ±.2 na typ VS = VD =.6 V or 3.3 V; see Figure 21 ±1 ±15 ±9 na max DIGITAL INPUTS Input High Voltage, VINH 2 V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH.5 μa typ VIN = VINL or VINH ±.1 μa max CIN, Digital Input Capacitance 6 pf typ DYNAMIC CHARACTERISTICS 1 ton 21 ns typ RL = 5 Ω, CL = 35 pf ns max VS = 1.5 V/ V; see Figure 22 toff 4 ns typ RL = 5 Ω, CL = 35 pf ns max VS = 1.5 V; see Figure 22 Break-Before-Make Time Delay, tbbm (ADG813 Only) 17 ns typ RL = 5 Ω, CL = 35 pf 5 ns min VS1 = VS2 = 1.5 V; see Figure 23 Charge Injection 3 pc typ VS = 1.5 V, RS = Ω, CL = 1 nf; see Figure 24 Off Isolation 67 db typ RL = 5 Ω, CL = 5 pf, f = 1 khz; see Figure 25 Channel-to-Channel Crosstalk 9 db typ RL = 5 Ω, CL = 5 pf, f = 1 khz; see Figure 27 Total Harmonic Distortion (THD + N).2 % RL = 32 Ω, f = 2 Hz to 2 khz, VS = 2 V p-p Insertion Loss.5 db typ RL = 5 Ω, CL = 5 pf, f = 1 khz 3 db Bandwidth 9 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 26 CS (Off) 3 pf typ CD (Off) 35 pf typ CD, CS (On) 6 pf typ POWER REQUIREMENTS VDD = 3.6 V IDD.3 μa typ Digital inputs = V or 3.6 V 1. 4 μa max 1 Guaranteed by design, but not subject to production test. Rev. B Page 3 of 16

4 VDD = 2.5 V ±.2 V, GND = V, unless otherwise noted. Temperature range for the Y version is 4 C to +125 C. Table 2. Parameter +25 C 4 C to +85 C 4 C to +125 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to VDD V On Resistance, RON.65 Ω typ VDD = 2.3 V, VS = V to VDD, IS = 1 ma; see Figure Ω max On Resistance Match Between.4 Ω typ VDD = 2.3 V, VS =.55 V, IS = 1 ma Channels, ΔRON.8.85 Ω max On Resistance Flatness, RFLAT (ON).16 Ω typ VDD = 2.3 V, VS = V to VDD, IS = 1 ma Ω max LEAKAGE CURRENTS VDD = 2.7 V Source Off Leakage, IS (Off) ±.2 na typ VS =.6 V/2.4 V, VD = 2.4 V/.6 V; see Figure 2 ±1 ±6 ±35 na max Drain Off Leakage, ID (Off) ±.2 na typ VS =.6 V/2.4 V, VD = 2.4 V/.6 V; see Figure 2 ±1 ±6 ±35 na max Channel On Leakage, ID, IS (On) ±.2 na typ VS = VD =.6 V or 2.4 V; see Figure 21 ±1 ±11 ±7 na max DIGITAL INPUTS Input High Voltage, VINH 1.7 V min Input Low Voltage, VINL.7 V max Input Current, IINL or IINH.5 μa typ VIN = VINL or VINH ±.1 μa max CIN, Digital Input Capacitance 6 pf typ DYNAMIC CHARACTERISTICS 1 ton 22 ns typ RL = 5 Ω, CL = 35 pf ns max VS = 1.5 V/ V; see Figure 22 toff 4 ns typ RL = 5 Ω, CL = 35 pf ns max VS = 1.5 V; see Figure 22 Break-Before-Make Time Delay, tbbm (ADG813 Only) 18 ns typ RL = 5 Ω, CL = 35 pf 5 ns min VS1 = VS2 = 1.5 V; see Figure 23 Charge Injection 25 pc typ VS = 1.25 V, RS = Ω, CL = 1 nf; see Figure 24 Off Isolation 67 db typ RL = 5 Ω, CL = 5 pf, f = 1 khz; see Figure 25 Channel-to-Channel Crosstalk 9 db typ RL = 5 Ω, CL = 5 pf, f = 1 khz; see Figure 27 Total Harmonic Distortion (THD + N).22 % RL = 32 Ω, f = 2 Hz to 2 khz, VS = 1.5 V p-p Insertion Loss.6 db typ RL = 5 Ω, CL = 5 pf, f = 1 khz 3 db Bandwidth 9 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 26 CS (Off) 32 pf typ CD (Off) 37 pf typ CD, CS (On) 6 pf typ POWER REQUIREMENTS VDD = 2.7 V IDD.3 μa typ Digital inputs = V or 2.7 V 1. 4 μa max 1 Guaranteed by design, but not subject to production test. Rev. B Page 4 of 16

5 VDD = 1.65 V to 1.95 V, GND = V, unless otherwise noted. Temperature range for the Y version is 4 C to +125 C. ADG811/ADG812/ADG813 Table 3. Parameter +25 C 4 C to +85 C 4 C to +125 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to VDD V On Resistance, RON 1 Ω typ VDD = 1.8 V, VS = V to VDD, IS = 1 ma; see Figure Ω max Ω max VDD = 1.65 V, VS = V to VDD, IS = 1 ma On Resistance Match Between.1 Ω typ VDD = 1.65 V, VS =.7 V, IS = 1 ma Channels, ΔRON LEAKAGE CURRENTS VDD = 1.95 V Source Off Leakage IS (Off) ±.2 na typ VS =.6 V/1.65 V, VD = 1.65 V/.6 V; see Figure 2 ±1 ±5 ±3 na max Drain Off Leakage ID (Off) ±.2 na typ VS =.6 V/1.65 V, VD = 1.65 V/.6 V; see Figure 2 ±1 ±5 ±3 na max Channel On Leakage ID, IS (On) ±.2 na typ VS = VD =.6 V or 1.65 V; see Figure 21 ±1 ±9 ±6 na max DIGITAL INPUTS Input High Voltage, VINH.65VDD V min Input Low Voltage, VINL.35VDD V max Input Current, IINL or IINH.5 μa typ VIN = VINL or VINH ±.1 μa max CIN, Digital Input Capacitance 6 pf typ DYNAMIC CHARACTERISTICS 1 ton 27 ns typ RL = 5 Ω, CL = 35 pf ns max VS = 1.5 V/ V; see Figure 22 toff 6 ns typ RL = 5 Ω, CL = 35 pf ns max VS = 1.5 V; see Figure 22 Break-Before-Make Time Delay, tbbm (ADG813 Only) 2 ns typ RL = 5 Ω, CL = 35 pf 5 ns min VS1 = VS2 = 1 V; see Figure 23 Charge Injection 15 pc typ VS = 1 V, RS = Ω, CL = 1 nf; see Figure 24 Off Isolation 67 db typ RL = 5 Ω, CL = 5 pf, f = 1 khz; Figure 25 Channel-to-Channel Crosstalk 9 db typ RL = 5 Ω, CL = 5 pf, f = 1 khz; see Figure 27 Total Harmonic Distortion (THD + N).14 % RL = 32 Ω, f = 2 Hz to 2 khz, VS = 1.2 V p-p Insertion Loss.8 db typ RL = 5 Ω, CL = 5 pf, f = 1 khz 3 db Bandwidth 9 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 26 CS (Off) 32 pf typ CD (Off) 38 pf typ CD, CS (On) 6 pf typ POWER REQUIREMENTS VDD = 1.95 V IDD.3 μa typ Digital inputs = V or 1.95 V 1. 4 μa max 1 Guaranteed by design, but not subject to production test. Rev. B Page 5 of 16

6 ABSOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise noted. Table 4. Parameter Rating VDD to GND.3 V to +4.6 V Analog Inputs 1.3 V to VDD +.3 V Digital Inputs 1 GND.3 V to 4.6 V or 1 ma, whichever occurs first Peak Current, S or D (Pulsed at 1 ms, 1% duty-cycle maximum) 3.3 V Operation 5 ma 2.5 V Operation 46 ma 1.8 V Operation 42 ma Continuous Current, S or D 3.3 V Operation 3 ma 2.5 V Operation 275 ma 1.8 V Operation 25 ma Operating Temperature Range, 4 C to +125 C Automotive (Y Version) Storage Temperature Range 65 C to +15 C Junction Temperature 15 C TSSOP Package θja Thermal Impedance 15 C/W θjc Thermal Impedance 27 C/W LFCSP Package θja Thermal Impedance 7 C/W IR Reflow, Peak Temperature <2 sec 235 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. Table 5. ADG811/ADG812 Truth Table ADG811 IN ADG812 IN Switch Condition 1 On 1 Off Table 6. ADG813 Truth Table Logic Switch 1, Switch 4 Switch 2, Switch 3 Off On 1 On Off ESD CAUTION 1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. Rev. B Page 6 of 16

7 D4 IN4 IN3 D D1 15 IN1 14 IN2 13 D2 ADG811/ADG812/ADG813 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS IN1 D1 S1 NC GND S4 D4 IN ADG811/ ADG812/ ADG813 TOP VIEW (Not to Scale) NC = NO CONNECT 16 IN2 15 D2 14 S2 13 VDD 12 NC 11 S3 1 D3 9 IN3 Figure 2. ADG811/ADG812/ADG813 Pin Configuration (16-Lead TSSOP) 436-A-2 S1 1 NC 2 GND 3 S4 4 PIN 1 INDICATOR ADG811 TOP VIEW (Not to Scale) 12 S2 11 VDD 1 NC 9 S3 NOTES 1. NC = NO CONNECT. 2. CONNECT EXPOSED PAD TO GND. Figure 3. ADG811 Pin Configuration (16-Lead LFCSP) Table 7. ADG811/ADG812/ADG813 Pin Configuration (16-Lead TSSOP) Pin No. Mnemonic Definition 1 IN1 Logic control input. 2 D1 Drain Terminal. This pin may be an 3 S1 Source Terminal. This pin may be an 4 NC No Connect. 5 GND Ground ( V) reference. 6 S4 Source Terminal. This pin may be an 7 D4 Drain Terminal. This pin may be an 8 IN4 Logic Control Input. 9 IN3 Logic Control Input. 1 D3 Drain Terminal. This pin may be an 11 S3 Source Terminal. This pin may be an 12 NC No Connect. 13 VDD Most Positive Power Supply Potential. 14 S2 Source Terminal. This pin may be an 15 D2 Drain Terminal. This pin may be an 16 IN2 Logic Control Input. Table 8. ADG811 Pin Configuration (16-Lead LFCSP) Pin No. Mnemonic Definition 1 S1 Source Terminal. This pin may be an 2 NC No Connect. 3 GND Ground ( V) Reference. 4 S4 Source Terminal. This pin may be an 5 D4 Drain Terminal. This pin may be an 6 IN4 Logic Control Input. 7 IN3 Logic Control Input. 8 D3 Drain Terminal. This pin may be an 9 S3 Source Terminal. This pin may be an 1 NC No Connect. 11 VDD Most Positive Power Supply Potential. 12 S2 Source Terminal. This pin may be an 13 D2 Drain Terminal. This pin may be an 14 IN2 Logic Control Input. 15 IN1 Logic Control Input. 16 D1 Drain Terminal. This pin may be an EPAD Connect exposed pad to GND. Rev. B Page 7 of 16

8 TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C = 3V = 2.7V = 3.3V ON RESISTANCE (Ω) = 3.6V = 3.3V ON RESISTANCE (Ω) C 4 C +125 C +85 C V D, V S (V) 436-A V D, V S (V) 436-A-6 Figure 4. On Resistance vs. VD (VS), VDD = 2.7 V to 3.6 V Figure 7. On Resistance vs. VD (VS) for Different Temperatures, VDD = 3.3 V.8 T A = 25 C 1.2 = 2.5V.7 = 2.3V 1. ON RESISTANCE (Ω) = 2.5V = 2.7V ON RESISTANCE (Ω) C +85 C +25 C 4 C V D, V S (V) 436-A V D, V S (V) 436-A-7 Figure 5. On Resistance vs. VD (VS), VDD = 2.5 V ±.2 V Figure 8. On Resistance vs. VD (VS) for Different Temperatures, VDD = 2.5 V ON RESISTANCE (Ω) T A = 25 C = 1.8V = 1.65V = 1.95V ON RESISTANCE (Ω) = 1.8V +125 C +85 C +25 C 4 C V D, V S (V) 436-A V D, V S (V) 436-A-8 Figure 6. On Resistance vs. VD (VS), VDD = 1.8 V ±.15 V Figure 9. On Resistance vs. VD (VS) for Different Temperatures, VDD = 1.8 V Rev. B Page 8 of 16

9 CURRENT (na) = 3.3V I D (OFF) I D, I S (ON) I S (OFF) Q INJ (pc) T A = 25 C V CC = 3.6V V CC = 2.5V V CC = 1.8V TEMPERATURE ( C) 436-A V S (V) 436-A-12 Figure 1. Leakage Current vs. Temperature, VDD = 3.3 V Figure 13. Charge Injection (QINJ) vs. Source Voltage (VS) 1 = 2.5V 35 I D (OFF) 3 t ON V CC = 1.8V CURRENT (na) I S (OFF) I D, I S (ON) TIME (ns) V CC = 2.5V V CC = 3V t OFF = 2.5V = 1.8V V CC = 3V TEMPERATURE ( C) 436-A TEMPERATURE ( C) 436-A-13 Figure 11. Leakage Current vs. Temperature, VDD = 2.5 V Figure 14. ton/toff Times vs. Temperature 1 = 1.8V I D (OFF) 1 1 CURRENT (na) I S (OFF) I D, I S (ON) ATTENUATION (db) T A = 25 C V CC = 3.3V/2.5V/1.8V TEMPERATURE ( C) 436-A FREQUENCY (MHz) 436-A-14 Figure 12. Leakage Current vs. Temperature, VDD = 1.8 V Figure 15. On Response vs. Frequency Rev. B Page 9 of 16

10 1 2 T A = 25 C V CC = 3.3V/2.5V/1.8V.8.6 = 2.5V T A = 25 C 32Ω LOAD 1.5V p-p ATTENUATION (db) THD+N (%) FREQUENCY (MHz) Figure 16. Crosstalk vs. Frequency 436-A k 2k 5k 1k 2k FREQUENCY (Hz) Figure 18. Total Harmonic Distortion + Noise (THD + N) vs. Frequency 436-A-17 ATTENUATION (db) T A = 25 C V CC = 3.3V/2.5V/1.8V FREQUENCY (MHz) Figure 17. Off Isolation vs. Frequency 436-A-16 Rev. B Page 1 of 16

11 TEST CIRCUITS I DS V1 V S S D R ON = V1/I DS Figure 19. On Resistance 436-A-18 V S I S (OFF) I D (OFF) A S D A V D Figure 2. Off Leakage 436-A-19 NC I D (ON) S D A Figure 21. On Leakage V D 436-A-2.1μF V IN ADG811 5% 5% V S IN S D R L V OUT C L 35pF V IN ADG812 5% 5% 9% 9% GND V OUT t ON t OFF 436-A-21 Figure 22. Switching Times.1μF S1 V S1 S2 V S2 IN1, IN2 V IN GND D1 D2 R L2 V OUT2 C L2 35pF R L1 C L1 35pF V OUT1 V IN V OUT V 8% 5% 5% t BBM 8% t BBM 436-A-22 Figure 23. Break-Before-Make Time Delay, tbbm (ADG813 Only) V IN SW ON SW OFF R S S D V OUT V S IN GND C L 1nF V OUT ΔV OUT Q INJ = C L ΔV OUT 436-A-23 Figure 24. Charge Injection Rev. B Page 11 of 16

12 .1μF S D GND NETWORK ANALYZER V S R L V OUT OFF ISOLATION = 2 LOG VS 436-A-24 Figure 25. Off Isolation.1μF S D GND NETWORK ANALYZER V S R L V OUT WITH SWITCH INSERTION LOSS = 2 LOG V OUT WITHOUT SWITCH 436-A-25 Figure 26. Bandwidth.1μF NETWORK ANALYZER V OUT R L S1 S2 D R L V S GND CHANNEL-TO-CHANNEL CROSSTALK = 2 LOG V OUT V S 436-A-26 Figure 27. Channel-to-Channel Crosstalk Rev. B Page 12 of 16

13 TERMINOLOGY IDD Positive supply current. VD, VS Analog voltage on Terminal D, Terminal S. RON Ohmic resistance between D and S. RFLAT (ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. ΔRON On resistance match between any two channels, that is, RON maximum RON minimum. IS (Off) Source leakage current with the switch off. ID (Off) Drain leakage current with the switch off. ID, IS (On) Channel leakage current with the switch on. VINL Maximum input voltage for Logic. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. CS (Off) Off switch source capacitance. Measured with reference to ground. CD (Off) Off switch drain capacitance. Measured with reference to ground. CD, CS (On) On switch capacitance. Measured with reference to ground. CIN Digital input capacitance. ton Delay time between the 5% and the 9% points of the digital input and switch on condition. toff Delay time between the 5% and the 9% points of the digital input and switch off condition. tbbm On or off time measured between the 8% points of both switches, when switching from one to another. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during on-to-off switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another because of parasitic capacitance. 3 db Bandwidth The frequency at which the output is attenuated by 3 db. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N The ratio of the harmonic amplitudes plus noise of a signal to the fundamental. Rev. B Page 13 of 16

14 OUTLINE DIMENSIONS BSC PIN 1.65 BSC.3.19 COPLANARITY MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters PIN 1 INDICATOR 3. BSC SQ TOP VIEW 2.75 BSC SQ MAX.3 PIN 1 INDICATOR * (BOTTOM 16 VIEW) SQ 1.15 EXPOSED PAD SEATING PLANE 12 MAX.8 MAX.65 TYP MAX.2 NOM.2 REF.5 BSC 1.5 REF 9 8 *COMPLIANT TO JEDEC STANDARDS MO-22-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Figure Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm 3 mm Body, Very Thin Quad (CP-16-2) Dimensions shown in millimeters 7228-A Rev. B Page 14 of 16

15 ORDERING GUIDE Model Temperature Range Package Description Package Option ADG811YRU 4 C to +125 C 16-Lead Thin Shrink Small Outline [TSSOP] RU-16 ADG811YRU-REEL 4 C to +125 C 16-Lead Thin Shrink Small Outline [TSSOP] RU-16 ADG811YRU-REEL7 4 C to +125 C 16-Lead Thin Shrink Small Outline [TSSOP] RU-16 ADG811YRUZ 1 4 C to +125 C 16-Lead Thin Shrink Small Outline [TSSOP] RU-16 ADG811YCPZ-REEL 1 4 C to +125 C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-2 ADG811YCPZ-REEL7 1 4 C to +125 C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-2 ADG812YRU 4 C to +125 C 16-Lead Thin Shrink Small Outline [TSSOP] RU-16 ADG812YRU-REEL 4 C to +125 C 16-Lead Thin Shrink Small Outline [TSSOP] RU-16 ADG812YRU-REEL7 4 C to +125 C 16-Lead Thin Shrink Small Outline [TSSOP] RU-16 ADG812YRUZ 1 4 C to +125 C 16-Lead Thin Shrink Small Outline [TSSOP] RU-16 ADG812YRUZ-REEL7 1 4 C to +125 C 16-Lead Thin Shrink Small Outline [TSSOP] RU-16 ADG813YRU 4 C to +125 C 16-Lead Thin Shrink Small Outline [TSSOP] RU-16 ADG813YRU-REEL 4 C to +125 C 16-Lead Thin Shrink Small Outline [TSSOP] RU-16 ADG813YRU-REEL7 4 C to +125 C 16-Lead Thin Shrink Small Outline [TSSOP] RU-16 ADG813YRUZ 1 4 C to +125 C 16-Lead Thin Shrink Small Outline [TSSOP] RU-16 1 Z = RoHS Compliant Part. Rev. B Page 15 of 16

16 NOTES Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D /9(B) Rev. B Page 16 of 16