High Voltage, Latch-up Proof, 4-Channel Multiplexer ADG5404

Transcription

1 ata Sheet FEATURES Latch-up proof 8 kv HBM ES rating Low on resistance (<1 Ω) ±9 V to ±22 V dual-supply operation 9 V to 4 V single-supply operation 48 V supply maximum ratings Fully specified at ±15 V, ±2 V, +12 V, and +36 V VSS to V analog signal range APPLICATIONS Relay replacement Automatic test equipment ata acquisition Instrumentation Avionics Audio and video switching Communication systems High Voltage, Latch-up Proof, 4-Channel Multiplexer AG544 FUNCTIONAL BLOCK IAGRAM S1 S2 S3 S4 AG544 1 OF 4 ECOER A A1 EN Figure GENERAL ESCRIPTION The AG544 is a complementary metal-oxide semiconductor (CMOS) analog multiplexer, comprising four single channels. The on-resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching audio signals. The AG544 is designed on a trench process, which guards against latch-up. A dielectric trench separates the P and N channel transistors, thereby preventing latch-up even under severe overvoltage conditions. The AG544 switches one of four inputs to a common output,, as determined by the 3-bit binary address lines, A, A1, and EN. Logic on the EN pin disables the device. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. All switches exhibit break-before-make switching action. PROUCT HIGHLIGHTS 1. Trench Isolation Guards Against Latch-Up. A dielectric trench separates the P and N channel transistors, thereby preventing latch-up even under severe overvoltage conditions. 2. Low RON. 3. ual-supply Operation. For applications where the analog signal is bipolar, the AG544 can be operated from dual supplies of up to ±22 V. 4. Single-Supply Operation. For applications where the analog signal is unipolar, the AG544 can be operated from a single-rail power supply of up to 4 V V logic-compatible digital inputs: VINH = 2. V, VINL =.8 V. 6. No VL logic power supply required. Rev. B ocument Feedback Information furnished by Analog evices is believed to be accurate and reliable. However, no responsibility is assumed by Analog evices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog evices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 916, Norwood, MA , U.S.A. Tel: Analog evices, Inc. All rights reserved. Technical Support

2 AG544 TABLE OF CONTENTS Functional Block iagram... 1 General escription... 1 Revision History... 2 Specifications... 3 ±15 V ual Supply... 3 ±2 V ual Supply V Single Supply V Single Supply... 6 Continuous Current per Channel, S or... 7 Absolute Maximum Ratings... 8 ata Sheet ES Caution...8 Pin Configurations and Function escriptions...9 Truth Table...9 Typical Performance Characteristics... 1 Test Circuits Terminology Trench Isolation Applications Information Outline imensions... 2 Ordering Guide... 2 REVISION HISTORY 11/217 Rev. A to Rev. B Changes to Table Changes to Table Changes to Table Changes to Table Changes to Figure Updated Outline imensions... 2 Change to Ordering Guide /211 Rev. to Rev. A Changes to Product Highlights... 1 Change to ISS Parameter, Table Updated Outline imensions /21 Revision : Initial Version Rev. B Page 2 of 2

3 ata Sheet AG544 SPECIFICATIONS ±15 V UAL SUPPLY V = 15 V ± 1%, VSS = 15 V ± 1%, GN = V, unless otherwise noted. Table 1. Parameter 25 C 4 C to +85 C 4 C to +125 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to VSS V On Resistance, RON 9.8 Ω typ VS = ±1 V, IS = 1 ma; see Figure Ω max V = V, VSS = 13.5 V On-Resistance Match.35 Ω typ VS = ±1 V, IS = 1 ma Between Channels, RON Ω max On-Resistance Flatness, RFLAT(ON) 1.2 Ω typ VS = ±1 V, IS = 1 ma Ω max LEAKAGE CURRENTS V = V, VSS = 16.5 V Source Off Leakage, IS (Off) ±.5 na typ VS = VS = ±1 V, V = 1 V; see Figure 24 ±.25 ±.75 ±6 na max rain Off Leakage, I (Off) ±.1 na typ VS = VS = ±1 V, V = 1 V; see Figure 24 ±.4 ±2 ±16 na max Channel On Leakage, I, IS (On) ±.1 na typ VS = V = ±1 V; see Figure 25 ±.4 ±2 ±16 na max IGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH.2 µa typ VIN = VGN or V ±.1 µa max igital Input Capacitance, CIN 5 pf typ YNAMIC CHARACTERISTICS 1 Transition Time, ttransition 187 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 1 V; see Figure 3 ton (EN) 16 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 1 V; see Figure 32 toff (EN) 125 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 1 V; see Figure 32 Break-Before-Make Time elay, t 45 ns typ RL = 3 Ω, CL = 35 pf 12 ns min VS1 = VS2 = 1 V; see Figure 31 Charge Injection, QINJ 22 pc typ VS = V, RS = Ω, CL = 1 nf; see Figure 33 Off Isolation 78 db typ RL = 5 Ω, CL = 5 pf, f = 1 khz; see Figure 26 Channel-to-Channel Crosstalk 58 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 28 Total Harmonic istortion + Noise.9 % typ RL = 1k Ω, 15 V p-p, f = 2 Hz to 2 khz; see Figure 29 3 db Bandwidth 53 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 27 Insertion Loss.7 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 27 CS (Off) 19 pf typ VS = V, f = 1 MHz C (Off) 92 pf typ VS = V, f = 1 MHz C, CS (On) 132 pf typ VS = V, f = 1 MHz POWER REQUIREMENTS V = V, VSS = 16.5 V I 45 µa typ igital inputs = V or V 55 7 µa max ISS.1 µa typ igital inputs = V or V 1 µa max V/VSS ±9/±22 V min/max GN = V 1 Guaranteed by design; not subject to production test. Rev. B Page 3 of 2

4 AG544 ata Sheet ±2 V UAL SUPPLY V = 2 V ± 1%, VSS = 2 V ± 1%, GN = V, unless otherwise noted. Table 2. Parameter 25 C 4 C to +85 C 4 C to +125 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to VSS V On Resistance, RON 9 Ω typ VS = ±15 V, IS = 1 ma; see Figure Ω max V = +18 V, VSS = 18 V On-Resistance Match.35 Ω typ VS = ±15 V, IS = 1 ma Between Channels, RON Ω max On-Resistance Flatness, RFLAT(ON) 1.5 Ω typ VS = ±15 V, IS = 1 ma Ω max LEAKAGE CURRENTS V = +22 V, VSS = 22 V Source Off Leakage, IS (Off) ±.5 na typ VS = ±15 V, V = 15 V; see Figure 24 ±.25 ±.75 ±6 na max rain Off Leakage, I (Off) ±.1 na typ VS = ±15 V, V = 15 V; see Figure 24 ±.4 ±2 ±16 na max Channel On Leakage, I, IS (On) ±.1 na typ VS = V = ±15 V; see Figure 25 ±.4 ±2 ±16 na max IGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH.2 µa typ VIN = VGN or V ±.1 µa max igital Input Capacitance, CIN 5 pf typ YNAMIC CHARACTERISTICS 1 Transition Time, ttransition 175 ns typ RL = 3 Ω, CL = 35 pf ns max VS = +1 V; see Figure 3 ton (EN) 148 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 1 V; see Figure 32 toff (EN) 12 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 1 V; see Figure 32 Break-Before-Make Time elay, t 4 ns typ RL = 3 Ω, CL = 35 pf 1 ns min VS1 = VS2 = 1 V; see Figure 31 Charge Injection, QINJ 29 pc typ VS = V, RS = Ω, CL = 1 nf; see Figure 33 Off Isolation 78 db typ RL = 5 Ω, CL = 5 pf, f = 1 khz; see Figure 26 Channel-to-Channel Crosstalk 58 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 28 Total Harmonic istortion + Noise.8 % typ RL = 1 kω, 2 V p-p, f = 2 Hz to 2 khz; see Figure 29 3 db Bandwidth 54 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 27 Insertion Loss.6 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 27 CS (Off) 18 pf typ VS = V, f = 1 MHz C (Off) 88 pf typ VS = V, f = 1 MHz C, CS (On) 129 pf typ VS = V, f = 1 MHz POWER REQUIREMENTS V = +22 V, VSS = 22 V I 5 µa typ igital inputs = V or V 7 11 µa max ISS.1 µa typ igital inputs = V or V 1 µa max V/VSS ±9/±22 V min/max GN = V 1 Guaranteed by design; not subject to production test. Rev. B Page 4 of 2

5 ata Sheet AG V SINGLE SUPPLY V = 12 V ± 1%, VSS = V, GN = V, unless otherwise noted. Table 3. Parameter 25 C 4 C to +85 C 4 C to +125 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to V V On Resistance, RON 19 Ω typ VS = V to 1 V, IS = 1 ma; see Figure Ω max V = 1.8 V, VSS = V On-Resistance Match.4 Ω typ VS = V to 1 V, IS = 1 ma Between Channels, RON Ω max On-Resistance Flatness, RFLAT(ON) 4.4 Ω typ VS = V to 1 V, IS = 1 ma Ω max LEAKAGE CURRENTS V = 13.2 V, VSS = V Source Off Leakage, IS (Off) ±.2 na typ VS = 1 V/1 V, V = 1 V/1 V; see Figure 24 ±.25 ±.75 ±6 na max rain Off Leakage, I (Off) ±.5 na typ VS = 1 V/1 V, V = 1 V/1 V; see Figure 24 ±.4 ±2 ±16 na max Channel On Leakage, I, IS (On) ±.5 na typ VS = V = 1 V/1 V; see Figure 25 ±.4 ±2 ±16 na max IGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH.2 µa typ VIN = VGN or V ±.1 µa max igital Input Capacitance, CIN 5 pf typ YNAMIC CHARACTERISTICS 1 Transition Time, ttransition 266 ns typ RL = 3 Ω, CL = 35 pf ns max VS = +8 V; see Figure 3 ton (EN) 26 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 8 V; see Figure 32 toff (EN) 135 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 8 V; see Figure 32 Break-Before-Make Time elay, t 125 ns typ RL = 3 Ω, CL = 35 pf 45 ns min VS1 = VS2 = 8 V; see Figure 31 Charge Injection, QINJ 92 pc typ VS = 6 V, RS = Ω, CL = 1 nf; see Figure 33 Off Isolation 78 db typ RL = 5 Ω, CL = 5 pf, f = 1MHz; see Figure 26 Channel-to-Channel Crosstalk 58 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 28 Total Harmonic istortion + Noise.75 % typ RL = 1k Ω, 6 V p-p, f = 2 Hz to 2 khz; see Figure 29 3 db Bandwidth 43 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 27 Insertion Loss 1.36 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 27 CS (Off) 22 pf typ VS = 6 V, f = 1 MHz C (Off) 15 pf typ VS = 6 V, f = 1 MHz C, CS (On) 14 pf typ VS = 6 V, f = 1 MHz POWER REQUIREMENTS V = 13.2 V I 4 µa typ igital inputs = V or V 5 65 µa max V 9/4 V min/max GN = V, VSS = V 1 Guaranteed by design; not subject to production test. Rev. B Page 5 of 2

6 AG544 ata Sheet +36 V SINGLE SUPPLY V = 36 V ± 1%, VSS = V, GN = V, unless otherwise noted. Table 4. Parameter 25 C 4 C to +85 C 4 C to +125 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to V V On Resistance, RON 1.6 Ω typ VS = V to 3 V, IS = 1 ma; see Figure Ω max V = 32.4 V, VSS = V On-Resistance Match.35 Ω typ VS = V to 3 V, IS = 1 ma Between Channels, RON Ω max On-Resistance Flatness, RFLAT(ON) 2.7 Ω typ VS = V to 3 V, IS = 1 ma Ω max LEAKAGE CURRENTS V =39.6 V, VSS = V Source Off Leakage, IS (Off) ±.5 na typ VS = 1 V/3 V, V = 3 V/1 V; see Figure 24 ±.25 ±.75 ±6 na max rain Off Leakage, I (Off) ±.1 na typ VS = 1 V/3 V, V = 3 V/1 V; see Figure 24 ±.4 ±2 ±16 na max Channel On Leakage, I, IS (On) ±.1 na typ VS = V = 1 V/3 V; see Figure 25 ±.4 ±2 ±16 na max IGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH.2 µa typ VIN = VGN or V ±.1 µa max igital Input Capacitance, CIN 5 pf typ YNAMIC CHARACTERISTICS 1 Transition Time, ttransition 196 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 18 V; see Figure 3 ton (EN) 17 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 18 V; see Figure 32 toff (EN) 13 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 18 V; see Figure 32 Break-Before-Make Time elay, t 52 ns typ RL = 3 Ω, CL = 35 pf 13 ns min VS1 = VS2 = 18 V; see Figure 31 Charge Injection, QINJ 28 pc typ VS = 18 V, RS = Ω, CL = 1 nf; see Figure 33 Off Isolation 78 db typ RL = 5 Ω, CL = 5 pf, f = 1MHz; see Figure 26 Channel-to-Channel Crosstalk 58 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 28 Total Harmonic istortion + Noise.3 % typ RL = 1k Ω, 18 V p-p, f = 2 Hz to 2 khz; see Figure 29 3 db Bandwidth 47 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 27 Insertion Loss.85 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 27 CS (Off) 18 pf typ VS = 18 V, f = 1 MHz C (Off) 89 pf typ VS = 18 V, f = 1 MHz C, CS (On) 128 pf typ VS = 18 V, f = 1 MHz POWER REQUIREMENTS V = 39.6 V I 8 µa typ igital inputs = V or V 1 13 µa max V 9/4 V min/max GN = V, VSS = V 1 Guaranteed by design; not subject to production test. Rev. B Page 6 of 2

7 ata Sheet AG544 CONTINUOUS CURRENT PER CHANNEL, S OR Table 5. Parameter 25 C 85 C 125 C Unit CONTINUOUS CURRENT, S OR V = +15 V, VSS = 15 V TSSOP (θja = C/W) ma max LFCSP (θja = 3.4 C/W) ma max V = +2 V, VSS = 2 V TSSOP (θja = C/W) ma max LFCSP (θja = 3.4 C/W) ma max V = 12 V, VSS = V TSSOP (θja = C/W) ma max LFCSP (θja = 3.4 C/W) ma max V = 36 V, VSS = V TSSOP (θja = C/W) ma max LFCSP (θja = 3.4 C/W) ma max Rev. B Page 7 of 2

8 AG544 ata Sheet ABSOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise noted. Table 6. Parameter Rating V to VSS 48 V V to GN.3 V to +48 V VSS to GN +.3 V to 48 V Analog Inputs 1 VSS.3 V to V +.3 V or 3 ma, whichever occurs first igital Inputs 1 VSS.3 V to V +.3 V or 3 ma, whichever occurs first Peak Current, Sx or Pins 515 ma (pulsed at 1 ms, 1% duty cycle maximum) Continuous Current, S or 2 ata + 15% Operating Temperature Range 4 C to +125 C Storage Temperature Range 65 C to +15 C Junction Temperature 15 C Thermal Impedance, θja 16-Lead TSSOP, θja Thermal C/W Impedance (4-Layer Board) 16-Lead LFCSP, θja Thermal 3.4 C/W Impedance (4-Layer Board) Reflow Soldering Peak 26(+/ 5) C Temperature, Pb Free Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Only one absolute maximum rating can be applied at any one time. ES CAUTION 1 Overvoltages at the Sx and pins are clamped by internal diodes. Limit current to the maximum ratings given. 2 See Table 5. Rev. B Page 8 of 2

9 ata Sheet AG544 PIN CONFIGURATIONS AN FUNCTION ESCRIPTIONS EN A A1 NC A 1 14 A1 EN 2 13 GN 3 AG V S1 4 TOP VIEW 11 S3 (Not to Scale) S2 5 1 S4 6 9 NC NC 7 8 NC NC = NO CONNECT Figure 2. TSSOP Pin Configuration 1 12 GN NC 2 AG V TOP VIEW S1 3 (Not so Scale) 1 S3 S2 4 9 S4 5 6 NC NC NC NOTES 1. NC = NO CONNECT. 2. EXPOSE PA TIE TO SUBSTRATE,. Figure 3. LFCSP Pin Configuration Table 7. Pin Function escriptions Pin No. TSSOP LFCSP Mnemonic escription 1 15 A Logic Control Input EN Active High igital Input. When this pin is low, the device is disabled and all switches are off. When this pin is high, the Ax logic inputs determine the on switches. 3 1 VSS Most Negative Power Supply Potential. 4 3 S1 Source Terminal. Can be an input or an output. 5 4 S2 Source Terminal. Can be an input or an output. 6 6 rain Terminal. Can be an input or an output. 7 to 9 2, 5, 7, 8, 13 NC No Connection. 1 9 S4 Source Terminal. Can be an input or an output S3 Source Terminal. Can be an input or an output V Most Positive Power Supply Potential GN Ground ( V) Reference A1 Logic Control Input. EP Exposed Pad The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS. TRUTH TABLE Table 8. EN A1 A S1 S2 S3 S4 X 1 X 1 Off Off Off Off 1 On Off Off Off 1 1 Off On Off Off 1 1 Off Off On Off Off Off Off On 1 X = don t care. Rev. B Page 9 of 2

10 AG544 ata Sheet TYPICAL PERFORMANCE CHARACTERISTICS ON RESISTANCE (Ω) T A = 25 C V 1 = +13.5V = 13.5V V = +11V = 11V V = +15V = 15V V = +1V V = +9V = 1V = 9V V = +16.5V = 16.5V ON RESISTANCE (Ω) T A = 25 C V = 36V = V V = 32.4V = V V = 39.6V = V V S, V (V) V S, V (V) Figure 4. RON as a Function of V (VS), ual Supply Figure 7. RON as a Function of V (VS), Single Supply ON RESISTANCE (Ω) V = +18V = 18V V = +2V = 2V V = +22V = 22V ON RESISTANCE (Ω) T A = +125 C T A = +85 C T A = +25 C T A = 4 C 4 2 T A = 25 C V S, V (V) Figure 5. RON as a Function of V (VS), ual Supply V = +15V = 15V V S, V (V) Figure 8. RON as a Function of V (VS) for ifferent Temperatures, ±15 V ual Supply ON RESISTANCE (Ω) T A = 25 C V = +1V = V V = 1.8V V = +9V = V = V V = 12V = V V = 13.2V = V V S, V (V) V = 11V = V Figure 6. RON as a Function of V (VS), Single Supply ON RESISTANCE (Ω) T A = +125 C T A = +85 C T A = +25 C T A = 4 C 2 V = +2V = 2V V S, V (V) Figure 9. RON as a Function of V (VS) for ifferent Temperatures, ±2 V ual Supply Rev. B Page 1 of 2

11 ata Sheet AG544 ON RESISTANCE (Ω) V = 12V = V T A = +125 C T A = +85 C T A = +25 C T A = 4 C LEAKAGE CURRENT (na) V = +2V = 2V V BIAS = +15V/ 15V I, I S (ON) + + I (OFF) + I S (OFF) + I S (OFF) + I, I S (ON) I (OFF) VS, V (V) Figure 1. RON as a Function of V (VS) for ifferent Temperatures, 12 V Single Supply TEMPERATURE ( C) Figure 13. Leakage Currents vs. Temperature, ±2 V ual Supply V = 12V = V V BIAS = 1V/1V I, I S (ON) + + ON RESISTANCE (Ω) T A = +125 C T A = +85 C T A = +25 C T A = 4 C LEAKAGE CURRENT (na).2.2 I (OFF) + I S (OFF) + I S (OFF) + I, I S (ON) 2 V = 36V = V V S, V (V) Figure 11. RON as a Function of V (VS) for ifferent Temperatures, 36 V Single Supply I (OFF) TEMPERATURE ( C) Figure 14. Leakage Currents vs. Temperature, 12 V Single Supply LEAKAGE CURRENT (na) V = +15V = 15V V BIAS = +1V/ 1V I, I S (ON) + + I (OFF) + I S (OFF) + I S (OFF) + I, I S (ON) I (OFF) + LEAKAGE CURRENT (na) V = 36V = V V BIAS = 1V/3V I, I S (ON) + + I S (OFF) + I (OFF) + I S (OFF) + I, I S (ON) I (OFF) TEMPERATURE ( C) Figure 12. Leakage Currents vs. Temperature, ±15 V ual Supply TEMPERATURE ( C) Figure 15. Leakage Currents vs. Temperature, 36 V Single Supply Rev. B Page 11 of 2

12 AG544 ata Sheet 1 T A = 25 C V = +15V = 15V 45 4 T A = 25 C OFF ISOLATION (db) CHARGE INJECTION (pc) V = +2V = 2V V = +15V = 15V V = 12V = V V = 36V = V 1 1k 1k 1k 1M 1M 1M 1G FREQUENCY (Hz) V S (V) Figure 16. Off Isolation vs. Frequency, ±15 V ual Supply Figure 19. Charge Injection vs. Source Voltage CROSSTALK (db) T A = 25 C V = +15V = 15V TIME (ns) V = +12V, = V V = +36V, = V V = +15V, = 15V V = +2V, = 2V 1 1k 1k 1M 1M 1M 1G FREQUENCY (Hz) Figure 17. Crosstalk vs. Frequency, ±15 V ual Supply TEMPERATURE ( C) Figure 2. Transition Time vs. Temperature INSERTION LOSS (db) T A = 25 C V = +15V = 15V ACPSRR (db) TA = 25 C 1 V = +15V = 15V NO ECOUPLING CAPACITORS ECOUPLING CAPACITORS k 1k 1k 1M 1M 1M FREQUENCY (Hz) Figure 18. On Response vs. Frequency, ±15 V ual Supply k 1k 1k 1M 1M FREQUENCY (Hz) Figure 21. ACPSRR vs. Frequency, ±15 V ual Supply Rev. B Page 12 of 2

13 ata Sheet AG LOA = 1kΩ T A = 25 C.8 V = 12V, = V, V S = 6V p-p TH + N (%) V = 36V, = V, V S = 18V p-p.2 V = 15V, = 15V, V S = 15V p-p.1 V = 2V, = 2V, V S = 2V p-p FREQUENCY (MHz) Figure 22. TH + N vs. Frequency, ±15 V ual Supply Rev. B Page 13 of 2

14 AG544 ata Sheet TEST CIRCUITS V.1µF.1µF V NETWORK ANALYZER 5Ω Sx 5Ω V S Sx V GN R L 5Ω I S V S OFF ISOLATION = 2 log V S Figure 23. On Resistance Figure 26. Off Isolation.1µFV.1µF V Sx NETWORK ANALYZER 5Ω V S I S (OFF) A Sx I (OFF) A GN R L 5Ω V S Figure 24. Off Leakage V WITH SWITCH INSERTION LOSS = 2 log WITHOUT SWITCH Figure 27. Bandwidth µFV.1µF NETWORK ANALYZER R L 5Ω V S1 S2 R L 5Ω NC Sx I (ON) A V S GN NC = NO CONNECT V Figure 25. On Leakage CHANNEL-TO-CHANNEL CROSSTALK = 2 log V S Figure 28. Channel-to-Channel Crosstalk Rev. B Page 14 of 2

15 ata Sheet AG544.1µFV.1µF AUIO PRECISION V R S IN Sx V S V p-p V IN GN R L 1kΩ Figure 29. TH + Noise V.1µF.1µF V IN 2.4V V A1 S1 A S2 S3 S4 EN GN R L 3Ω V S1 V S4 C L 35pF ARESS RIVE (V IN ) 3V V 5% 5% 9% 9% t TRANSITION t TRANSITION Figure 3. Address to Output Switching Times V.1µF.1µF V IN 3Ω V A1 A S1 S2 S3 S4 V S1 ARESS RIVE (V IN ) 3V V 2.4V EN GN R L 3Ω C L 35pF 8% 8% t BBM Figure 31. Break-Before-Make Time elay Rev. B Page 15 of 2

16 AG544 ata Sheet V.1µF.1µF V IN 3Ω A1 S1 V S V A S2 S3 S4 EN GN R L 3Ω C L 35pF ENABLE RIVE (V IN ) 3V V OUTPUT V 5% 5%.9.9 t ON (EN) t OFF (EN) Figure 32. Enable-to-Output Switching elay V Δ V Q INJ = C L Δ V S R S Sx ECOER C L 1nF V IN SW OFF SW ON SW OFF GN A1 A2 EN V IN SW OFF SW OFF Figure 33. Charge Injection Rev. B Page 16 of 2

17 ata Sheet AG544 TERMINOLOGY I The positive supply current. ISS The negative supply current. V (VS) The analog voltage on Terminal and Terminal S. RON The ohmic resistance between Terminal and Terminal S. RFLAT(ON) Flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. I (Off) The drain leakage current with the switch off. I, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic. VINH The minimum input voltage for Logic 1. IINL (IINH) The input current of the digital input. CS (Off) The off switch source capacitance, which is measured with reference to ground. C (Off) The off switch drain capacitance, which is measured with reference to ground. C, CS (On) The on switch capacitance, which is measured with reference to ground. CIN The digital input capacitance. ttransition The delay time between the 5% and 9% points of the digital input and switch-on condition when switching from one address state to another. ton (EN) The delay between applying the digital control input and the output switching on. See Figure 32. toff (EN) The delay between applying the digital control input and the output switching off. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3 db. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. TH + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. ACPSRR (AC Power Supply Rejection Ratio) The ratio of the amplitude of signal on the output to the amplitude of the modulation. This is a measure of the part s ability to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of.62 V p-p. Rev. B Page 17 of 2

18 AG544 TRENCH ISOLATION In the AG544, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction-isolated switches, are eliminated, and the result is a completely latch-up proof switch. In junction isolation, the N and P wells of the PMOS and NMOS transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode can become forward-biased. A silicon-controlled rectifier (SCR) type circuit is formed by the two transistors, causing a significant amplification of the current that, in turn, leads to latch-up. With trench isolation, this diode is removed, and the result is a latch-up proof switch. TRENCH NMOS PMOS P-WELL N-WELL BURIE OXIE LAYER HANLE WAFER Figure 34. Trench Isolation ata Sheet Rev. B Page 18 of 2

19 ata Sheet APPLICATIONS INFORMATION The AG54xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, automotive, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. The AG544 high voltage multiplexer allows AG544 single-supply operation from 9 V to 4 V and dual-supply operation from ±9 V to ±22 V. The AG544, as well as three other AG54xx family members, AG5412/AG5413 and AG5436, achieve an 8 kv human body model ES rating that provides a robust solution and eliminates the need for separate protection circuitry designs in some applications. Rev. B Page 19 of 2

20 AG544 ata Sheet OUTLINE IMENSIONS BSC PIN BSC COPLANARITY MAX SEATING PLANE.2.9 COMPLIANT TO JEEC STANARS MO-153-AB-1 Figure Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) imensions shown in millimeters A PIN 1 INICATOR SEATING PLANE SQ 3.9 TOP VIEW.65 BSC BOTTOM VIEW COMPLIANT TO JEEC STANARS MO-22-WGGC. Figure Lead Lead Frame Chip Scale Package [LFCSP] 4 mm 4 mm Body and.75 mm Package Height (CP-16-17) imensions shown in millimeters MAX.2 NOM COPLANARITY.8.2 REF 8 EXPOSE PA PIN 1 INICATOR SQ MIN FOR PROPER CONNECTION OF THE EXPOSE PA, REFER TO THE PIN CONFIGURATION AN FUNCTION ESCRIPTIONS SECTION OF THIS ATA SHEET C ORERING GUIE Model 1 Temperature Range Package escription Package Option AG544BRUZ 4 C to +125 C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 AG544BRUZ-REEL7 4 C to +125 C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 AG544BCPZ-REEL7 4 C to +125 C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP Z = RoHS Compliant Part Analog evices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners /17(B) Rev. B Page 2 of 2

21 Mouser Electronics Authorized istributor Click to View Pricing, Inventory, elivery & Lifecycle Information: Analog evices Inc.: AG544BRUZ AG544BRUZ-REEL7 EVAL-AG544FEBZ EVAL-14TSSOPEBZ