LC2 MOS Precision 5 V/3 V Quad SPST Switches ADG511/ADG512/ADG513

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Derrick Emil Watts
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1 a FEATURE +3 V, +5 V or 5 V Power upplies Ultralow Power issipation (<0.5 W) Low Leakage (<100 pa) Low On Resistance (<50 ) Fast witching Times Low Charge Injection TTL/CMO Compatible 16-Lead IP or OIC Package APPLICATION Battery-Powered Instruments ingle upply ystems Remote Powered Equipment 5 V upply ystems Computer Peripherals such as isk rives Precision Instrumentation Audio and Video witching Automatic Test Equipment Precision ata Acquisition ample Hold ystems Communication ystems Compatible with 5 V upply ACs and ACs such as A7840/A7848, A7870/A7871/A7872/A7874/ A7875/A7876/A7878 GENERAL ECRIPTION The AG511, AG512 and AG513 are monolithic CMO ICs containing four independently selectable analog switches. These switches feature low, well-controlled on resistance and wide analog signal range, making them ideal for precision analog signal switching. These switch arrays are fabricated using Analog evices advanced linear compatible CMO (LC 2 MO) process which offers the additional benefits of low leakage currents, ultralow power dissipation and low capacitance for fast switching speeds with minimum charge injection. These features make the AG511, AG512 and AG513 the optimum choice for a wide variety of signal switching tasks in precision analog signal processing and data acquisition systems. The ability to operate from single +3 V, +5 V or ± 5 V bipolar supplies make the AG511, AG512 and AG513 perfect for use in battery-operated instruments, 4 20 ma loop systems and with the new generation of ACs and ACs from Analog evices. The use of 5 V supplies and reduced operating currents give much lower power dissipation than devices operating from ± 15 V supplies. LC2 MO Precision 5 V/3 V Quad PT witches AG511/AG512/AG513 IN1 IN2 IN3 IN4 AG511 FUNCTIONAL BLOCK IAGRAM IN1 IN2 IN3 IN4 AG IN1 IN2 IN3 IN4 WITCHE HOWN FOR A LOGIC "1" INPUT AG513 The AG511, AG512 and AG513 contain four independent PT switches. The AG511 and AG512 differ only in that the digital control logic is inverted. The AG511 switch is turned on with a logic low on the appropriate control input, while a logic high is required for the AG512. The AG513 contains two switches whose digital control logic is similar to that of the AG511 while the logic is inverted in the remaining two switches. PROUCT HIGHLIGHT 1. 5 Volt ingle upply Operation The AG511/AG512/AG513 offers high performance, including low on resistance and wide signal range, fully specified and guaranteed with +3 V, ± 5 V as well as +5 V supply rails. 2. Ultralow Power issipation CMO construction ensures ultralow power dissipation. 3. Low R ON 4. Break-Before-Make witching witches are guaranteed to have break-before-make operation. This allows multiple outputs to be tied together for multiplexer applications without the possibility of momentary shorting between channels Information furnished by Analog evices is believed to be accurate and reliable. However, no responsibility is assumed by Analog evices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog evices. One Technology Way, P.O. Box 9106, Norwood, MA , U..A. Tel: 781/ Fax: 781/ Analog evices, Inc., 2001

2 AG511/AG512/AG513 PECIFICATION 1 ual upply ( = +5 V 10%, = 5 V 10%, GN = 0 V, unless otherwise noted) B Versions T Version 40 C to 55 C to Parameter 25 C +85 C 25 C +125 C Unit Test Conditions/Comments ANALOG WITCH Analog ignal Range to to V R ON Ω typ V = ±3.5 V, I = 10 ma; Ω max = +4.5 V, = 4.5 V LEAKAGE CURRENT = +5.5 V, = 5.5 V ource OFF Leakage I (OFF) ± ± na typ V = ±4.5 V, V = 4.5 V; ± 0.1 ± 2.5 ± 0.1 ± 2.5 na max Test Circuit 2 rain OFF Leakage I (OFF) ± ± na typ V = ±4.5 V, V = 4.5 V; ± 0.1 ± 2.5 ± 0.1 ± 2.5 na max Test Circuit 2 Channel ON Leakage I, I (ON) ± 0.05 ± 0.05 na typ V = V = ±4.5 V; ± 0.2 ± 5 ± 0.2 ± 5 na max Test Circuit 3 IGITAL INPUT Input High Voltage, H V min Input Low Voltage, L V max Input Current I INL or I INH µa typ = L or H ± 0.1 ± 0.1 µa max YNAMIC CHARACTERITIC 2 t ON ns typ R L = 300 Ω. C L = 35 pf; ns max V = ±3 V; Test Circuit 4 t OFF ns typ R L = 300 Ω. C L = 35 pf; ns max V = ±3 V; Test Circuit 4 Break-Before-Make Time ns typ R L = 300 Ω, C L = 35 pf; elay, t (AG513 Only) V 1 = V 2 = 3 V; Test Circuit 5 Charge Injection pc typ V = 0 V, R = 0 Ω, C L = 10 nf; Test Circuit 6 OFF Isolation db typ R L = 50 Ω, C L = 5 pf, f = 1 MHz; Test Circuit 7 Channel-to-Channel Crosstalk db typ R L = 50 Ω, C L = 5 pf, f = 1 MHz; Test Circuit 8 C (OFF) 9 9 pf typ f = 1 MHz C (OFF) 9 9 pf typ f = 1 MHz C, C (ON) pf typ f = 1 MHz POWER REQUIREMENT +4.5/ /5.5 V min/max 4.5/ / 5.5 V min/max I µa typ = +5.5 V, = 5.5 V 1 1 µa max igital Inputs = 0 V or 5 V I µa typ 1 1 µa max NOTE 1 Temperature ranges are as follows: B Versions 40 C to +85 C; T Version 55 C to +125 C. 2 Guaranteed by design, not subject to production test. pecifications subject to change without notice. 2

3 ingle upply ( = 5 V 10%, = 0 V, GN = 0 V, unless otherwise noted) B Versions T Version 40 C to 55 C to Parameter 25 C +85 C 25 C +125 C Unit Test Conditions/Comments ANALOG WITCH Analog ignal Range 0 V to 0 V to V R ON Ω typ V = 3.5 V, I = 10 ma; Ω max = 4.5 V LEAKAGE CURRENT = 5.5 V ource OFF Leakage I (OFF) ±0.025 ±0.025 na typ V = 4.5/1 V, V = V; ±0.1 ±2.5 ±0.1 ±2.5 na max Test Circuit 2 rain OFF Leakage I (OFF) ±0.025 ±0.025 na typ V = 4.5/1 V, V = V; ±0.1 ±2.5 ±0.1 ±2.5 na max Test Circuit 2 Channel ON Leakage I, I (ON) ±0.05 ±0.05 na typ V = V = 4.5 V/1 V; ±0.2 ±5 ±0.2 ±5 na max Test Circuit 3 IGITAL INPUT Input High Voltage, H V min Input Low Voltage, L V max Input Current I INL or I INH µa typ = L or H ±0.1 ±0.1 µa max YNAMIC CHARACTERITIC 2 t ON ns typ R L = 300 Ω, C L = 35 pf; ns max V = 2 V; Test Circuit 4 t OFF ns typ R L = 300 Ω, C L = 35 pf; ns max V = 2 V; Test Circuit 4 Break-Before-Make Time ns typ R L = 300 Ω, C L = 35 pf; elay, t (AG513 Only) V 1 = V 2 = 2 V; Test Circuit 5 Charge Injection pc typ V = 0 V, R = 0 Ω, C L = 10 nf; Test Circuit 6 OFF Isolation db typ R L = 50 Ω, C L = 5 pf, f = 1 MHz; Test Circuit 7 Channel-to-Channel Crosstalk db typ R L = 50 Ω, C L = 5 pf, f = 1 MHz; Test Circuit 8 C (OFF) 9 9 pf typ f = 1 MHz C (OFF) 9 9 pf typ f = 1 MHz C, C (ON) pf typ f = 1 MHz POWER REQUIREMENT 4.5/ /5.5 V min/max I µa typ = 5.5 V 1 1 µa max igital Inputs = 0 V or 5 V NOTE 1 Temperature ranges are as follows: B Versions 40 C to +85 C; T Version 55 C to +125 C. 2 Guaranteed by design, not subject to production test. pecifications subject to change without notice. AG511/AG512/AG513 3

4 AG511/AG512/AG513 PECIFICATION 1 ingle upply ( = 3.3 V 10%, = 0 V, GN = 0 V, unless otherwise noted) B Version 0 C to Parameter 25 C 70 C Unit Test Conditions/Comments ANALOG WITCH Analog ignal Range 0 V to V R ON 200 Ω typ V = 1.5 V, I = 1 ma; 500 Ω max = 3 V LEAKAGE CURRENT = 3.6 V ource OFF Leakage I (OFF) ± na typ V = 2.6/1 V, V = V; ± 0.1 ± 2.5 na max Test Circuit 2 rain OFF Leakage I (OFF) ± na typ V = 2.6/1 V, V = V; ± 0.1 ± 2.5 na max Test Circuit 2 Channel ON Leakage I, I (ON) ± 0.05 na typ V = V = 2.6 V/1 V; ± 0.2 ± 5 na max Test Circuit 3 IGITAL INPUT Input High Voltage, H 2.4 V min Input Low Voltage, L 0.8 V max Input Current I INL or I INH µa typ = L or H ± 0.1 µa max YNAMIC CHARACTERITIC 2 t ON 600 ns typ R L = 300 Ω, C L = 35 pf; 1200 ns max V = 1 V; Test Circuit 4 t OFF 100 ns typ R L = 300 Ω, C L = 35 pf; 160 ns max V = 1 V; Test Circuit 4 Break-Before-Make Time 500 ns typ R L = 300 Ω, C L = 35 pf; elay, t (AG513 Only) V 1 = V 2 = 1 V; Test Circuit 5 Charge Injection 11 pc typ V = 0 V, R = 0 Ω, C L = 10 nf; Test Circuit 6 OFF Isolation 68 db typ R L = 50 Ω, C L = 5 pf, f = 1 MHz; Test Circuit 7 Channel-to-Channel Crosstalk 85 db typ R L = 50 Ω, C L = 5 pf, f = 1 MHz; Test Circuit 8 C (OFF) 9 pf typ f = 1 MHz C (OFF) 9 pf typ f = 1 MHz C, C (ON) 35 pf typ f = 1 MHz POWER REQUIREMENT 3/3.6 V min/max I µa typ = 3.6 V 1 µa max igital Inputs = 0 V or 3 V NOTE 1 Temperature range is as follows: B Version 40 C to +85 C. 2 Guaranteed by design, not subject to production test. pecifications subject to change without notice. 4

5 AG511/AG512/AG513 ABOLUTE MAXIMUM RATING 1 (T A = +25 C unless otherwise noted) to V to GN V to +25 V to GN V to 25 V Analog, igital Inputs V to + 2 V or 30 ma, Whichever Occurs First Continuous Current, or ma Peak Current, or ma (Pulsed at 1 ms, 10% uty Cycle max) Operating Temperature Range Industrial (B Version) C to +85 C Extended (T Version) C to +125 C torage Temperature Range C to +150 C Junction Temperature C Cerdip Package, Power issipation mw θ JA Thermal Impedance C/W Lead Temperature, oldering (10 sec) C Plastic Package, Power issipation mw θ JA Thermal Impedance C/W Lead Temperature, oldering (10 sec) C OIC Package, Power issipation mw θ JA Thermal Impedance C/W Lead Temperature, oldering Vapor Phase (60 sec) C Infrared (15 sec) C NOTE 1 tresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at IN, or will be clamped by internal diodes. Current should be limited to the maximum ratings given. CAUTION E (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AG511/AG512/AG513 features proprietary E protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper E precautions are recommended to avoid performance degradation or loss of functionality. WARNING! E ENITIVE EVICE ORERING GUIE Model 1 Temperature Range 2 Package Option 3 AG511BN 40 C to +85 C N-16 AG511BR 40 C to +85 C R-16A AG511ABR 4 40 C to +85 C R-16A AG511TQ 4 55 C to +125 C Q-16 AG512BN 40 C to +85 C N-16 AG512BR 40 C to +85 C R-16A AG512ABR 4 40 C to +85 C R-16A AG513BN 40 C to +85 C N-16 AG513BR 40 C to +85 C R-16A AG513ABR 4 40 C to +85 C R-16A NOTE 1 For availability of MIL-T-883, Class B processed parts, contact factory V specifications apply over 0 C to 70 C temperature range. 3 N = Plastic IP; R = 0.15" mall Outline IC (OIC); Q = Cerdip. 4 Trench isolated latch-up proof parts. ee Trench Isolation section. 5

6 AG511/AG512/AG513 PIN CONFIGURATION (IP/OIC) IN IN AG511 AG512 AG GN 4 4 IN TOP VIEW 12 (Not to cale) NC 3 3 IN3 NC = NO CONNECT Truth Table (AG511/AG512) AG511 AG512 witch In In Condition 0 1 ON 1 0 OFF Truth Table (AG513) witch witch Logic 1, 4 2, 3 0 OFF ON 1 ON OFF TERMINOLOGY Most Positive Power upply Potential. Most Negative Power upply Potential in dual supplies. In single supply applications, it may be connected to GN. GN Ground (0 V) Reference. ource Terminal. May be an input or output. rain Terminal. May be an input or output. IN Logic Control Input. R ON Ohmic Resistance between and. I (OFF) ource Leakage Current with the switch OFF. I (OFF) rain Leakage Current with the switch OFF. I, I (ON) Channel Leakage Current with the switch ON. V (V ) Analog Voltage on terminals,. C (OFF) OFF witch ource Capacitance. C (OFF) OFF witch rain Capacitance. C, C (ON) ON witch Capacitance. t ON elay between applying the digital control input and the output switching on. t OFF elay between applying the digital control input and the output switching off. t OFF or ON time measured between the 90% points of both switches when switching from one address state to another. Crosstalk A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. Off Isolation A measure of unwanted signal coupling through an OFF switch. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. 6

7 Typical Performance Characteristics AG511/AG512/AG T A = 25 C 10mA 1mA = +5V = 5V R ON = +3V = 3V = +5V = 5V I UPPLY 100 A 10 A 1 A 100nA I, I+ 1 W 4 W V OR V RAIN OR OURCE VOLTAGE V TPC 1. On Resistance as a Function of V (V ) ual upplies 10nA k 10k 100k 1M 10M FREQUENCY Hz TPC 4. upply Current vs. Input witching Frequency R ON = +5V = 5V 125 C 85 C 25 C LEAKAGE CURRENT na = +5V = 5V V = 5V V = 5V I (OFF) I (ON) I (OFF) V OR V RAIN OR OURCE VOLTAGE V TPC 2. On Resistance as a Function of V (V ) for ifferent Temperatures TEMPERATURE C TPC 5. Leakage Currents as a Function of Temperature R ON T A = 25 C = 5V = 0V = 3V = 0V OFF IOLATION db = +5V = 5V V OR V RAIN OR OURCE VOLTAGE V TPC 3. On Resistance as a Function of V (V ) ingle upply k 10k 100k 1M 10M FREQUENCY Hz TPC 6. Off Isolation vs. Frequency 7

8 AG511/AG512/AG513 LEAKAGE CURRENT na = +5V = 5V T A = +25 C I (ON) I (OFF) I (OFF) V OR V RAIN OR OURCE VOLTAGE V TPC 7. Leakage Currents as a Function of V (V ) network R C and C C. This compensation network also reduces the hold time glitch while optimizing the acquisition time. Using the illustrated op amps and component values, the pedestal error has a maximum value of 5 mv over the ± 3 V input range. The acquisition time is 2.5 µs while the settling time is 1.85 µs. +5V A845 5V W2 W1 +5V AG511/ AG512/ AG513 R C pF C C 1000pF C H 2200pF +5V OP07 5V 5V CROTALK db = +5V = 5V k 10k 100k 1M 10M FREQUENCY Hz TPC 8. Crosstalk vs. Frequency APPLICATION Figure 1 illustrates a precise sample-and-hold circuit. An A845 is used as the input buffer while the output operational amplifier is an OP07. uring the track mode, W1 is closed and the output follows the input signal. In the hold mode, W1 is opened and the signal is held by the hold capacitor C H. ue to switch and capacitor leakage, the voltage on the hold capacitor will decrease with time. The AG511/AG512/ AG513 minimizes this droop due to its low leakage specifications. The droop rate is further minimized by the use of a polystyrene hold capacitor. The droop rate for the circuit shown is typically 15 µv/µs. A second switch, W2, which operates in parallel with W1, is included in this circuit to reduce pedestal error. ince both switches will be at the same potential, they will have a differential effect on the op amp OP07, which will minimize charge injection effects. Pedestal error is also reduced by the compensation Figure 1. Accurate ample-and-hold TRENCH IOLATION The MO devices that make up the AG511A/AG512A/ AG513A are isolated from each other by an oxide layer (trench) (see Figure 2). When the NMO and PMO devices are not electrically isolated from each other, there exists the possibility of latch-up caused by parasitic junctions between CMO transistors. Latch-up is caused when P-N junctions that are normally reverse biased, become forward biased, causing large currents to flow. This can be destructive. CMO devices are normally isolated from each other by Junction Isolation. In Junction Isolation the N and P wells of the CMO transistors form a diode that is reverse biased under normal operation. However, during overvoltage conditions, this diode becomes forward biased. A ilicon-controlled Rectifier (CR)- type circuit is formed by the two transistors, causing a significant amplification of the current that, in turn, leads to latch-up. With Trench Isolation, this diode is removed; the result is a latch-up-proof circuit. T R E N C H V G V G V V V V P + P-CHANNEL P + T N R + N-CHANNEL N + E N C N H P BURIE OXIE LAYER UBTRATE (BACKGATE) Figure 2. Trench Isolation T R E N C H 8

9 AG511/AG512/AG513 Test Circuits I V1 I (OFF) A I (OFF) A I (ON) A V V V V V R ON = V1/I Test Circuit 1. On Resistance Test Circuit 2. Off Leakage Test Circuit 3. On Leakage 3V AG511 50% 50% 3V V IN R L 300 C L 35pF AG512 50% 50% 90% 90% GN t ON t OFF Test Circuit 4. witching Times 3V V 1 V R L1 300 C L1 35pF 1 1 0V 0V 50% 50% 90% 90% IN1, IN2 R L2 300 C L2 35pF GN 2 0V 90% 90% t t Test Circuit 5. Break-Before-Make Time elay 3V R V IN C L 10nF GN Q INJ = C L Test Circuit 6. Charge Injection 9

10 AG511/AG512/AG V IN GN R L 50 V R L 50 1 GN 2 NC CHANNEL-TO-CHANNEL CROTALK = 20 LOG V / Test Circuit 7. Off Isolation Test Circuit 8. Channel-to-Channel Crosstalk 10

11 AG511/AG512/AG513 OUTLINE IMENION imensions shown in inches and (mm). 16-Lead Plastic IP (N-16) (21.34) (18.92) (4.06) (2.93) (0.558) (0.356) (7.11) (6.10) PIN (1.52) (5.33) (0.38) MAX (2.54) BC (3.30) MIN (1.77) EATING (1.15) PLANE (8.26) (7.62) (4.95) (2.93) (0.381) (0.204) 16-Lead Cerdip (Q-16) (0.13) MIN (2.03) MAX (5.08) MAX (5.08) (3.18) (0.58) (0.36) 1 8 PIN (21.34) MAX (2.54) BC (7.87) (5.59) (1.52) (0.38) (3.81) MIN EATING (1.78) PLANE (0.76) (8.13) (7.37) (0.38) (0.20) 16-Lead OIC (R-16A) (10.00) (9.80) (4.00) (3.80) (6.20) (5.80) (0.25) (0.10) PIN (1.75) (1.35) (0.50) (0.25) x 45 EATING PLANE (1.27) BC (0.49) (0.35) (0.25) (0.19) (1.27) (0.41) 11

12 AG511/AG512/AG513 Revision History Location Page ata heet changed from REV. B to. Changes to pecifications table, ual upply, and Notes: T Versions made singular Changes to pecifications table, ingle upply, and Notes: T Versions made singular Change to Ordering Guide: Removed one line PRINTE IN U..A. C00036b 0 5/01(C) 12

LC 2 MOS Precision 5 V Quad SPST Switches ADG661/ADG662/ADG663

LC 2 MOS Precision 5 V Quad SPST Switches ADG661/ADG662/ADG663 a FEATURE +5 V, 5 V Power upplies Ultralow Power issipation (