8-Ch/Dual 4-Ch High-Performance CMOS Analog Multiplexers

Transcription

1 8-Ch/ual 4-Ch High-Performance CMOS Analog Multiplexers ESCRIPTION The G48 is an 8-channel single-ended analog multiplexer designed to connect one of eight inputs to a common output as determined by a 3-bit binary address (,, ). The G49 is a dual 4-channel differential analog multiplexer designed to connect one of four differential inputs to a common dual output as determined by its 2-bit binary address (, ). Break-before-make switching action protects against momentary crosstalk between adjacent channels. An on channel conducts current equally well in both directions. In the off state each channel blocks voltages up to the power supply rails. An enable () function allows the user to reset the multiplexer/demultiplexer to all switches off for stacking several devices. All control inputs, address (A x ) and enable () are TTL compatible over the full specified operating temperature range. Applications for the G48/49 include high speed data acquisition, audio signal switching and routing, ATE systems, and avionics. High performance and low power dissipation make them ideal for battery operated and remote instrumentation applications. esigned in the 44 V silicon-gate CMOS process, the absolute maximum voltage rating is extended to 44 V. Additionally, single supply operation is also allowed. An epitaxial layer prevents latchup. For additional information please see Technical Article TA21 (FaxBack Number 76). FEATURES Low On-Resistance - r S(on) : 1 Ω Low Charge Injection - Q: 2 pc Fast Transition Time - t TRANS : 16 ns Low Power - I SUPPLY : 1 µa Single Supply Capability 44 V Supply Max Rating TTL Compatible Logic BEFITS Reduced Switching Errors Reduced Glitching Improved ata Throughput Reduced Power Consumption Increased Ruggedness Wide Supply Ranges (± 5 V to ± 2 V) APPLICATIONS ata Acquisition Systems Audio Signal Routing ATE Systems Battery Powered Systems High Rel Systems Single Supply Systems Medical Instrumentation Pb-free Available RoHS* COMPLIANT FUNCTIONAL BLOCK IAGRAM AN PIN CONFIGURATION G48 ual-in-line SOIC and TSSOP G49 ual-in-line SOIC and TSSOP ecoders/rivers 15 2 ecoders/rivers 15 GN V- GN 3 14 V a 4 13 b S 2 S S 2a 5 12 S 2b S S 6 S 3a 6 11 S 3b S S 7 S 4a 7 1 S 4b 8 9 S 8 a 8 9 b Top View Top View * Pb containing terminations are not RoHS compliant, exemptions may apply S Rev. G, 11-Jun-7 1

2 TRUTH TABLES AN ORERING INFORMATION TRUTH TABLE - G48 On Switch X X X None TRUTH TABLE - G49 On Switch X X None Logic "" = V AL.8 V Logic "1" = V AH 2.4 V X = on t Care ORERING INFORMATION - G48 Temp Range Package Part Number ORERING INFORMATION - G49 Temp Range Package Part Number 16-Pin Plastic IP G48J G48J-E3 16-Pin Plastic IP G49J G49J-E3-4 to 85 C 16-Pin SOIC G48Y G48Y-E3 G48Y-T1 G48Y-T1-E3-4 to 85 C 16-Pin SOIC G49Y G49Y-E3 G49Y-T1 G49Y-T1-E3 16-Pin TSSOP G48Q G48Q-E3 G48Q-T1 G48Q-T1-E3 16-Pin TSSOP G49Q G49Q-E3 G49Q-T1 G49Q-T1-E3 ABSOLUTE MAXIMUM RATINGS Parameter Limit Unit 44 Voltages Referenced to V- GN 25 igital Inputs a (V-) - 2 to () + 2, V S, V or 2 ma, whichever occurs first Current (Any Terminal) 3 Peak Current, S or (Pulsed at 1 ms, 1 % duty cycle max) 1 Storage Temperature Power issipation (Package) b (AK Suffix) - 65 to 15 (J, Y Suffix) - 65 to Pin Plastic IP c Pin Narrow SOIC and TSSOP d 6 16-Pin CerIP e 9 LCC-2 f 75 Notes: a. Signals on S X, X or IN X exceeding or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads soldered or welded to PC board. c. erate 6 mw/ C above 75 C. d. erate 7.6 mw/ C above 75 C. e. erate 12 mw/ C above 75 C. f. erate 1 mw/ C above 75 C. V ma C mw 2 S Rev. G, 11-Jun-7

3 SPECIFICATIONS a Parameter Symbol Test Conditions Unless Otherwise Specified = 15 V, V- = V AL =.8 V, V AH = 2.4 V f Temp b Typ c A Suffix - 55 to 125 C Suffix - 4 to 85 C Min d Max d Min d Max d Analog Switch Analog Signal Range e V ANALOG V rain-source Room r On-Resistance S(on) V = ± 1 V, I S = - 1 ma Ω r S(on) Matching Between Channels g Δr S(on) V = ± 1 V Room % Source Off Leakage Current I S(off) V S = ± 1 V V = ± 1 V, V = V V = ± 1 V Room G rain Off Leakage Current I (off) V S = ± 1 V Room V = V G49 na rain On Leakage Current I (on) Room V S = V = ± 1 G Sequence Each Room Switch On G igital Control Logic High Input Voltage V INH Logic Low Input Voltage V INL.8.8 V Logic High Input Current I AH V A = 2.4 V, 15 V Logic Low Input Current I AL V = V, 2.4 V, V A = V µa Logic Input Capacitance C in f = 1 MHz Room 8 pf ynamic Characteristics Transition Time t TRANS See Figure Break-Before-Make Interval t OP See Figure 4 Room 1 1 Enable Turn-On Time t ON() Room ns See Figure Enable Turn-Off Time t OFF() Room Charge Injection Q C L = 1 nf, V S = V Room 2 pc Off Isolation h OIRR V = V, R L = 1 kω f = 1 khz Room - 75 db Source Off Capacitance C S(off) V = V, V S = V, f = 1 MHz Room 3 G48 Room 26 rain Off Capacitance C (off) V = V G49 Room 14 pf V = V G48 Room 37 rain On Capacitance C (on) f = 1 MHz G49 Room 25 Power Supplies Positive Supply Current I V = V A = V or 5 V µa Negative Supply Current I Room Positive Supply Current I+ ma V = 2.4 V, V A = V 2 2 Negative Supply Current I µa Room Unit S Rev. G, 11-Jun-7 3

4 SPECIFICATIONS a FOR SINGLE SUPPLY Test Conditions Unless Otherwise Specified = 12 V, V- = V A Suffix - 55 to 125 C Suffix - 4 to 85 C Parameter Symbol V AL =.8 V, V AH = 2.4 V f Temp b Typ c Min d Max d Min d Max d Unit Analog Switch rain-source On-Resistance e,f r S(on) V = 3 V, 1 V, I S = - 1 ma Room 9 Ω ynamic Characteristics Switching Time of Multiplexer e t TRANS V S1 = 8 V, V S8 = V, V IN = 2.4 V Room 18 Enable Turn-On Time e t ON() V INH = 2.4 V, V INL = V Room 18 ns Enable Turn-Off Time e t OFF() V S1 = 5 V Room 12 Charge Injection e Q C L = 1 nf, V S = 6 V, R S = Room 5 pc Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25 C, = as determined by the operating temperature suffix. c. Typical values are for ESIGN AI ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. V IN = input voltage to perform proper function. g. Δr S(on) = r S(on) MAX - r S(on) MIN. h. Worst case isolation occurs on Channel 4 due to proximity to the drain pin. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 4 S Rev. G, 11-Jun-7

5 TYPICAL CHARACTERISTICS 25 C, unless otherwise noted 8 6 = 15 V V- = C (on) V S = V for I (off) V S = V for I (on) G49 I (off) G48 I (off) CS, (pf) 4 C (off) (pa) I G49 I (on) C S(off) - 4 G48 I (on) V ANALOG Analog Voltage (V) Source/rain Capacitance vs. Analog Voltage V ANALOG Analog V oltage (V) rain Leakage Current vs. Source/rain Voltage (Single 12-V Supply) = 15 V V- = V S = -V for I (off) V = V S(open) for I (on) G49 I (off) 1 = 15 V V- = (pa) I G49 I (on) I S(off) (pa) 5-1 G48 I (on), I (off) - 5 = 12 V V- = V V or V S - rain or Source Voltage (V) rain Leakage Current vs. Source/rainVoltage V S - Source Voltage (V) Source Leakage Current vs. Source Voltage ma V SU PPL Y = ± 15 V - 1 ma ma V TH (V) 1. I- - 1 µa V = 2.4 V - 1 µa.5-1 µa V = V or 5 V V SUPPLY (V) Input Switching Threshold vs. Supply Voltage -.1 µa 1 1 k 1 k 1 k 1 M 1 M Switching Frequency (Hz) Negative Supply Current vs. Switching Frequency S Rev. G, 11-Jun-7 5

6 TYPICAL CHARACTERISTICS 25 C, unless otherwise noted 1 ma V SUPPLY = 15 V 1 µa 1 µa I+ 1 ma 1 µa I+ 1 ma V = 2.4 V I+, I- 1 na 1 na 1 µa V = V or 5 V 1 na 1 pa - (I-) V SU PPL Y = ± 15 V V A = V V = V 1 µa 1 1 k 1 k 1 k 1 M 1 M Switching Frequency (Hz) Positive Supply Current vs. Switching Frequency 1 pa Temperature ( C) I SUPPLY vs. Temperature C L = 1 pf V IN = 5 Vp-p I+ (µa) = 15 V V- = V IN = V V = V Q (pc) = 15 V V- = = 12 V V- = V Temperature ( C) Positive Supply Current vs. Temperature (G48) V S - Source Voltage (V) Charge Injection vs. Analog Voltage ± 5 V = 7.5 V V r S(on) (Ω) ± 2 V ± 15 V ± 8 V ± 1 V ± 12 V r S(on) (Ω) V- = V 12 V 15 V 2 V 22 V V - rain V oltage (V) r S(on) vs. V and Supply V - rain Voltage (V) r S(on) vs. V and Supply (Single Supply) 6 S Rev. G, 11-Jun-7

7 TYPICAL CHARACTERISTICS 25 C, unless otherwise noted 8 13 r S(on) (Ω) = 15 V V- = 125 C 85 C 25 C r S(on) (Ω) C 85 C 25 C C - 4 C 2 1 C - 4 C - 55 C 3-55 C = 12 V V- = V V S - Source V oltage (V) r S(on) vs. V S and Temperature V S - Source V oltage (V) r S(on) vs. V S and Temperature (Single Supply) (db) Off-Isolation = 15 V V- = R L = 1 kω LOSS (db) = 15 V V- = Ref. 1 Vrms R L = 1 kω Crosstalk R L = 5 Ω k 1 k 1 k 1 M 1 M f - Frequency (Hz) Off Isolation and Crosstalk vs. Frequency 1 M k 1 k 1 k 1 M 1 M 1 M f - Frequency (Hz) Insertion Loss vs. Frequency t TRANS t (ns) 15 t (ns) 2 t TRANS t OFF() 15 t OFF() 1 t ON() 125 t ON() 75 ± 1 ± 12 ± 14 ± 16 ± 18 ± 2 ± V SUPPLY (V) Switching Time vs. Bipolar Supply) V SUPPLY (V) Switching Time vs. Single Supply S Rev. G, 11-Jun-7 7

8 SCHEMATIC IAGRAM (TYPICAL CHANNEL) GN V REF A X Level Shift ecode/ rive V- S n V- Figure 1. TEST CIRCUITS ± 1 V GN G48 S 2 - S 7 S 8 V- 5 Ω 3 Ω ± 1 V 35 pf Logic Input 3 V V 5 % t r < 2 ns t f < 2 ns a - S 4a, a ± 1 V Switch Output V S1 V V S8 9 % 9 % G49 S 4b b GN V- 5 Ω 3 Ω ± 1 V 35 pf t TRANS ON S 8 ON t TRANS Figure 2. Transition Time 8 S Rev. G, 11-Jun-7

9 TEST CIRCUITS - 5 V 5 Ω A G48 GN V- S 2 - S 8 1 kω 35 pf Logic Input Switch Output 3 V V t ON() V 5 % t r < 2 ns t f < 2 ns t OFF() 1 % b - 5 V 9 % a - S 4a, a S 2b - S 4b 5 Ω G49 GN V- b 1 kω 35 pf Figure 3. Enable Switching Time V 5 Ω G48 G49 All S and a GN V- b, 3 Ω + 5 V 35 pf Logic Input Switch Output 3 V V V S V 5 % 8 % t OP t r < 2 ns t f < 2 ns Figure 4. Break-Before-Make Interval S Rev. G, 11-Jun-7 9

10 TEST CIRCUITS R g S X Logic Input 3 V V OFF ON OFF Channel Select GN V- C L 1 nf Switch Output Δ is the measured voltage due to charge transfer error Q, when the channel turns off. Q = C L x Δ Δ Figure 5. Charge Injection V S V IN S X V S V IN S X R g = 5 Ω S 8 R g = 5 Ω S 8 GN V- R L 1 kω GN V- R L 1 kω Off Isolation = 2 log UT V IN Crosstalk = 2 log UT V IN Figure 6. Off Isolation Figure 7. Crosstalk V S R g = 5 Ω GN V- R L 1 kω Channel Select A1 GN S 8 V- Meter HP4192A Impedance Analyzer or Equivalent f = 1 MHz Insertion Loss = 2 log UT V IN Figure 8. Insertion Loss Figure 9. Source rain Capacitance 1 S Rev. G, 11-Jun-7

11 APPLICATIONS HINTS Overvoltage Protection A very convenient form of overvoltage protection consists of adding two small signal diodes (1N4148, 1N914 type) in series with the supply pins (see Figure 1). This arrangement effectively blocks the flow of reverse currents. It also floats the supply pin above or below the normal or V- value. In this case the overvoltage signal actually becomes the power supply of the IC. From the point of view of the chip, nothing has changed, as long as the difference VS - (V-) doesn t exceed + 44 V. The addition of these diodes will reduce the analog signal range to 1 V below and 1 V above V-, but it preserves the low channel resistance and low leakage characteristics. 1N4148 V g S X G48 1N4148 Figure 1. Overvoltage Protection Using Blocking iodes V- 8-Channel Sequential Multiplexer/emultiplexer ifferential 4-Channel Sequential Multiplexer/emultiplexer Analog Inputs (Outputs) GN V- S 2 S 3 S 4 G48 S 5 S 6 S 7 S 8 Analog Output (Input) ifferential Analog Inputs (Outputs) GN V- a S 2a S 3a a S 4a G49 b S 2b b S 3b S 4b ifferential Analog Outputs (Inputs) Clock In NC Enable In M7493 B IN (MUX On-Off Control) Q B Q C Q J Q J Q A IN Q NC Clock 1/2 MM74C73 1/2 MM74C73 A r 1 r 2 GN In CLK CLK K Q NC K Q CLEAR GN CLEAR Reset Enable Figure NC maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see S Rev. G, 11-Jun-7 11

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