0.3 pc Charge Injection, 100 pa Leakage CMOS ± 5 V / 5 V / 3 V Dual SPDT Analog Switch

Transcription

1 0.3 pc Charge Injection, pa Leakage CMOS ± 5 / 5 / 3 Dual SPDT Analog Switch DESCRIPTION The is a dual SPDT CMOS, analog switch, designed to operate from a +3 to +16 single supply, or from ± 3 to ± 8, dual supplies. The is fully specified at +3, +5, and ± 5. The offers ultralow charge injection less than ± 0.4 pc over the entire signal range and s of 13 pa typical at 25 C. It offers on resistance of 63 typ., and low parasitic capacitance of 3.7 pf source off, and 8.4 pf Drain on. The part is ideal for analog front end, data acquisition and sample and hold designs providing fast and precision signal switching. The switches one of two inputs to a common output as determined by the 3-bit binary address lines:,, and EN. Each switch conducts equally well in both directions when on, blocks input voltages up to the supply level when off, and exhibits break before make switching action. All control logic inputs have guaranteed 2 logic high limits when operating from +5 or ± 5 supplies and 1.4 when operating from a 3 supply. The operating temperature range is specified from -40 C to +125 C. It is available in 14 lead TSSOP and the space saving 1.8 mm x 2.6 mm miniqfn package. FEATURES Ultra low charge injection (Less than ± 0.3 pc, typ. over the full analog signal range) Leakage current < 0.5 na max. at 85 C (for EQ-T1-GE4) Low switch capacitance (C S(off), 3.7 pf typ.) Fully specified with single supply operation at 3, 5, and dual supplies at ± 5 CMOS / TTL compatible 700 MHz, -3 db bandwidth Excellent isolation and crosstalk performance (typ. > -60 db at MHz) Fully specified from -40 C to +85 C and -40 C to +125 C 14 pin TSSOP and 16 pin miniqfn package (1.8 mm x 2.6 mm) Material categorization: for definitions of compliance please see APPLICATIONS Data acquisition systems Medical instruments Precision instruments Communications systems Automated test equipment Sample and hold circuit Relay replacement FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION mqfn-16 NC NC TSSOP Logic 12 2 Logic Yxx S1A 3 S2A S1A 4 11 S2A S1B 4 9 S2B S1B 5 S2B Pin 1 Device Marking: Yxx for (miniqfn16) xx = Date/Lot Traceability Code D1 NC NC D2 Top iew D1 NC 6 7 Top iew 9 8 D2 NC = Hi, all switches are controlled by addr pins. = Lo, all switches are off. S Rev. B, 09-Oct-17 1 Document Number: ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

2 TRUTH TABLE SELECTED INPUT ON SWITCHES INPUT L X X All Switches Open H L L D1 to S1A, D2 to S2A H L H D1 to S1B, D2 to S2A H H L D1 to S1A, D2 to S2B H H H D1 to S1B, D2 to S2B ORDERING INFORMATION TEMP. RANGE PACKAGE PART NUMBER -40 C to +125 C a 14 pin TSSOP EQ-T1-GE4 16 pin miniqfn EN-T1-GE4 Note a. -40 C to +85 C datasheet limits apply. ABSOLUTE MAXIMUM RATINGS (T A = 25 C, unless otherwise noted) PARAMETER LIMIT UNIT to -0.3 to +18 to 18 S, D () -0.3 to () or 30 ma, whichever occurs first Digital inputs a () -0.3 to () Continuous current (any terminal) 30 Peak current, S or D (pulsed 1 ms, % duty cycle) ma Storage temperature -65 to +150 C Power dissipation (package) b 14 pin TSSOP c pin miniqfn d, e 525 mw Thermal resistance (package) b 14 pin TSSOP pin miniqfn 152 C/W ESED / HBM EIA / JESD22-14-A 2K ESD / CDM EIA / JESD22-C1-A 1K Latch up JESD ma Notes a. Signals on S X, D X, or IN X exceeding or will be clamped by internal diodes. Limit forward diode current to maximum current ratings b. All leads welded or soldered to PC board c. Derate 5.6 mw/ C above 70 C d. Derate 6.6 mw/ C above 70 C e. Manual soldering with iron is not recommended for leadless components. The miniqfn-16 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper lip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection S Rev. B, 09-Oct-17 2 Document Number: ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

3 SPECIFICATIONS FOR DUAL SUPPLIES ( = 5, = -5 ) PARAMETER SYMBOL TEST CONDITIONS UNLESS OTHERWISE SPECIFIED = 5, = -5 IN,, AND = 2, 0.8 a TEMP. b TYP. c -40 C to +125 C -40 C to +85 C MIN. d MAX. d MIN. d MAX. d Analog Switch Analog signal range e ANALOG Full Drain-source Room R On-resistance DS(on) I S = 1 ma, D = -3, 0, +3 Full On-resistance match R DS(on) I S = 1 ma, D = ± 3 On-resistance flatness R flat(on) I S = 1 ma, D = -3, 0, +3 Switch off (for 14 pin TSSOP) Switch on (for 14 pin TSSOP) Switch off (for 16 pin miniqfn) Switch on (for 16 pin miniqfn) Digital Control Room Full Room Full Room ± I S(off) = 5.5, = -5.5 Full D = ± 4.5, S = 4.5 Room ± I D(off) Full I D(on) = 5.5, = -5.5, D = S = ± 4.5 Room ± Full Room ± I S(off) = 5.5, = -5.5 Full D = ± 4.5, S = 4.5 Room ± I D(off) Full I D(on) = 5.5, = -5.5, D = S = ± 4.5 Room ± Full Input current, IN low I IN,, and IL Under test = 0.8 Full Input current, IN high I IN,, and IH Under test = 2 Full μa Input capacitance C IN f = 1 MHz Room pf Dynamic Characteristics Transition time t S(CLOSE) = 3, S(OPEN) = 0, Room TRANS R L = 300, C L = 35 pf Full Turn-on time t ON R L = 300, C L = 35 pf Room Full Turn-off time t OFF S = ± 3 Room Full ns Break-before-make t S = 3 Room time BBM R L = 300, C L = 35 pf Full Charge injection e Q INJ GEN = 0, R GEN = 0, C L = 1 nf Room pc Off isolation e OIRR R L = 50, C L = 5 pf, f = MHz Room db Bandwidth e BW R L = 50, C L = 5 pf Room MHz Channel-to-channel crosstalk e X TALK R L = 50, C L = 5 pf, f = MHz Room db Source off capacitance e C S(off) Room Drain off capacitance e C D(off) f = 1 MHz Room pf Drain on capacitance e C D(on) Room UNIT na S Rev. B, 09-Oct-17 3 Document Number: ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

4 SPECIFICATIONS FOR DUAL SUPPLIES ( = 5, = -5 ) PARAMETER Power Supply Power supply current I+ Negative supply current SYMBOL I- TEST CONDITIONS UNLESS OTHERWISE SPECIFIED = 5, = -5 IN,, AND = 2, 0.8 a IN = 0 or TEMP. b Room Full Room Full Ground current I Room Full Notes a. Signals on S X, D X, or IN X exceeding or will be clamped by internal diodes. Limit forward diode current to maximum current ratings b. All leads welded or soldered to PC board c. Derate 5.6 mw/ C above 70 C d. Derate 6.6 mw/ C above 70 C e. Manual soldering with iron is not recommended for leadless components. The miniqfn-16 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper lip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection TYP. c -40 C to +125 C -40 C to +85 C MIN. d MAX. d MIN. d MAX. d UNIT μa S Rev. B, 09-Oct-17 4 Document Number: ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

5 SPECIFICATIONS FOR SINGLE SUPPLY ( = 5, = 0 ) PARAMETER SYMBOL TEST CONDITIONS UNLESS OTHERWISE SPECIFIED = 5, = 0 IN,, AND = 2, 0.8 a TEMP. b TYP. c -40 C to +125 C -40 C to +85 C MIN. d MAX. d MIN. d MAX. d Analog Switch Analog signal range e ANALOG Full Drain-source Room R On-resistance DS(on) I S = 1 ma, D = +3.5 Full On-resistance match R DS(on) I S = 1 ma, D = +3.5 On-resistance flatness R flat(on) I S = 1 ma, D = 0, +3.5 Switch off (for 14 pin TSSOP) Switch on (for 14 pin TSSOP) Switch off (for 16 pin miniqfn) Switch on (for 16 pin miniqfn) Digital Control Room Full Room Full Room ± I S(off) = 5.5, = 0 Full D = 1 / 4.5, I S = 4.5 / 1 Room ± D(off) Full I D(on) = 5.5, = 0 D = S = 1 / 4.5 Room ± Full Room ± I S(off) = 5.5, = 0 Full D = 1 / 4.5, I S = 4.5 / 1 Room ± D(off) Full I D(on) = 5.5, = 0, D = S = 1 / 4.5 Room ± Full Input current, IN low I IN,, and IL Under test = 0.8 Full Input current, IN high I IN,, and IH Under test = 2 Full μa Input capacitance C IN f = 1 MHz Room pf Dynamic Characteristics Transition time t TRANS Room Full S(CLOSE) = 3, S(OPEN) = 0, Room Turn-on time t ON R L = 300, C L = 35 pf Full Room Turn-off time t OFF Full ns Room Break-before-make-time t BMM Full Charge injection e Q INJ C L = 1 nf, R GEN = 0, GEN = 0 Full pc Off-isolation e OIRR Room Channel-to-channel f = MHz, R L = 50, C L = 5 pf db crosstalk e X TALK Room Bandwidth e BW R L = 50, C L = 5 pf Room MHz Source off capacitance e C S(off) Drain off capacitance e C D(off) f = 1 MHz Room pf Drain on capacitance e C D(on) UNIT na S Rev. B, 09-Oct-17 5 Document Number: ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

6 SPECIFICATIONS FOR SINGLE SUPPLY ( = 5, = 0 ) PARAMETER Power Supply SYMBOL Power supply current I+ TEST CONDITIONS UNLESS OTHERWISE SPECIFIED = 5, = 0 IN,, AND = 2, 0.8 a TEMP. b Room Full Room Negative supply current I- IN = 0 or Full Room Ground current I Full Notes a. Signals on S X, D X, or IN X exceeding or will be clamped by internal diodes. Limit forward diode current to maximum current ratings b. All leads welded or soldered to PC board c. Derate 5.6 mw/ C above 70 C d. Derate 6.6 mw/ C above 70 C e. Manual soldering with iron is not recommended for leadless components. The miniqfn-16 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper lip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection TYP. c -40 C to +125 C -40 C to +85 C MIN. d MAX. d MIN. d MAX. d UNIT μa S Rev. B, 09-Oct-17 6 Document Number: ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

7 SPECIFICATIONS FOR SINGLE SUPPLY ( = 3, = 0 ) PARAMETER SYMBOL TEST CONDITIONS UNLESS OTHERWISE SPECIFIED = 3, = 0 IN,, AND = 1.4, 0.6 a TEMP. b TYP. c -40 C to +125 C -40 C to +85 C MIN. d MAX. d MIN. d MAX. d Analog Switch Analog signal range e ANALOG Full Drain-source Room R On-resistance DS(on) I S = 1 ma, D = +1.5 Full Room On-resistance match R DS(on) I S = 1 ma, D = +1.5 Full Switch off (for 14 pin TSSOP) Switch on (for 14 pin TSSOP) Switch off (for 16 pin miniqfn) Switch on (for 16 pin miniqfn) Digital Control Room ± I S(off) = 3.3, = 0 Full D = 1 / 3, I S = 3 / 1 Room ± D(off) Full I D(on) = 3.3, = 0 D = S = 1 / 3 Room ± Full Room ± I S(off) = 3.3, = 0 Full D = 1 / 3, I S = 3 / 1 Room ± D(off) Full I D(on) = 3.3, = 0, D = S = 1 / 3 Room ± Full Input current, IN low I IN,, and IL Under test = 0.6 Full Input current, IN high I IN,, and IH Under test = 1.4 Full μa Input capacitance C IN f = 1 MHz Room pf Dynamic Characteristics Transition time t TRANS Room Full S(CLOSE) = 3, S(OPEN) = 0, Room Turn-on time t ON R L = 300, C L = 35 pf Full Room Turn-off time t OFF Full ns Room Break-before-make time t BMM Full Charge injection e Q INJ C L = 1 nf, R GEN = 0, GEN = 0 Full pc Off-isolation e OIRR Room Channel-to-channel f = MHz, R L = 50, C L = 5 pf db crosstalk e X TALK Room Bandwidth e BW R L = 50, C L = 5 pf Room MHz Source off capacitance e C S(off) Room Drain off capacitance e C D(off) f = 1 MHz Room pf Drain on capacitance e C D(on) Room UNIT na S Rev. B, 09-Oct-17 7 Document Number: ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

8 SPECIFICATIONS FOR SINGLE SUPPLY ( = 3, = 0 ) PARAMETER Power Supply Power supply current I+ Negative supply current SYMBOL I- TEST CONDITIONS UNLESS OTHERWISE SPECIFIED = 3, = 0 IN,, AND = 1.4, 0.6 a IN = 0 or TEMP. b Room Full Room Full Ground current I Room Full Notes a. Signals on S X, D X, or IN X exceeding or will be clamped by internal diodes. Limit forward diode current to maximum current ratings b. All leads welded or soldered to PC board c. Derate 5.6 mw/ C above 70 C d. Derate 6.6 mw/ C above 70 C e. Manual soldering with iron is not recommended for leadless components. The miniqfn-16 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper lip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection TYP. c -40 C to +125 C -40 C to +85 C MIN. d MAX. d MIN. d MAX. d UNIT μa Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S Rev. B, 09-Oct-17 8 Document Number: ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

9 TYPICAL CHARACTERISTICS (25 C, unless otherwise noted) R ON - On-Resistance (Ω) = +3 = +5 = R ON - On-Resistance (Ω) ± = ± 5 ± = ± I S = 1 ma D - Analog oltage () 35 I S = 1 ma D - Analog oltage () On-Resistance vs. D (Single Supply oltage) On-Resistance vs. D (Dual Supply oltage) R ON - On-Resistance (Ω) = +3 I S = 1 ma +125 C +85 C +25 C -40 C D - Analog oltage () 00 0 R ON - On-Resistance (Ω) = +5 I S = 1 ma D - Analog oltage () +125 C +85 C +25 C -40 C 00 0 On-Resistance vs. Analog oltage and Temperature On-Resistance vs. Analog oltage and Temperature R ON - On-Resistance (Ω) ± = ±5 I S = 1 ma +125 C +85 C +25 C -40 C D - Analog oltage () 00 0 Loss, OIRR, X TALK (db) 00 0 Loss X TALK OIRR ± = ±5-1 K 1M M M 1G Frequency (Hz) On-Resistance vs. Analog oltage and Temperature Insertion Loss, Off-Isolation, Crosstalk vs. Frequency S Rev. B, 09-Oct-17 9 Document Number: ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

10 TYPICAL CHARACTERISTICS (25 C, unless otherwise noted) Leakage Current (pa) I S(OFF), D = 1, S = 3 I D(ON), D = 3 I D(OFF), D = 3, S = 1 I S(OFF), D = 3, S = 1 I D(OFF), D = 1, S = = +3.3 I D(ON), D = Leakage Current (pa) I S(OFF), D = 1, S = 4.5 I D(ON), D = I D(OFF), D = 4.5, S = I S(OFF), D = 4.5, S = I D(OFF), D = 1, S = = +5.5 I D(ON), D = Temperature ( C) Temperature ( C) Leakage Current vs. Temperature Leakage Current vs. Temperature Leakage Current (pa) I S(OFF), D = -4.5, S = 4.5 I D(ON), D = 4.5 I D(OFF), D = 4.5, S = I S(OFF), D = 4.5, S = I D(OFF), D = -4.5, S = 4.5 ± = ±5.5 I D(ON), D = Q INJ - Charge Injection (pc) = 3 ±= ±5 = Temperature ( C) S - Analog oltage () Leakage Current vs. Temperature Charge Injection vs. Analog oltage T - Switching Threshold () C to +125 C INH =-40 C INL = 125 C T - Switching Threshold () C to +125 C INH =-40 C INL = 125 C Single Supply oltage () ± - Dual Supply oltage () Switching Threshold vs. Supply oltage Switching Threshold vs. Supply oltage S Rev. B, 09-Oct-17 Document Number: ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

11 TYPICAL CHARACTERISTICS (25 C, unless otherwise noted) I+ - Supply Current (μa) = K K 1M M Input Switching Frequency (Hz) Supply Current vs. Switching Frequency 00 0 I+, I-, I - Supply Current (µa) ±= ±5 I+ I K M Input Switching Frequency (Hz) Supply Current vs. Switching Frequency I I+ - Supply Current (na) = +5 IN = or = +3 IN = or Temperature ( C) Supply Current vs. Temperature 00 0 I+ - Supply Current (µa) = +5 IN = Temperature ( C) Supply Current vs. Temperature I+ - Supply Current (µa) = 3.0 = IN,, () line t ON(EN), t OFF(EN) - Switching Time (ns) = +5, t OFF = +5, t ON ± = ±5, t ON ± = ±5, t OFF Temperature ( C) Supply Current vs. Enable Input oltage Switching Time vs. Temperature S Rev. B, 09-Oct Document Number: ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

12 TEST CIRCUITS 50 Ω S1A or S2A S2A or S2B S1A or S2A S2A or S2B, CC 50 % 0 t r < 5 ns t f < 5 ns S1A or S2A D1 or D2 O O 50 % 300 Ω 35 pf 90 % t TRANS t TRANS Fig. 1 - Transition Time S1A or S2A S1B or S2B CC 0 50 % t r < 5 ns t f < 5 ns S1A or S2A 90 % 90 % D1 or D2 O O 50 % 50 Ω 300 Ω 35 pf 0 t ON S1A or S2A ON t OFF Fig. 2 - Enable Switching Time 50 Ω SxA - SxB, CC 0 50 % t r < 5 ns t f < 5 ns SxA or SxB 80 % + D1 or D2 O O 300 Ω 35 pf 0 t D Fig. 3 - Break-Before-Make S Rev. B, 09-Oct Document Number: ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

13 TEST CIRCUITS + t r < 5 ns t f < 5 ns Channel Select R g + CC 0 OFF ON OFF SxA or SxB g D1 or D2 O O Δ O - C L 1 nf Charge Injection = Δ O X C L - Fig. 4 - Charge Injection + Network Analyzer Network Analyzer S1A or S2A IN g R g = 50 Ω + SxA or SxB IN g R g = 50 Ω D1 or D2 OUT D1 or D2 OUT 50 Ω 50 Ω Insertion Loss = 20 log OUT IN Off Isolation = 20 log OUT IN Fig. 5 - Insertion Loss Fig. 7 - Off-Isolation Network Analyzer S1A or S2A D1 or D2 50 Ω S1B or S2B IN OUT g R g = 50 Channel Select S1A or S2A to S2A or S2B Impedance Analyzer - 50 Ω D1 or D2 - Cross Talk = 20 log OUT IN Fig. 6 - Crosstalk Fig. 8 - Source / Drain Capacitance maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see S Rev. B, 09-Oct Document Number: ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

14 Thin miniqfn16 Case Outline Package Information A D B Terminal tip (4) 16 x b M M C AB C C E L C Pin #1 identifier (5) 15 x L e Top view Bottom view C Seating plane Side view A3 A 0. C 0. C DIMENSIONS MILLIMETERS (1) INCHES MIN. NOM. MAX. MIN. NOM. MAX. A A ref ref. b D e 0.40 BSC BSC E L L N (3) Nd (3) 4 4 Ne (3) 4 4 Notes (1) Use millimeters as the primary measurement. (2) Dimensioning and tolerances conform to ASME Y14.5M (3) N is the number of terminals. Nd and Ne is the number of terminals in each D and E site respectively. (4) Dimensions b applies to plated terminal and is measured between 0.15 mm and 0.30 mm from terminal tip. (5) The pin 1 identifier must be existed on the top surface of the package by using identification mark or other feature of package body. (6) Package warpage max mm. ECN: T Rev. B, 09-May-16 DWG: 6023 Revision: 09-May-16 1 Document Number: ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

15 Package Information 14L TSSOP C L 14 D C L 3 e 4 E1 E Notes: 1. All dimensions are in millimeters (angles in degrees) 2. Dimensioning and tolerancing per ANSI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs 4 Dimension E1 does not include internal flash or protrusion 5 Dimension b does not include dambar protrusion 6 Cross section B to B to be determined at 0. mm to 0.25 mm from the lead tip Pin 1 ID mark Detail A b A2 A Seating Plane B B Gauge Plane R R1 c1 5 b Seating Plane c θ1 L b1 Detail B to B L1 Detail A SYMBOL MINIMUM NOMINAL MAXIMUM A A D E E L R R b b c c θ1 0-8 L1 1.0 ref. e 0.65 BSC ECN: T Rev. A, 14-Jan-08 DWG: 5962 Document Number: Revision: 14-Jan-08 1

16 PAD Pattern RECOMMENDED MINIMUM PADS FOR MINI QFN 16L (0.0221) (0.0157) (0.0089) (0.1142) (0.0182) (0.0472) 2. (0.0827) Mounting Footprint Dimensions in mm (inch) Document Number: Revision: 05-Mar- 1

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