High-Speed, Low-Glitch D/CMOS Analog Switches

Transcription

1 G6, G62, G63 High-Speed, Low-Glitch /CMOS Analog Switches ESCRIPTION The G6, G62, G63 feature high-speed lowcapacitance lateral MOS switches. Charge injection has been minimized to optimize performance in fast sample-andhold applications. Each switch conducts equally well in both directions when on and blocks up to 6 V p-p when off. Capacitances have been minimized to ensure fast switching and low-glitch energy. To achieve such fast and clean switching performance, the G6, G62, G63 are built on the proprietary /CMOS process. This process combines n-channel MOS switching FETs with low-power CMOS control logic and drivers. An epitaxial layer prevents latchup. The G6 and G62 differ only in that they respond to opposite logic levels. The versatile G63 has two normally open and two normally closed switches. It can be given various configurations, including four SPST, two SPT, one PT. For additional information see Applications Note AN27. FEATURES Fast switching - t ON : 2 ns Low charge injection: ± 2 pc Wide bandwidth: MHz V CMOS logic compatible Low R S(on) : 8 Low quiescent power :.2 nw Single supply operation BENEFITS Improved data throughput Minimal switching transients Improved system performance Easily interfaced Low insertion loss Minimal power consumption APPLICATIONS Fast sample-and-holds Synchronous demodulators Pixel-rate video switching isk/tape drives AC deglitching Switched capacitor filters GaAs FET drivers Satellite receivers FUNCTIONAL BLOCK IAGRAM AN PIN CONFIGURATION G6 IN 6 IN S 3 4 S 2 V- 4 ual-in-line and SOIC 3 V+ GN Top View 2 V L S 4 6 S IN IN 3 G6 IN NC IN 2 2 Key S 4 8 S 2 V- 7 V+ NC 6 LCC 6 NC Top View 7 GN V L S S IN 4 NC IN 3 3 Four SPST Switches per Package TRUTH TABLE Logic G6 G62 ON OFF OFF ON Logic V Logic 4 V * Pb containing terminations are not RoHS compliant, exemptions may apply ocument Number: 77 S-4-Rev. I, 3-Jan-

2 G6, G62, G63 FUNCTIONAL BLOCK IAGRAM AN PIN CONFIGURATION G63 G63 IN 6 IN S 3 4 S 2 V- 4 ual-in-line and SOIC 3 V+ GN Top View 2 V L S 4 6 S IN IN 3 Key S 4 V- NC 6 GN 7 S 4 8 IN NC IN LCC Top View IN 4 NC IN S 2 V+ NC V L S 3 Four SPST Switches per Package TRUTH TABLE Logic SW, SW 4 SW 2, SW 3 OFF ON ON OFF Logic V Logic 4 V ORERING INFORMATION Temp. Range Package Part Number G6, G62 G63-4 C to 8 C - 4 C to 8 C 6-Pin Plastic IP 6-Pin Narrow SOIC 6-Pin Plastic IP 6-Pin Narrow SOIC G6J G6J-E3 G62J G62J-E3 G6Y G6Y-E3 G6Y-T G6Y-T-E3 G62Y G62Y-E3 G62Y-T G62Y-T-E3 G63J G63J-E3 G63Y G63Y-E3 G63Y-T G63Y-T-E3 2 ocument Number: 77 S-4-Rev. I, 3-Jan-

3 G6, G62, G63 ABSOLUTE MAXIMUM RATINGS Parameter Limit Unit V+ to V- -.3 to 2 V+ to GN -.3 to 2 V- to GN - 9 to.3 V L to GN - to (V+) + or 2 ma, whichever occurs first V V a (V-) - to (V+) + IN or 2 ma, whichever occurs first V S, V a (V-) -.3 to (V+) + 6 or 2 ma, whichever occurs first Continuous Current (Any Terminal) ± 3 Current, S or (Pulsed at µs, % uty Cycle) ± ma Storage Temperature CerIP - 6 to Plastic - 6 to 2 C 6-Pin Plastic IP c 47 Power issipation (Package) b 6-Pin Narrow SOIC d 6 6-Pin CerIP e 9 mw 2-Pin LCC e 9 Notes: a. Signals on S X, X, or IN X exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC board. c. erate 6 mw/ C above 7 C. d. erate 7.6 mw/ C above 7 C. e. erate 2 mw/ C above 7 C. RECOMMENE OPERATING RANGE Parameter Limit Unit V+ to 2 V- - to V L 4 to V+ V V IN to V L V ANALOG V- to (V+) - ocument Number: 77 S-4-Rev. I, 3-Jan- 3

4 G6, G62, G63 SPECIFICATIONS a Test Conditions Unless Otherwise Specified V+ = V, V L = V, V IN = 4 V, V f Temp. b Typ. c A Suffix - C to 2 C Suffix - 4 C to 8 C Parameter Symbol Min. d Max. d Min. d Max. d Unit Analog Switch Analog Signal Range e V ANALOG V- = - V, V+ = 2 V Full V Switch On-Resistance R S(on) Room I S = - ma, V = V Full 6 6 Resistance Match Bet Ch. R S(on) Room 2 Source Off Leakage I S(off) V S = V, V = V Room ± Hot rain Off Leakage Current I (off) V S = V, V = V Room ± Hot na Switch On Leakage Current I (on) V S = V = V Room ± Hot igital Control Input Voltage High V IH Full 4 4 Input Voltage Low V IL Full V Input Current I IN Room Hot Input Capacitance C IN Room pf ynamic Characteristics Off State Input Capacitance C S(off) V S = V Room 3 Off State Output Capacitance C (off) V = V Room 2 pf On State Input Capacitance C S(on) V S = V = V Room Bandwidth BW R L = Room MHz Turn-On Time e t ON R L = 3 C L = 3 pf Room Turn-Off Time e t OFF V S = ± 2 V, See test circuit, figure 2 Room Room ns Turn-On Time t ON R L = 3 C L = 7 pf Full V S = ± 2 V, Room Turn-Off Time t OFF See test circuit, figure 2 Full 3 3 Charge Injection e Q C L = nf, V S = V Room 4 Ch. Injection Change e,g Q C L = nf, V S 3 V Room pc Off Isolation e R OIRR IN = R L = f = MHz Room 74 Crosstalk e R X IN =, R L = TALK f = MHz Room 87 db Power Supplies Positive Supply Current I+ Room Full Room Negative Supply Current I- Full V IN = V or V Room Logic Supply Current I L Full Room Ground Current I GN Full µa µa 4 ocument Number: 77 S-4-Rev. I, 3-Jan-

5 G6, G62, G63 SPECIFICATIONS FOR UNIPOLAR SUPPLIES a Parameter Symbol Test Conditions Unless Otherwise Specified V+ = V, V L = V, V IN = 4 V, V f Temp. b Ty.p c A Suffix - C to 2 C Suffix - 4 C to 8 C Min. d Max. d Min. d Max. d Analog Switch Analog Signal Range e V ANALOG Full 7 7 V Switch On-Resistance R S(on) I S = - ma, V = V Room ynamic Characteristics Turn-On Time e t ON R L = 3 C L = 3 pf Room 3 3 Turn-Off Time e t OFF V S = 2 V, See test circuit, figure 2 Room 2 2 Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 2 C, Full = as determined by the operating temperature suffix. c. Typical values are for ESIGN AI ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. e. Guaranteed by design, not subject to production test. f. V IN = input voltage to perform proper function. g. Q = Q at V S = 3 V - Q at V S = - 3 V. Unit ns Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TYPICAL CHARACTERISTICS (2 C, unless otherwise noted) R S(on) - rain-source On-Resistance ( ) I S = - ma V+ = V V- = - V V+ = 2 V V- = - V V+ = V - Leakage Current (pa), I I S V+ = V I S(of f), I (of f) I (on) V - rain Voltage (V) R S(on) vs. V and Power Supply Voltages V or V S - rain or Source Voltage (V) Leakage Current vs. Analog Voltage ocument Number: 77 S-4-Rev. I, 3-Jan-

6 G6, G62, G63 TYPICAL CHARACTERISTICS (2 C, unless otherwise noted) 6 24 V+ = V 22 2 V TH - Logic Input Voltage (V) Time (ns) t OFF t ON V+ = V R L = 3 C L = pf V L - Logic Supply Voltage (V) Input Switching Threshold vs. V L Temperature ( C) Switching Times vs. Temperature R S(on) - rain-source On-Resistance ( ) V+ = V I S = - ma C 2 C - C V - rain Voltage (V) R S(on) vs. V and Temperature 2 Charge (pc) V+ = V - 2 Qd Qs V ANALO G - Analog Voltage (V) Charge Injection vs. Analog Voltage na R L = na Leakage (A) I S(off), I (off) pa pa I (on) I S(of f), I (of f) Insertion Loss (db) db Point pa - 2. pa Temperature ( C) Leakage Currents vs. Temperature - 24 f - Frequency (MHz) - 3 db Bandwidth/Insertion Loss vs. Frequency 6 ocument Number: 77 S-4-Rev. I, 3-Jan-

7 G6, G62, G63 TYPICAL CHARACTERISTICS (2 C, unless otherwise noted) (db) V+ = V Of f Isolation Crosstalk Supply Current (ma) V+ = V V L = V C X =, V I+ I- I L K K K M M f - Frequency (MHz) Crosstalk and Off Isolation vs. Frequency f - Frequency (Hz) Supply Currents vs. Switching Frequency SCHEMATIC IAGRAM (Typical Channel) V+ V L S IN X Input Logic Level Translator river MOS Switch V- Figure. TEST CIRCUITS ± 2 V + V V L S IN GN + V V+ V- R L 3 V O C L V Logic Input V V S = ± 2 V Switch Output V % 2 % 9 % t r < ns t f < ns V- t ON t OFF C L (includes fixture and stray capacitance) Figure 2. Switching Time V O = V S R L R L + r S(on) ocument Number: 77 S-4-Rev. I, 3-Jan- 7

8 G6, G62, G63 TEST CIRCUITS C + V + V C V S V L S V+ + V + V R g = V, 4 V IN V g R g V V L S IN GN V+ V- - 3 V V O C L nf NC V, 4 V V S X TA LK Isolation = 2 log V O C = RF bypass S 2 2 IN 2 GN V- - 3 V C V O R L Figure 3. Charge Injection Figure 4. Crosstalk APPLICATIONS High-Speed Sample-and-Hold In a fast sample-and-hold application, the analog switch characteristics are critical. A fast switch reduces aperture uncertainty. A low charge injection eliminates offset (step) errors. A low leakage reduces droop errors. The CLC, a fast input buffer, helps to shorten acquisition and settling times. A low leakage, low dielectric absorption hold capacitor must be used. Polycarbonate, polystyrene and polypropylene are good choices. The JFET output buffer reduces droop due to its low input bias current. (see figure.) Pixel-Rate Switch Windows, picture-in-picture, title overlays are economically generated using a high-speed analog switch such as the G63. For this application the two video sources must be sync locked. The glitch-less analog switch eliminates halos. (see figure 6.) GaAs FET rivers Figure 7 illustrates a high-speed GaAs FET driver. To turn the GaAs FET on V are applied to its gate via S, whereas to turn it off, - 8 V are applied via S 2. This high-speed, low-power driver is especially suited for applications that require a large number of RF switches, such as phased array radars. Input Buffer + V + 2 V Output Buffer Analog Input 7 CLC S + LF36 - ± V Output to A/ V Control IN / 4 G6 C HOL 6 pf Polystyrene - V Figure. High-Speed Sample-and-Hold 8 ocument Number: 77 S-4-Rev. I, 3-Jan-

9 G6, G62, G63 APPLICATIONS Background 7 / 2 CLC4 + V + 2 V Output Buffer + CLC4-7 Composite Output Titles V Control / 2 G63 - V Figure 6. A Pixel-Rate Switch Creates Title Overlays + V S V L V+ RF IN GaAs RF OUT IN / 2 G63 S 2 2 V IN 2 GN V- - 8 V Figure 7. A High-Speed GaAs FET river that Saves Power maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?77. ocument Number: 77 S-4-Rev. I, 3-Jan- 9

10 Package Information JEEC Part Number: MS E im Min Max Min Max A A B C E e.27 BSC. BSC H L ECN: S-3946 Rev. F, 9-Jul- WG: 3 H C All Leads e B A L. mm.4 IN ocument Number: Jul-

11 Package Information E E S Q A A L B e B C e A MAX im Min Max Min Max A A B B C E E e e A L Q S ECN: S-3946 Rev., 9-Jul- WG: 482 ocument Number: Jul-

12 Package Information E E S Q A A L L B e B C e A im Min Max Min Max A A B B C E E e 2.4 BSC. BSC e A 7.62 BSC.3 BSC L L Q S ECN: S-3946 Rev. G, 9-Jul- WG: 43 ocument Number: Jul-

13 Packaging Information A e L 28 2 E A im Min Max Min Max BSC. BSC ECN: S-3946 Rev. B, 9-Jul- WG: 32 L B ocument Number: Jul-

14 Application Note 826 RECOMMENE MINIMUM PAS FOR SO-6 RECOMMENE MINIMUM PAS FOR SO (9.449).47 (.94) APPLICATION NOTE.246 (6.248).2 (3.86).22 (.9). (.27).28 (.7) Recommended Minimum Pads imensions in Inches/(mm) Return to Index Return to Index ocument Number: Revision: 2-Jan-8

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