P-Channel 150 V (D-S) MOSFET

Transcription

1 P-Channel 5 V (-S) MOSFET Si4H PROUCT SUMMARY V S (V) R S(on) () I (A) Q g (TYP.) -5.6 at V GS = - V at V GS = -6 V SOT-363 SC-7 Single (6 leads) S nc FEATURES TrenchFET power MOSFETS Small, thermally enhanced SC-7 package Ultra low on-resistance Material categorization: for definitions of compliance please see APPLICATIONS Active clamp circuits in C/C power supplies S Top View Marking Code: BG Ordering Information: Si4H-T-GE3 (lead (Pb)-free and halogen-free) 3 G G P-Channel MOSFET ABSOLUTE MAXIMUM RATINGS (T A = 5 C, unless otherwise noted) PARAMETER SYMBOL 5 s STEAY STATE UNIT rain-source Voltage V S -5 V Gate-Source Voltage V GS ± Continuous rain Current (T J = 5 C) a T A = 5 C I T A = 85 C Pulsed rain Current I M -.8 A Continuous iode Current (iode Conduction) a I S Single Pulse Avalanche Current I AS -. L =. mh Single Pulse Avalanche Energy E AS. mj Maximum Power issipation a T A = 5 C.56 P W T A = 85 C.8.5 Operating Junction and Storage Temperature Range T J, T stg -55 to +5 C THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYPICAL MAXIMUM UNIT Maximum Junction-to-Ambient a t 5 s 6 8 R thja Steady State 5 C/W Maximum Junction-to-Foot (rain) Steady State R thjf Note a. Surface mounted on " x " FR4 board. S6-887-Rev., 9-May-6 ocument Number: 734 For technical questions, contact: pmostechsupport@vishay.com THIS OCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PROUCTS ESCRIBE HEREIN AN THIS OCUMENT ARE SUBJECT TO SPECIFIC ISCLAIMERS, SET FORTH AT

2 Si4H SPECIFICATIONS (T J = 5 C, unless otherwise noted) PARAMETER SYMBOL TEST CONITIONS MIN. TYP. MAX. UNIT Static Gate Threshold Voltage V GS(th) V S = V GS, I = - μa V Gate-Body Leakage I GSS V S = V, V GS = ± V - - ± na V S = -5 V, V GS = V Zero Gate Voltage rain Current I SS V S = -5 V, V GS = V, T J = 85 C μa On-State rain Current a I (on) V S = -5 V, V GS = - V A V GS = - V, I = -.5 A rain-source On-State Resistance a R S(on) V GS = -6 V, I = -.5 A Forward Transconductance a g fs V S = - V, I = -.5 A S iode Forward Voltage a V S I S = -.4 A, V GS = V V ynamic b Total Gate Charge Q g Gate-Source Charge Q gs V S = -75 V, V GS = - V, I = -.5 A nc Gate-rain Charge Q gd Gate Resistance R g f = MHz Turn-On elay Time t d(on) Rise Time t r V = -75 V, R L = 75-7 Turn-Off elay Time t d(off) I - A, V GEN = -4.5 V, R g = ns Fall Time t f - 7 Reverse Recovery Time t rr I F = -.5 A, di/dt = A/μs Body iode Reverse Recovery Charge Q rr - 65 nc Notes a. Pulse test; pulse width 3 μs, duty cycle %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S6-887-Rev., 9-May-6 ocument Number: 734 For technical questions, contact: pmostechsupport@vishay.com THIS OCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PROUCTS ESCRIBE HEREIN AN THIS OCUMENT ARE SUBJECT TO SPECIFIC ISCLAIMERS, SET FORTH AT

3 Si4H TYPICAL CHARACTERISTICS (5 C, unless otherwise noted).8.7 V GS = V thru 5 V.8.7 I - rain Current (A) V 3 V V S - rain-to-source Voltage (V) Output Characteristics - rain Current (A) I T C = 5 C.3. 5 C C V GS - Gate-to-Source Voltage (V) Transfer Characteristics R S(on) V GS = 6 V V GS = V C - Capacitance (pf) 5 5 C rss C oss C iss I - rain Current (A) On-Resistance vs. rain Current V S - rain-to-source Voltage (V) Capacitance.5 - Gate-to-Source Voltage (V) V GS V S = 75 V I =.5 A R S(on) - On-Resistance (Normalized) V GS = V I =.5 A Q g - Total Gate Charge (nc) Gate Charge T J - Junction Temperature ( C) On-Resistance vs. Junction Temperature S6-887-Rev., 9-May-6 3 ocument Number: 734 For technical questions, contact: pmostechsupport@vishay.com THIS OCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PROUCTS ESCRIBE HEREIN AN THIS OCUMENT ARE SUBJECT TO SPECIFIC ISCLAIMERS, SET FORTH AT

4 Si4H TYPICAL CHARACTERISTICS (5 C, unless otherwise noted) 6 5 I S - Source Current (A). T J = 5 C T J = 5 C - On-Resistance () R S(on) 4 3 I =.5 A V S - Source-to-rain Voltage (V) Source-rain iode Forward Voltage V GS - Gate-to-Source Voltage (V) On-Resistance vs. Gate-to-Source Voltage.3 35 Variance (V) V GS(th) I = 5 µa Power (W) 8 4 T A = 5 C Single Pulse T J - Temperature ( C)... Time (s) Threshold Voltage Single Pulse Power, Junction-to-Ambient µs Limited by R S(on) * µs ms - rain Current (A) I.. T A = 5 C Single Pulse ms ms s, s s, C.. V S - rain-to-source Voltage (V) *V GS > minimum V GS at which R S(on) is specified Safe Operating Area S6-887-Rev., 9-May-6 4 ocument Number: 734 For technical questions, contact: pmostechsupport@vishay.com THIS OCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PROUCTS ESCRIBE HEREIN AN THIS OCUMENT ARE SUBJECT TO SPECIFIC ISCLAIMERS, SET FORTH AT

5 Si4H TYPICAL CHARACTERISTICS (5 C, unless otherwise noted) Normalized Effective Transient Thermal Impedance.. uty Cycle = Single Pulse Square Wave Pulse uration (s) Notes: P M t t t. uty Cycle, = t. Per Unit Base = R thja = C/W 3. T JM - T A = P M Z (t) thja 4. Surface Mounted Normalized Thermal Transient Impedance, Junction-to-Ambient Normalized Effective Transient Thermal Impedance. uty Cycle = Single Pulse Square Wave Pulse uration (s) Normalized Thermal Transient Impedance, Junction-to-Foot maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see S6-887-Rev., 9-May-6 5 ocument Number: 734 For technical questions, contact: pmostechsupport@vishay.com THIS OCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PROUCTS ESCRIBE HEREIN AN THIS OCUMENT ARE SUBJECT TO SPECIFIC ISCLAIMERS, SET FORTH AT

6 Package Information e b e E E -B- -A- A A c L im Min Nom Max Min Nom Max A A..4 A b c E E e.65bsc.6bsc e L Nom 7Nom A ECN: S-3946 Rev. B, 9-Jul- WG: 555 ocument Number: Jul-

7 AN85 Single-Channel LITTLE FOOT SC-7 6-Pin MOSFET Copper Leadframe Version Recommended Pad Pattern and Thermal Performance INTROUCTION The new single 6-pin SC-7 package with a copper leadframe enables improved on-resistance values and enhanced thermal performance as compared to the existing 3-pin and 6-pin packages with Alloy 4 leadframes. These devices are intended for small to medium load applications where a miniaturized package is required. evices in this package come in a range of on-resistance values, in n-channel and p-channel versions. This technical note discusses pin-outs, package outlines, pad patterns, evaluation board layout, and thermal performance for the single-channel version. EVALUATION BOARS SINGLE SC7-6 The evaluation board (EVB) measures.6 inches by.5 inches. The copper pad traces are the same as in Figure. The board allows examination from the outer pins to 6-pin IP connections, permitting test sockets to be used in evaluation testing. See Figure 3. 5 (mil) BASIC PA PATTERNS See Application Note 86, Recommended Minimum Pad Patterns With Outline rawing Access for MOSFETs, ( for the basic pad layout and dimensions. These pad patterns are sufficient for the low to medium power applications for which this package is intended. Increasing the drain pad pattern yields a reduction in thermal resistance and is a preferred footprint. The availability of four drain leads rather than the traditional single drain lead allows a better thermal path from the package to the PCB and external environment. 96 (mil) 7 (mil) 3 (mil) , (mil) 6 (mil) 8 (mil) PIN-OUT 6 (mil) 6 (mil) Figure shows the pin-out description and Pin identification.the pin-out of this device allows the use of four pins as drain leads, which helps to reduce on-resistance and junction-to-ambient thermal resistance. FIGURE. SC-7 (6 leads) Single SOT-363 SC-7 (6-LEAS) 6 5 The thermal performance of the single 6-pin SC-7 has been measured on the EVB, comparing both the copper and Alloy 4 leadframes. This test was first conducted on the traditional Alloy 4 leadframe and was then repeated using the -inch PCB with dual-side copper coating. G 3 4 S Top View FIGURE. For package dimensions see outline drawing SC-7 (6-Leads) ( ocument Number: ec-3

8 AN85 Front of Board SC7-6 Back of Board SC7-6 vishay.com FIGURE 3. THERMAL PERFORMANCE Junction-to-Foot Thermal Resistance (Package Performance) The junction to foot thermal resistance is a useful method of comparing different packages thermal performance. A helpful way of presenting the thermal performance of the 6-Pin SC-7 copper leadframe device is to compare it to the traditional Alloy 4 version. Thermal performance for the 6-pin SC-7 measured as junction-to-foot thermal resistance, where the foot is the drain lead of the device at the bottom where it meets the PCB. The junction-to-foot thermal resistance is typically 4C/W in the copper leadframe and 63C/W in the Alloy 4 leadframe a four-fold improvement. This improved performance is obtained by the enhanced thermal conductivity of copper over Alloy 4. Power issipation The typical R JA for the single 6-pin SC-7 with copper leadframe is 3C/W steady-state, compared with C/W for the Alloy 4 version. The figures are based on the -inch FR4 test board. The following example shows how the thermal resistance impacts power dissipation for the two different leadframes at varying ambient temperatures. ALLOY 4 LEAFRAME Room Ambient 5 C P T J(max) T A R JA P 5o C 5 o C o CW P 59 mw Elevated Ambient 6 C P T J(max) T A R JA P 5o C 5 o C o CW P 45 mw COOPER LEAFRAME Room Ambient 5 C P T J(max) T A R JA P 5o C 5 o C 4 o CW P. W Elevated Ambient 6 C P T J(max) T A R JA P 5o C 6 o C 4 o CW P 76 mw As can be seen from the calculations above, the compact 6-pin SC-7 copper leadframe LITTLE FOOT power MOSFET can handle up to W under the stated conditions. Testing To further aid comparison of copper and Alloy 4 leadframes, Figure 5 illustrates single-channel 6-pin SC-7 thermal performance on two different board sizes and two different pad patterns. The measured steady-state values of R JA for the two leadframes are as follows: LITTLE FOOT 6-PIN SC-7 ) Minimum recommended pad pattern on the EVB board V (see Figure 3. ) Industry standard -inch PCB with maximum copper both sides. Alloy C/W.8C/W Copper 8.5C/W 3.5C/W The results indicate that designers can reduce thermal resistance (R JA ) by 36% simply by using the copper leadframe device rather than the Alloy 4 version. In this example, a C/W reduction was achieved without an increase in board area. If increasing in board size is feasible, a further 5C/W reduction could be obtained by utilizing a -inch square PCB area. The copper leadframe versions have the following suffix: Single: Si4xxEH ual: Si9xxEH Complementary: Si5xxEH ocument Number: ec-3

9 AN Thermal Resistance (C/W) Alloy 4 Copper Thermal Resistance (C/W) 5 5 Alloy 4 Copper Time (Secs) Time (Secs) FIGURE 4. Leadframe Comparison on EVB FIGURE 5. Leadframe Comparison on Alloy 4 -inch PCB ocument Number: ec-3 3

10 Application Note 86 RECOMMENE MINIMUM PAS FOR SC-7: 6-Lead.67 (.7) APPLICATION NOTE.96 (.438).45 (.43).6 (.648).6 (.46).6 (.648). (.4) Recommended Minimum Pads imensions in Inches/(mm) Return to Index Return to Index ocument Number: 76 8 Revision: -Jan-8

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