DATASHEET DG408, DG409. Features. Applications. Ordering Information. Single 8-Channel/Differential 4-Channel, CMOS Analog Multiplexers

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1 ATASHEET G48, G49 Single 8-Channel/ifferential 4-Channel, CMOS Analog Multiplexers FN3283 Rev 8. The G48 Single 8-Channel, and G49 ifferential 4-Channel monolithic CMOS analog multiplexers are drop-in replacements for the popular G58A and G59A series devices. They each include an array of eight analog switches, a TTL/CMOS compatible digital decode circuit for channel selection, a voltage reference for logic thresholds and an ABLE input for device selection when several multiplexers are present. The G48 and G49 feature lower signal ON resistance (<1 ) and faster switch transition time (t TRANS < 25ns) compared to the G58A or G59A. Charge injection has been reduced, simplifying sample and hold applications. The improvements in the G48 series are made possible by using a high-voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. Power supplies may be single-ended from +5V to +34V, or split from 5V to 2V. The analog switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a 5V analog input range. Features ON Resistance (Max, 25 C) Low Power Consumption (P ) <11mW Fast Switching Action - t TRANS <25ns - t ON/OFF() <15ns Low Charge Injection Upgrade from G58A/G59A TTL, CMOS Compatible Single or Split Supply Operation Pb-Free Plus Anneal Available (RoHS Compliant) Applications ata Acquisition Systems Audio Switching Systems Automatic Testers Hi-Rel Systems Sample and Hold Circuits Communication Systems Analog Selector Switch Ordering Information PART NUMBER PART MARKING TEMP. RANGE ( C) PACKAGE PKG. WG. # G48J G48J -4 to Ld PIP E16.3 G48JZ (Note) G48JZ -4 to Ld PIP** (Pb-free) E16.3 G48Y* G48Y -4 to Ld SOIC M16.15 G48YZ* (Note) G48YZ -4 to Ld SOIC (Pb-free) M16.15 G48VZ* (Note) G48VZ -4 to Ld TSSOP (Pb-free) M G49J G49J -4 to Ld PIP E16.3 G49JZ (Note) G49JZ -4 to Ld PIP** (Pb-free) E16.3 G49Y* G49Y -4 to Ld SOIC M16.15 G49YZ* (Note) G49YZ -4 to Ld SOIC (Pb-free) M16.15 G49VZ* (Note) G49VZ -4 to Ld TSSOP (Pb-free) M *Add -T suffix for tape and reel. **Pb-free PIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 1% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEEC J ST-2. FN3283 Rev 8. Page 1 of 17

2 G48, G49 Pinouts G48 (PIP, SOIC, TSSOP) TOP VIEW G49 (PIP, SOIC, TSSOP) TOP VIEW A V- S 1 S 2 S 3 S A 1 A 1 16 A 1 15 A GN 14 GN V S 5 S 1A S 2A S 1B 12 S 2B 11 S 6 S 3A 6 11 S 3B 1 S 7 S 4A 7 1 S 4B 9 S 8 A 8 9 B Functional Block iagrams G48 G49 S 1 S 1A A S 2 ECOER/ RIVER S 4A S 1B B S 8 S 4B ECOER/ RIVER 5V REF LEVEL SHIFT 5V REF LEVEL SHIFT IGITAL PROTECTION IGITAL PROTECTION A A 1 A 2 A A 1 TRUTH TABLE G48 A 2 A 1 A ON X X X NONE TRUTH TABLE G49 A 1 A ON X X NONE NOTES: 1. V AH Logic 1 2.4V. 2. V AL Logic.8V FN3283 Rev 8. Page 2 of 17

3 G48, G49 Pin escriptions - (G48) PIN SYMBOL ESCRIPTION 1 A Logic ecode Input (Bit, LSB) 2 Enable Input 3 V- Negative Power Supply Terminal 4 S 1 Source (Input) for Channel 1 5 S 2 Source (Input) for Channel 2 6 S 3 Source (Input) for Channel 3 7 S 4 Source (Input) for Channel 4 8 rain (Output) 9 S 8 Source (Input) for Channel 8 1 S 7 Source (Input) for Channel 7 11 S 6 Source (Input) for Channel 6 12 S 5 Source (Input) for Channel 5 13 Positive Power Supply Terminal (Substrate) 14 GN Ground Terminal (Logic Common) 15 A 2 Logic ecode Input (Bit 2, MSB) 16 A 1 Logic ecode Input (Bit 1) Pin escriptions - (G49) PIN SYMBOL ESCRIPTION 1 A Logic ecode Input (Bit, LSB) 2 Enable Input 3 V- Negative Power Supply Terminal 4 S 1A Source (Input) for Channel 1a 5 S 2A Source (Input) for Channel 2a 6 S 3A Source (Input) for Channel 3a 7 S 4A Source (Input) for Channel 4a 8 A rain a (Output a) 9 B rain b (Output b) 1 S 4B Source (Input) for Channel 4b 11 S 3B Source (Input) for Channel 3b 12 S 2B Source (Input) for Channel 2b 13 S 1B Source (Input) for Channel 1b 14 Positive Power Supply Terminal 15 GN Ground Terminal (Logic Common) 16 A 1 Logic ecode Input (Bit 1, MSB) FN3283 Rev 8. Page 3 of 17

4 G48, G49 Absolute Maximum Ratings to V V GN to V V igital Inputs, V S, V (Note 3)......(V-) -2V to () + 2V or 2mA, Whichever Occurs First Continuous Current (Any Terminal) mA Peak Current, S or (Pulsed 1ms, 1% uty Cycle Max).. 1mA Operating Conditions Temperature Range C to 85 C Thermal Information Thermal Resistance (Typical, Note 4) JA ( C/W) PIP Package SOIC Package TSSOP Package Maximum Junction Temperature C Maximum Storage Temperature Range C to 125 C Maximum Lead Temperature (Soldering 1s) C (SOIC and TSSOP - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. Signals on S X, X, or A X exceeding or V- are clamped by internal diodes. Limit diode current to maximum current ratings. 4. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Test Conditions: =, V- =, V AL =.8V, V AH = 2.4V, Unless Otherwise Specified PARAMETER TEST CONITIONS TEMP ( C) (NOTE 5) MIN (NOTE 6) TYP (NOTE 5) MAX UNITS YNAMIC CHARACTERISTICS Transition Time, t TRANS (See Figure 1) Full ns Break-Before-Make Interval, t OP (See Figure 3) ns Enable Turn-ON Time, t ON() (See Figure 2) ns Full ns Enable Turn-OFF Time, t OFF() (See Figure 2) Full ns Charge Injection, Q C L = 1nF, V S = V pc OFF Isolation V = V, R L = 1k, f = 1kHz (Note 9) db Logic Input Capacitance, C IN f = 1MHz pf Source OFF Capacitance, C S(OFF) V = V, V S = V, pf f = 1MHz rain OFF Capacitance, C (OFF) V = V, V = V, G48 f = 1MHz pf G pf rain ON Capacitance, C (ON) V = 3V, V = V, G48 f = 1MHz, V A = V or 3V pf G pf IGITAL CHARACTERISTICS Logic Input Current, Input Voltage High, I AH V A = 2.4V, 15V Full -1-1 A Logic Input Current, Input Voltage Low, I AL V = V, 2.4V, V A = V Full -1-1 A ANALOG CHARACTERISTICS Analog Signal Range, V ANALOG Full V rain-source ON Resistance, r S(ON) V = 1V, I S = -1mA (Note 7) Full r S(ON) Matching Between Channels, V = 1V, -1V (Note 8) r S(ON) Source OFF Leakage Current, I S(OFF) V = V, V S = 1V, V = +1V na Full -5-5 na FN3283 Rev 8. Page 4 of 17

5 G48, G49 Electrical Specifications Test Conditions: =, V- =, V AL =.8V, V AH = 2.4V, Unless Otherwise Specified (Continued) PARAMETER TEST CONITIONS TEMP ( C) (NOTE 5) MIN (NOTE 6) TYP (NOTE 5) MAX rain OFF Leakage Current, I (OFF) V = V, V = 1V, G48 V S = +1V na Full -2-2 na G na Full -1-1 na rain ON Leakage Current, I (ON) V S = V = 1V (Note 7) G na Full -2-2 na G na Full -1-1 na POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V = V, V A = V (Standby) Full A Negative Supply Current, I- Full A Positive Supply Current, I+ V = 2.4V, V A = V ma (Enabled) Full ma Negative Supply Current, I- Full A UNITS Electrical Specifications Single Supply Test Conditions: = 12V, V- = V, V AL =.8V, V AH = 2.4V, Unless Otherwise Specified PARAMETER TEST CONITION TEMP ( C) (NOTE 5) MIN (NOTE 6) TYP (NOTE 5) MAX UNITS YNAMIC CHARACTERISTICS Switching Time of Multiplexer, t TRANS V S1 = 8V, V S8 = V, V IN = 2.4V ns Enable Turn-ON Time, t ON() V INH = 2.4V, V INL = V, ns Enable Turn-OFF Time, t OFF() V S1 = 5V ns Charge Injection, Q C L = 1nF, V G = V, R G = pc ANALOG CHARACTERISTICS Analog Signal Range, V ANALOG Full - 12 V rain-source ON-Resistance, r S(ON) V = 3V, 1V, I S = -1mA (Note 7) NOTES: 5. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Typical values are for ESIGN AI ONLY, not guaranteed nor production tested. 7. Sequence each switch ON. 8. r S(ON) = r S(ON) (Max) - r S(ON) (Min). 9. Worst case isolation occurs on channel 4 due to proximity to the drain pin. FN3283 Rev 8. Page 5 of 17

6 G48, G49 Test Circuits and Waveforms +2.4V +2.4V S 1 1V S 1B 1V A S 2 - S 7 A G48 1 S 8 A 2 GN V- 1V S 1A - S 4A, A A G49 S 4B A 1 GN V- B 1V pF pF FIGURE 1A. G48 TEST CIRCUIT FIGURE 1B. G49 TEST CIRCUIT 3V V V S1 S 1 ON V V S8 5%.8 V S8 5% t r < 2ns t f < 2ns.8 V S1 t TRANS S 8 ON t TRANS FIGURE 1C. MEASUREMT POINTS FIGURE 1. TRANSITION TIME A S 1-5V A S 1B G48 G49 A 1 A S 2 - S 8 1 S 1A - S 4A A V 2 IN VIN S 2B - S 4B, A V GN V- O GN V- B pF 5 3-5V V o 35pF FIGURE 2A. G48 TEST CIRCUIT FIGURE 2B. G49 TEST CIRCUIT V IN 3V V 5% 5% t r < 2ns t f < 2ns V t ON().9 t OFF() FIGURE 2C. MEASUREMT POINTS FIGURE 2. ABLE ING TIMES FN3283 Rev 8. Page 6 of 17

7 G48, G49 Test Circuits and Waveforms (Continued) +2.4V ALL S AN A A G48 A 1 G49 A 2 GN, B V- +5V (V S ) 3V V V S 8% 8% t r < 2ns t f < 2ns pF V t OP FIGURE 3A. TEST CIRCUIT FIGURE 3B. MEASUREMT POINTS FIGURE 3. BREAK-BEFORE-MAKE INTERVAL R G S X 3V V V G CHANNEL SELECT A A 1 A 2 GN V- C L 1nF ON OFF IS THE MEASURE VOLTAGE UE TO CHARGE TRANSFER ERROR, Q Q = C L x FIGURE 4A. TEST CIRCUIT FIGURE 4. CHARGE INJECTION FIGURE 4B. MEASUREMT POINTS V 5V SIGNAL GERATOR V IN S X S 8 A 2 A 1 A V- 1k 1k V IN SIGNAL GERATOR S 1 S X S 8 A 2 A 1 A V- 1k GN GN ANALYZER ANALYZER UT OFF ISOLATION = 2 Log V IN UT CROSSTALK = 2 Log V IN FIGURE 5. OFF ISOLATION FIGURE 6. CROSSTALK FN3283 Rev 8. Page 7 of 17

8 G48, G49 Test Circuits and Waveforms (Continued) 5V 3R V V IN S 1 SIGNAL GERATOR A 2 A 1 A V- R L CHANNEL SELECT A 2 A 1 A V- S 1 S 8 IMPEANCE ANALYZER GN GN ANALYZER UT INSERTION LOSS = 2 Log V IN FIGURE 7. INSERTION LOSS FIGURE 8. SOURCE/RAIN CAPACITANCES Typical Applications Overvoltage Protection A very convenient form of overvoltage protection consists of adding two small signal diodes (1N4148, 1N914 type) in series with the supply pins (see Figure 9). This arrangement effectively blocks the flow of reverse currents. It also floats the supply pin above or below the normal or V- value. In this case the overvoltage signal actually becomes the power supply of the IC. From the point of view of the chip, nothing has changed, as long as the difference - (V-) doesn t exceed 44V. The addition of these diodes will reduce the analog signal range to 1V below and 1V above V-, but it preserves the low channel resistance and low leakage characteristics. Typical application information is for esign Aid Only, not guaranteed and not subject to production testing. V G S X V- 1N4148 G48 1N4148 FIGURE 9. OVERVOLTAGE PROTECTION USING BLOCKING IOES FN3283 Rev 8. Page 8 of 17

9 G48, G49 Typical Performance Curves = V- = C (ON) 2. 5 I IN (pa) 1. C S, (pf) C (OFF).5pA 25. C S(OFF) V IN (V) V A (V) FIGURE 1. CURRT vs VOLTAGE FIGURE 11. SOURCE/RAIN CAPACITANCE vs ANALOG VOLTAGE (SINGLE 12V SUPPLY) 8 6 = V- = C (ON) V SUPPLY = 15V V IN = V C S, (pf) 4 C (OFF) I IN (pa) C S(OFF) V A (V) FIGURE 12. SOURCE/RAIN CAPACITANCE vs ANALOG VOLTAGE TEMPERATURE ( C) FIGURE 13. CURRT vs TEMPERATURE G48 I (OFF) G49 I (OFF) G49 I (ON) G48 I (ON) 6 2 = 15V V- = V S = -V FOR I (OFF) V = V S(OP) FOR I (ON) I (pa) I (pa) V S = V FOR I (OFF) V S = V FOR I (ON) V (V) FIGURE 14. RAIN LEAKAGE CURRT vs SOURCE/RAIN VOLTAGE (SINGLE 12V SUPPLY) -1 G49 I (OFF) G49 I (ON) G48 I (ON), I (OFF) V S, V (V) FIGURE 15. RAIN LEAKAGE CURRT vs SOURCE/RAIN VOLTAGE FN3283 Rev 8. Page 9 of 17

10 G48, G49 Typical Performance Curves (Continued) = V- = I S(OFF) (pa) 5 V IN (V) = +12V V- = V V S (V) FIGURE 16. SOURCE LEAKAGE CURRT vs SOURCE VOLTAGE V SUPPLY ( V) FIGURE 17. ING THRESHOL vs SUPPLY VOLTAGE V SUPPLY = 15V V SUPPLY = 15V = 2.4V 1 2 -(I-) ( A) 1 2 I+ (ma) 1 1 = V 1 = 2.4V 1.1 = V.1 1 1K 1K 1K 1M 1M.1 1 1k 1k 1k 1M 1M ING FREQUCY (Hz) ING FREQUCY (Hz) FIGURE 18. NEGATIVE SUPPLY CURRT vs ING FREQUCY FIGURE 19. POSITIVE SUPPLY CURRT vs ING FREQUCY I+ V SUPPLY = 15V I+, I- (na) I- (na) (I-) -6 = 15V V- = V IN = V V = V TEMPERATURE ( C) FIGURE 2. I SUPPLY vs TEMPERATURE TEMPERATURE ( C) FIGURE 21. NEGATIVE SUPPLY CURRT vs TEMPERATURE FN3283 Rev 8. Page 1 of 17

11 G48, G49 Typical Performance Curves (Continued) 2 15 = 15V V- = V IN = V V = V C L = 1,pF V IN = 5V P-P = 15V V- = I+ ( A) 1 Q (pc) TEMPERATURE ( C) 1-1 = 12V V- = V V S (V) 15 FIGURE 22. POSITIVE SUPPLY CURRT vs TEMPERATURE (G48) FIGURE 23. CHARGE INJECTION vs ANALOG VOLTAGE V = 7.5V r S(ON) ( ) V 1V 12V r S(ON) ( ) V 12V 15V 2V 2 15V 2V V (V) V V- = V V (V) FIGURE 24. r S(ON) vs V AN SUPPLY FIGURE 25. r S(ON) vs V (SINGLE SUPPLY) = 15V V- = C r S(ON) ( ) C 85 C 25 C r S(ON) ( ) C 25 C 2 1 C -4 C -55 C V S (V) C 3-4 C = 12V -55 C V- = V V S (V) FIGURE 26. r S(ON) vs V S AN TEMPERATURE FIGURE 27. r S(ON) vs V S AN TEMPERATURE (SINGLE SUPPLY) FN3283 Rev 8. Page 11 of 17

12 G48, G49 Typical Performance Curves (Continued) = V- = R L = 1k (db) -9 OFF ISOLATION t (ns) t TRANS t OFF() -5 CROSSTALK 125 t ON() k 1k 1k 1M 1M 1M FREQUCY (Hz) FIGURE 28. OFF ISOLATION AN CROSSTALK vs FREQUCY V SUPPLY (V) FIGURE 29. ING TIME vs SINGLE SUPPLY 2 19 t TRANS 175 t TRANS t ON() t (ns) t (ns) t OFF() 1 11 t OFF() t ON() V SUPPLY ( V) FIGURE 3. ING TIME vs BIPOLAR SUPPLY V IN (V) FIGURE 31. ING TIME vs V IN (SINGLE SUPPLY) t TRANS R L = 1k t (ns) LOSS (db) = V- = REF. 1V RMS t OFF() -4 1 t ON() -5 R L = V IN (V) FIGURE 32. ING TIME vs V IN (BIPOLAR SUPPLY) FREQUCY (Hz) FIGURE 33. INSERTION LOSS vs FREQUCY FN3283 Rev 8. Page 12 of 17

13 G48, G49 ie Characteristics IE IMSIONS: 18 m x 332 m x 485 m METALLIZATION: Type: SiAl Thickness: 12kÅ 1kÅ PASSIVATION: Type: Nitride Thickness: 8kÅ 1kÅ WORST CASE CURRT SITY: 9.1 x 1 4 A/cm 2 Metallization Mask Layout G48 A A 1 A 2 GN (2) (1) (16) (15) (14) NC V- (3) (13) S 1 (4) (12) S 5 S 2 (5) (11) S 6 S 3 (6) NC S 4 (7) (8) (9) S 8 (1) S 7 FN3283 Rev 8. Page 13 of 17

14 G48, G49 ie Characteristics IE IMSIONS: 18 m x 332 m x 485 m METALLIZATION: Type: SiAl Thickness: 12kÅ 1kÅ PASSIVATION: Type: Nitride Thickness: 8kÅ 1kÅ WORST CASE CURRT SITY: 9.1 x 1 4 A/cm 2 Metallization Mask Layout G49 A A 1 GN (2) (1) (16) NC (15) NC V- (3) (14) S 1A (4) (13) S 1B S 2A (5) (12) S 2B S 3A (6) (11) S 3B S 4A (7) (8) A (9) B (1) S 4B FN3283 Rev 8. Page 14 of 17

15 G48, G49 Thin Shrink Small Outline Plastic Packages (TSSOP) N INEX AREA (.2) e.1(.4) M C A M E1 -B- -Ab -C- SEATING PLANE A B S E.25(.1) M B A1 NOTES: 1. These package dimensions are within allowable dimensions of JEEC MO-153-AB, Issue E. 2. imensioning and tolerancing per ANSI Y14.5M imension does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.15mm (.6 inch) per side. 4. imension E1 does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.15mm (.6 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. imension b does not include dambar protrusion. Allowable dambar protrusion shall be.8mm (.3 inch) total in excess of b dimension at maximum material condition. Minimum space between protrusion and adjacent lead is.7mm (.27 inch). 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) GAUGE PLANE.1(.4).25.1 A2 M L c M LEA THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A b c E e.26 BSC.65 BSC - E L N o 8 o o 8 o - Rev. 1 2/2 FN3283 Rev 8. Page 15 of 17

16 G48, G49 ual-in-line Plastic Packages (PIP) INEX AREA BASE PLANE SEATING PLANE 1 B1 -C- -A- N N/2 B e 1 E1 NOTES: 1. Controlling imensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. imensioning and tolerancing per ANSI Y14.5M Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No imensions A, A1 and L are measured with the package seated in JE- EC seating plane gauge GS-3. 5., 1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed.1 inch (.25mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. ambar protrusions shall not exceed.1 inch (.25mm). 9. N is the maximum number of terminal positions. 1. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of inch ( mm). -B- A1.1 (.25) M C A A2 L B S A e C E C L e A C e B E16.3 (JEEC MS-1-BB ISSUE ) 16 LEA UAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B , 1 C E E e.1 BSC 2.54 BSC - e A.3 BSC 7.62 BSC 6 e B L N Rev. 12/93 FN3283 Rev 8. Page 16 of 17

17 G48, G49 Small Outline Plastic Packages (SOIC) N INEX AREA e B.25(.1) M C A M E -B- -A- -C- SEATING PLANE A B S H.25(.1) M B A1.1(.4) NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number imensioning and tolerancing per ANSI Y14.5M imension does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.15mm (.6 inch) per side. 4. imension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.25mm (.1 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured.36mm (.14 inch) or greater above the seating plane, shall not exceed a maximum value of.61mm (.24 inch). 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. L M h x 45 C M16.15 (JEEC MS-12-AC ISSUE C) 16 LEA NARROW BOY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C E e.5 BSC 1.27 BSC - H h L N Rev. 1 6/5 Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN3283 Rev 8. Page 17 of 17