CA3262A, CA3262. Quad-Gated, Inverting Power Drivers. Features. Description. Ordering Information. Pinouts. August 1997

Transcription

1 Semiconductor CA6A, CA6 August 997 Quad-Gated, Inverting Power Drivers Features Independent Over-Current Limiting On Each Output Independent Over-Temperature Limiting On Each Output Output Drivers Capable of Switching 7mA Load Inputs Compatible With TTL or 5V CMOS Logic Suitable For Resistive, Lamp or Inductive Loads Power-Frame Package Construction For Good Heat Dissipation Operating Temperature Ranges - CA6A o C to 5 o C - CA o C to 85 o C Applications System Applications Solenoids Automotive Relays Appliances Lamps Industrial Controls Steppers Robotics Small Motors Displays Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NO. CA6E - to 85 6 Ld PDIP E6. CA6AE - to 5 6 Ld PDIP E6. CA6AQ - to 5 8 Ld PLCC N8.5 CA6AM - to 5 Ld SOIC (W) M. Description The CA6 and CA6A are used to interface low-level logic to high current loads. Each Power Driver has four inverting switches consisting of a non-inverting logic input stage and an inverting low-side driver output stage. All inputs are 5V TTL/CMOS logic compatible and have a common Enable input. Each output device has independent current limiting ( ) and thermal limiting ( ) for protection from over-load conditions. Steering diodes connected from each output (in pairs) to the Clamp pins may be used in conjunction with external zener diodes to protect the IC against over-voltage transients that result from inductive load switching. To allow for maximum heat transfer from the chip, all ground pins on the DIP, PLCC and SOIC packages are directly connected to the mounting pad of the chip. Integral heat spreading lead frames directly connect the bond pads and ground leads to conduct heat from the chip junction to the PC Board for good heat dissipation. The CA6 and CA6A can drive four incandescent lamp loads without modulating their brilliance when the cold lamps are energized. Outputs may be parallel connected to drive high current loads. The maximum output current of each output is determined by the over-current limiting threshold which is typically.a but may be as low as.7a. Pinouts OUT A OUT B CA6, CA6A (PDIP) TOP VIEW 6 5 IN A IN B INDEX CA6A (PLCC) TOP VIEW OUT B OUT A IN A IN B OUT A OUT B CA6A (SOIC) TOP VIEW PRELIMINARY IN A IN B OUT C OUT D IN C IN D OUT C OUT C OUT D IN D IN C IN C OUT D IN D CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright Harris Corporation 997 File Number 86.6

2 CA6A, CA6 Functional Block Diagram IN D V+ OUT D CONSTANT CURRENT SOURCES IN C OUT C INPUT REFEREE VOLTAGE.V IN B OUT B OUT A TO SUBSEQUENT STAGES FIGURE. CA6A EQUIVALENT SCHEMATIC OF ONE INPUT STAGE IN A TRUTH TABLE (Each Output) IN OUT H H L H L H L X H H = High, L = Low, X = Don t Care +5V P.S. V+ OUT D RELAY IN D V BATT OUT C IN C SOLENOID TTL OR CMOS LOGIC LEVEL INPUTS IN B OUT B V BATT HIGH CURRENT HIGH SIDE DR MOTOR OUT A V BATT IN A LAMP FIGURE. QUAD INVERTING POWER DRIVER (QDR) SHOWN WITH TYPICAL APPLICATION LOADS

3 CA6A, CA6 Absolute Maximum Ratings Logic Supply Voltage, V Logic Input Voltage, V IN V Output Voltage, V CEX V Output Sustaining Voltage, V CE(SUS) V Output Transient Current (Note ) Output Load Current (Note ) Operating Conditions Temperature Range CA6AE, CA6AQ, CA6AM o C to 5 o C CA6E o C to 85 o C Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) For PC Mount Without Added Copper Ground Area CA6E (PDIP) CA6AE (PDIP) CA6AQ (PLCC) CA6AM (SOIC) For PC Mount With sq. in. of Added Copper Ground Area CA6E (PDIP) CA6AE (PDIP) CA6AQ (PLCC) CA6AM (SOIC) See Maximum Power Dissipation vs Temperature curves, Figures 6A and 6B. Maximum Junction Temperature o C Maximum Storage Temperature Range o C to 5 o C Maximum Lead Temperature (Soldering s) o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications = 5.5V, T A = - o C to 5 o C for CA6A and = 5.5V, T A = - o C to 85 o C for CA6 Unless Otherwise Specified CA6 CA6A PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS Output Leakage Current I CEX V CE = 6V, V =.8V µa Output Sustaining V CE(SUS) Note V Voltage Collector Emitter V CE(SAT) V IN = V, =.75V Saturation Voltage I C = ma V (See Figures B and 5B) I C = ma V I C = ma V I C = ma V I C = 5mA V I C = 6mA V I C = 7mA, T A = - o C V Input Low Voltage V IL V Input High Voltage V IH V Input Low Current I IL V IN =.8V µa Input High Current I IH V IN = V = 5.5V, µa I C = 6mA Supply Current, All Outputs ON, (See Figures A and 5A) Supply Current, All Outputs OFF, (See Figures A and 5A) I CC(ON) I CC(OFF) V IN = V, V = 5.5V, I OUTA = 5mA, I OUTB = 5mA, I OUTC = 5mA, I OUTD = 5mA V IN = V (Note ) 55 ma (Note ) 5 ma Clamp Diode Leakage I R µa V Current R = 6V Clamp Diode Forward V F I F = A, V IN = V V Voltage, (See Figures D and 5D) I F =.5A, V IN = V V Turn-On Delay, t PHL, t PLH I OUT = 5mA µs (See Figures C and 5C) Over Current Limiting V OUT = V, V IN = 5.5V,.7 - (Note ).7 - (Note ) A V = 5.5V DESIGN PARAMETERS Over Temperature Limiting (Junction Temperature) o C

4 CA6A, CA6 Electrical Specifications = 5.5V, T A = - o C to 5 o C for CA6A and = 5.5V, T A = - o C to 85 o C for CA6 Unless Otherwise Specified (Continued) CA6 CA6A PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS Input Capacitance, Input C IN pf Enable Capacitance C EN pf NOTES:. The CA6 and CA6A have on-chip limiting for transient peak currents. Under short-circuit conditions with voltage applied to the collector of the output transistor and with the output transistor turned ON, the current will increase to.a, typical. Over-Current Limiting protects a short circuit condition for a normal operating range of output supply voltage. During a short circuit condition, the output driver will shortly thereafter (approx. 5ms) go into Over-Temperature Limiting. While Over-Current Limiting may range to peak currents greater than A, each output will typically withstand a direct short circuit up to supply voltage levels of 6V. Excessive dissipation before thermal limiting occurs may cause damage to the chip for supply voltages greater than 8V. The CA6 and CA6A are rated to withstand peak current, cold turn-on conditions of #68 or #9 lamp loads.. The total DC current for the CA6 and CA6A with all outputs ON should not exceed the total of ( x.7a + Max. I CC ) ~.85A. This level of current will significantly increase the chip temperature due to increased dissipation and may cause thermal shutdown in high ambient temperature conditions (See Absolute Maximum Ratings for Dissipation). Any one output may be allowed to exceed.7a but may be subject to Over-Current Limiting above the min. limit of.7a. As a practical limit, no single output should be loaded to more than A (Max).. Normal applications require a surface mount of the 8 lead PLCC and lead SOIC packages on a PC Board. The PLCC, SOIC and PDIP packages have power lead frame construction through the ground pins to conduct heat from the frame to the PC Board ground area. Thermal resistance, θ JA, is given for a surface mount of the 8 lead PLCC and the lead SOIC packages on a oz. copper PC board with minimal ground area and with square inches of ground area.. I CC varies with temperature. Typically, I CC(ON) is 8mA at 5 o C and ma at - o C. Typically, I CC(OFF) is.ma at 5 o C and.ma at - o C. 5. Tested with a switched-off 5mA Load of mh (with Ω series resistance), V BATT = V and the outputs (V CE ) clamped to +V maximum with an external zener diode. Applications Typical circuit configurations for applying the CA6 and CA6A are shown in the application circuit of Figure. To their rated capabilities, both circuits can be used to drive inductive, resistive and lamp loads. The CA6A has a lower V SAT than the CA6 and is rated for 5 o C ambient temperature applications. The CA6 data sheet rating is 85 o C. Otherwise, the protection features described apply to both the CA6 and CA6A. The maximum voltage for full load current switching is the output sustaining voltage, V CE(SUS) which should not exceed V. To provide a means of over-voltage protection, on-chip steering diodes are connected from each output to one of two pins. Over-voltage pulses may be generated from inductive load switching and must be clamped or limited to a peak voltage less than V CE(SUS). To limit an inductive voltage pulse, a zener diode should be connected to the appropriate pin. When the voltage pulse exceeds the zener threshold, the excess energy is dumped to ground via the on-chip steering diode and the external zener diode. The on-chip diodes may be used in a free-wheeling mode by connecting the pins to an external clamp supply voltage. Zener diode clamp protection is preferred over the power supply clamp option, primarily because the power supplies may be subject to large transient changes; including turn-on and turn-off conditions where non-tracking conditions between supplies could allow forward conduction through the steering diodes. For all transient conditions of either method, the clamp voltage should greater than the maximum supply voltage of the switching outputs and less than V CE(SUS). Note that the rate of change of the output current during load switching is fast. Therefore, even small values of inductance, including the inductance of a few meters of hook-up wire to the load circuit, can generate voltage spikes of considerable amplitude at the output terminals and may require clamping to protect the device ratings. Current-limiting is provided as protection for shorted or overloaded output conditions. Voltage is sampled across a small metal resistor in the emitter of each output stage. When the voltage exceeds a preset comparator level, drive is reduced to the output. Current limiting is sustained unless thermal conditions exceed the preset thermal shutdown temperature of 55 o C. If an output is shorted, the remaining three outputs will continue to function normally unless the continued heat spreading is sufficient to raise the junction temperature at any other output to a level greater than 55 o C. High ambient temperature conditions may allow this to happen. The degree of interaction is minimized at chip layout design by separating the output devices, each to a separate corner of the chip. As noted, the thermal resistance values of the PDIP, PLCC and SOIC packages are improved by direct connection of the leads to the chip mounting pad. For a normal PC Board application, the thermal resistance coefficient for each package can be significantly lowered by increasing ground copper area on the PC board next to the ground pins of the IC.

5 CA6A, CA6 I B CURRENT AMPLIFIER TEMP. SENSE CURRENT SENSE BANDGAP VOLT. REF. FIGURE. EACH OUTPUT POWER DRIVER IS A COMPOSITE CIRCUIT WITH OVER-TEMPERATURE SENSE FOR THERMAL LIMITING AND OVER-CURRENT SENSE TO PROVIDE CURRENITING Typical Performance Curves 8 7 SUPPLY VOLTAGE ( ) = 5.5V.7 SUPPLY VOLTAGE ( ) =.75V SUPPLY CURRENT (ma) 6 5 V IN = V, I OUT = 5mA (EACH) THERMAL SHUTDOWN COLLECTOR-TO-EMITTER SATURATION VOLTAGE (V) I C = 7mA I C = 6mA V IN = V, I OUT = ma FIGURE A. TYPICAL SUPPLY CURRENT (PIN ) CHARACTERISTICS FIGURE B. TYPICAL COLLECTOR-TO-EMITTER SATURATION VOLTAGE CHARACTERISTICS IN QUAD-GATED INVERTING POWER DRIVER OUTPUT PROPAGATION DELAY TIME (µs) t PHL V IN 9,, 5, 6 (6) (7) (7) (8) V OUT,, 6, 8 () () () () 5% 5% t PHL t PLH (ON) 5% (OFF) 5% t PLH DIODE FORWARD VOLTAGE (V) I F =.5A I F = A FIGURE C. TYPICAL PROPAGATION DELAY TIME CHARAC- TERISTICS FIGURE. TYPICAL CHARACTERISTICS OF THE CA6E FIGURE D. TYPICAL -DIODE FORWARD VOLTAGE CHARACTERISTICS 5

6 CA6A, CA6 Typical Performance Curves (Continued) 8 7 SUPPLY VOLTAGE ( ) = 5.5V.7 SUPPLY VOLTAGE ( ) =.75 I OUT = 6mA SUPPLY CURRENT (ma) 6 5 V IN HIGH I OUT = 5mA (EACH) V IN LOW I OUT = ma COLLECTOR-TO-EMITTER SATURATION VOLTAGE (V) FIGURE 5A. TYPICAL SUPPLY CURRENT (PIN ) CHARACTERISTICS FIGURE 5B. TYPICAL COLLECTOR-TO-EMITTER SATURATION VOLTAGE CHARACTERISTICS IN QUAD-GATED INVERTING POWER DRIVER OUTPUTS PROPAGATION DELAY TIME (µs) 9,, 5, 6 (6) (7) (7) (8),, 6, 8 () () () () V IN t PHL V OUT(ON) 5% 5% t PHL t PLH t PLH (OFF) DIODE FORWARD VOLTAGE (V) I F =.5A I F = A FIGURE 5C. TYPICAL PROPAGATION DELAY TIME CHARACTERISTICS FIGURE 5D. TYPICAL -DIODE FORWARD VOLTAGE CHARACTERISTICS FIGURE 5. TYPICAL CHARACTERISTICS OF THE CA6AE AND CA6AQ.5.5 PACKAGE DISSIPATION (W).5 PACKAGE DERATING WITHOUT HEAT SINK - CA6AQ (PLCC) - CA6AE (PDIP), CA6AM (SOIC) PACKAGE DISSIPATION (W).5 PACKAGE DERATING WITH SQ IHES OF COPPPER PC BOARD HEAT SINK AREA - CA6AQ (PLCC) - CA6AM (SOIC) - CA6AE (PDIP) FIGURE 6A. DISSIPATION RATING CHART FOR PLCC, PDIP AND SOIC PACKAGES WITHOUT ADDITIONAL HEAT SINKS FIGURE 6B. DISSIPATION RATING CHART FOR PLCC, PDIP AND SOIC PACKAGES WITH SQ. IN. OF COPPER PC BOARD HEAT SINKING 6

7 Dual-In-Line Plastic Packages (PDIP) CA6A, CA6 INDEX AREA BASE PLANE SEATING PLANE D B N N/ B D e D -C- -A- NOTES:. Controlling Dimensions: IH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y.5M-98.. Symbols are defined in the MO Series Symbol List in Section. of Publication No Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS-. 5. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.5mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.5mm). 9. N is the maximum number of terminal positions.. Corner leads (, N, N/ and N/ + ) for E8., E6., E8., E8., E.6 will have a B dimension of. -.5 inch (.76 -.mm). E -B- A. (.5) M C A A L B S A e C E C L e A e B C E6. (JEDEC MS--BB ISSUE D) 6 LEAD DUAL-IN-LINE PLASTIC PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B , C D D E E e. BSC.5 BSC - e A. BSC 7.6 BSC 6 e B L N Rev. /9 7

8 . (.7).8 (.) PIN () IDENTIFIER. (.5) MAX PLCS C L D D.6 (.66). (.8). (.7).56 (.).5 (.7) TP E E C L A A. (.). (.5) CA6A, CA6 Plastic Leaded Chip Carrier Packages (PLCC). (.) C.5 (.6).5 (.) R D/E D/E VIEW A. (.5) MIN SEATING PLANE N8.5 (JEDEC MS-8AB ISSUE A) 8 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A D D D , 5 E E E , 5 N Rev. /95 -C-.5 (.6).5 (.) MIN MIN VIEW A TYP. NOTES:. Controlling dimension: IH. Converted millimeter dimensions are not necessarily exact.. Dimensions and tolerancing per ANSI Y.5M-98.. Dimensions D and E do not include mold protrusions. Allowable mold protrusion is. inch (.5mm) per side.. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. N is the number of terminal positions. 8

9 Small Outline Plastic Packages (SOIC) CA6A, CA6 N INDEX AREA e D B.5(.) M C A M E -B- -A- -C- SEATING PLANE A B S H.5(.) M B A.(.) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 95.. Dimensioning and tolerancing per ANSI Y.5M-98.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.5mm (.6 inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.5mm (. inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured.6mm (. inch) or greater above the seating plane, shall not exceed a maximum value of.6mm (. inch). Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α L M h x 5 o C M. (JEDEC MS--AD ISSUE C) LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e.5 BSC.7 BSC - H h L N 7 α o 8 o o 8 o - Rev. /9 9

10 This datasheet has been downloaded from: Datasheets for electronic components.