For Reference Only FEATURES
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1 BiMOS II -BIT SERIAL INPUT, LATCHED SOURCE DRIVERS Data Sheet 262.4D GROUND UCN55A CLOCK 2 CLK SHIFT REGISTER V DD 5 SERIAL 4 ST LATCHES OE V BB 4 OUT OUT 2 OUT OUT 4 SERIAL DATA OUT LOGIC SUPPLY OUTPUT ENABLE Note the UCN55A (DIP) and the A55SLW (SOIC) are electrically identical and share a common terminal number assignment. ABSOLUTE MAXIMUM RATINGS at T A = +25 C Output Voltage, V OUT V Logic Supply Voltage Range, V DD V to 2 V Driver Supply Voltage Range, V BB V to 50 V Input Voltage Range, V IN V to V DD + 0. V Continuous Output Current, I OUT ma Allowable Package Power Dissipation, P D See Graph Operating Temperature Range, T A C to +5 C Storage Temperature Range, T S C to +50 C The UCN55A, UCN55EP, and A55SLW BiMOS II serialinput, latched source drivers are designed for applications emphasizing low output saturation voltages and currents to -250 ma per output. These smart high-side octal, driver ICs merge an -bit CMOS shift register, associated CMOS latches, and CMOS control logic (strobe and output enable) with medium current emitter-follower (sourcing) outputs. Typical applications include incandescent or LED displays (both directly driven and multiplexed), non-impact (i.e., thermal) printers, relays, and solenoids. Each device is suitable for high-side applications to -250 ma per channel. The maximum supply voltage is 50 V and a minimum output sustaining voltage rating of 5 V for inductive load applications. Under normal operating conditions, the UCN55A and UCN55EP are capable of providing -20 ma ( outputs continuous and simultaneous) at +65 C with a logic supply of 5 V. Similar devices, with higher output current ratings, are the UCN50A and UCN5A. BiMOS II devices can operate at greatly improved data-input rates. With a 5 V supply, they will typically operate at better than 5 MHz. At 2 V, significantly higher speeds are obtained. The CMOS inputs provide for minimum loading and are compatible with standard CMOS, PMOS, and NMOS circuits. TTL or DTL circuits may require the use of appropriate pull-up resistors to ensure a proper input-logic high. A CMOS serial data output allows cascading these devices in multiple drive-line applications required by many dot matrix, alphanumeric, and bar graph displays. These devices are rated for continuous operation over the temperature range of -20 C to +5 C. Because of limitations on package power dissipation, the simultaneous operation of all output drivers may require a reduction in duty cycle. The UCN55A is supplied in a standard -pin dual in-line plastic package with a copper lead frame for increased allowable package power dissipation. The UCN55EP is supplied in a 20-lead plastic leaded chip carrier for minimum area, surface-mount applications. The A55SLW is supplied in a -lead wide-body plastic SOIC. For Reference Only DISCONTINUED PRODUCT Caution: CMOS devices have input-static protection, but are susceptible to damage when exposed to extremely high static electrical charges. 2 0 LOAD SUPPLY OUT OUT 7 OUT 6 OUT 5 Dwg. PP-026-2A FEATURES Low Output-Saturation Voltage Source Outputs to 50 V Output Current to -250 ma To. MHz Data-lnput Rate Low-Power CMOS Logic & Latches Always order by complete part number, e.g., UCN55A.
2 -BIT SERIAL-INPUT, ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS SUFFIX 'EP', R = 5 C/W θja SUFFIX 'A', R θja = 60 C/W SUFFIX 'LW', R θja = 0 C/W AMBIENT TEMPERATURE IN C CLOCK SERIAL GROUND MOS BIPOLAR FUNCTIONAL BLOCK DIAGRAM -BIT SERIAL-PARALLEL SHIFT REGISTER LATCHES OUT OUT 2 OUT OUT 4 OUT 5 OUT 6 OUT 7 OUT SERIAL DATA OUT V DD OUTPUT ENABLE V BB Dwg. GP Dwg. No. A-2,654 TYPICAL INPUT CIRCUIT V DD IN UCN55EP Dwg. EP-00-4A TYPICAL OUTPUT DRIVER Dwg. No. A-4,6 Dwg. No. A-2,655 5 Northeast Cutoff, Box 506 Worcester, Massachusetts (50) Copyright 5, 2004 Allegro MicroSystems, Inc.
3 -BIT SERIAL-INPUT, ELECTRICAL CHARACTERISTICS at T A = +25 C, V BB = 50 V, V DD = 5 V and 2 V (unless otherwise noted). Limits Characteristic Symbol Test Conditions Min. Max. Units Output Leakage Current I OUT T A = +25 C -50 µa T A = +70 C -00 µa Output Saturation Voltage V CE(SAT) I OUT = -60 ma. V I OUT = -20 ma.2 V Output Sustaining Voltage V CE(sus) I OUT = -20 ma, L = 2 mh 5 V Input Voltage V IN() V DD = 5.0 V.5 5. V V DD = 2 V V V IN(0) V DD = 5 V to 2 V V Input Current I IN() V DD = V IN = 5.0 V 50 µa V DD = V IN = 2 V 240 µa Input lmpedance z IN V DD = 5.0 V 00 kω V DD = 2 V 50 kω Max. Clock Frequency f CLK. MHz Serial Data-Output r OUT V DD = 5.0 V 20 kω Resistance V DD = 2 V 6.0 kω Turn-ON Delay t PLH Output Enable to Output, I OUT = -20 ma 2.0 µs Turn-OFF Delay t PHL Output Enable to Output, I OUT = -20 ma 0 µs Supply Current I BB All outputs ON, All outputs open 0 ma All outputs OFF 200 µa I DD V DD = 5 V, All outputs OFF, Inputs = 0 V 00 µa V DD = 2 V, All outputs OFF, Inputs = 0 V 200 µa V DD = 5 V, One output ON, All inputs = 0 V.0 ma V DD = 2 V, One output ON, All inputs = 0 V.0 ma Diode Leakage Current I R V R = 25 V, T A = +25 C 50 µa V R = 25 V, T A = +70 C 00 µa Diode Forward Voltage V F I F = 20 ma 2.0 V
4 -BIT SERIAL-INPUT, CLOCK A B D C E F BLANKING G OUT N TIG CONDITIONS (V DD = 5.0 V, Logic Levels are V DD and Ground) Dwg. No. A-2,64A A. Minimum Data Active Time Before Clock Pulse (Data Set-Up Time) ns B. Minimum Data Active Time After Clock Pulse (Data Hold Time) ns C. Minimum Data Pulse Width ns D. Minimum Clock Pulse Width ns E. Minimum Time Between Clock Activation and Strobe ns F. Minimum Strobe Pulse Width ns G. Typical Time Between Strobe Activation and Output Transition....0 µs Serial Data present at the input is transferred to the shift register on the logic 0 to logic transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to its respective latch when the is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the is held high. Applications where the latches are bypassed ( tied high) will require that the OUTPUT ENABLE input be high during serial data entry. When the OUTPUT ENABLE input is high, all of the output buffers are disabled (OFF) without affecting the information stored in the latches or shift register. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches. 5 Northeast Cutoff, Box 506 Worcester, Massachusetts (50)
5 -BIT SERIAL-INPUT, TYPICAL APPLICATION UCN55A + 2 V DATA OUT FOR > SEGMENTS PER DIGIT CLOCK 2 SHIFT REGISTER V DD OE 5 4 OUTPUT ENABLE (ACTIVE LOW) 4 LATCHES V BB UCN52A TO OTHER SEGMENTS CLOCK C V DATA OUT SHIFT REGISTER LATCHES 4 2 TO OTHER DIGITS OUTPUT ENABLE 7 0 Dwg. No. B-54 TRUTH TABLE Serial Shift Register Contents Serial Latch Contents Output Contents Data Clock Data Strobe Output Input Input I I 2 I... I N- I N Output Input I I 2 I... I N- I N Enable I I 2 I... I N- I N H H R R 2... R N-2 R N- R N- L L R R 2... R N-2 R N- R N- X R R 2 R... R N- R N R N X X X... X X X L R R 2 R... R N- R N P P 2 P... P N- P N P N H P P 2 P... P N- P N L P P 2 P... P N- P N X X X... X X H L L L... L L L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
6 -BIT SERIAL-INPUT, UCN55A Dimensions in Inches (controlling dimensions) MAX MAX Dimensions in Millimeters (for reference only) Dwg. MA-00-A in MAX MAX NOTES: Lead thickness is measured at seating plane or below. 2. Lead spacing tolerance is non-cumulative.. Exact body and lead configuration at vendor s option within limits shown. Dwg. MA-00-A mm 5 Northeast Cutoff, Box 506 Worcester, Massachusetts (50)
7 -BIT SERIAL-INPUT, UCN55EP Dimensions in Inches (controlling dimensions) INDEX AREA Dwg. MA A in Dimensions in Millimeters (for reference only) INDEX AREA NOTES:. Lead spacing tolerance is non-cumulative. 2. Exact body and lead configuration at vendor s option within limits shown. Dwg. MA A mm
8 -BIT SERIAL-INPUT, A55SLW Dimensions in Inches (for reference only) TO Dwg. MA-00-A in Dimensions in Millimeters (controlling dimensions) TO NOTES: Lead spacing tolerance is non-cumulative. 2. Exact body and lead configuration at vendor s option within limits shown. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design Dwg. MA-00-A of its products. mm The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 5 Northeast Cutoff, Box 506 Worcester, Massachusetts (50)
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