High Voltage Latch-Up Proof, Single SPST Switch ADG5401

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1 ata heet FEATURE Latch-up immune under all circumstances Human body model (HBM) E rating: kv Low on resistance: 6.5 Ω ±9 V to ±22 V dual-supply operation 9 V to V single-supply operation V supply maximum ratings Fully specified at ±5 V, ±2 V, +2 V, and +36 V V to V analog signal range APPLICATION High voltage signal routing Automatic test equipment Analog front-end circuits Precision data acquisition Amplifier gain select Industrial instrumentation Relay replacement GENERAL ECRIPTION The AG5 is a monolithic industrial, complementary metal oxide semiconductor (CMO) analog switch containing a latchup immune single-pole/single-throw (PT) switch. The switch conducts equally well in both directions when on, and has an input signal range that extends to the power supplies. In the off condition, signal levels up to the supplies are blocked. The ultralow on resistance and on-resistance flatness of these switches make them ideal solutions for data acquisition and gain switching applications, where low distortion is critical. The latch-up immune construction and high E rating make these switches more robust in harsh environments. High Voltage Latch-Up Proof, ingle PT witch AG5 FUNCTIONAL BLOCK IAGRAM AG5 WITCHE HOWN FOR A LOGIC INPUT Figure. PROUCT HIGHLIGHT. Trench isolation guards against latch-up. A dielectric trench separates the P channel and N channel transistors, thereby preventing latch-up even under severe overvoltage conditions. 2. Low RON of 6.5 Ω. 3. ual-supply operation. For applications where the analog signal is bipolar, the AG5 can operate from dual supplies of up to ±22 V.. ingle-supply operation. For applications where the analog signal is unipolar, the AG5 can operate from a singlerail power supply of up to V V logic compatible digital inputs: VINH = 2. V, VINL =. V. 6. No VL logic power supply required. 7. Available in -lead MOP package and -lead, 2 mm 3 mm LFCP packages. IN 72- Rev. A ocument Feedback Information furnished by Analog evices is believed to be accurate and reliable. However, no responsibility is assumed by Analog evices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. pecifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog evices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U..A. Tel: Analog evices, Inc. All rights reserved. Technical upport

2 AG5 TABLE OF CONTENT Features... Applications... Functional Block iagram... General escription... Product Highlights... Revision History... 2 pecifications... 3 ±5 V ual upply... 3 ±2 V ual upply... 2 V ingle upply V ingle upply... 6 ata heet Continuous Current per Channel, or...7 Absolute Maximum Ratings... E Caution... Pin Configurations and Function escriptions...9 Typical Performance Characteristics... Test Circuits... 3 Terminology... 5 Applications Information... 6 Trench Isolation... 6 Outline imensions... 7 Ordering Guide... 7 REVIION HITORY /5 Rev. to Rev. A Added -Lead LFCP... Universal Changed Continuous Current, or Parameter to -Lead MOP, Table Added Figure 2; Renumbered equentially... 9 Changes to Table Changes to Figure... Added Figure Changes to Figure 2 and Figure Added AC Power upply Rejection Ratio (ACPRR), Terminology ection... 5 Added Figure 3, Outline imensions... 7 Changes to Ordering Guide /3 Revision : Initial Version Rev. A Page 2 of 7

3 ata heet AG5 PECIFICATION ±5 V UAL UPPLY V = +5 V ± %, V = 5 V ± %, GN = V, unless otherwise noted. Table. Parameter 25 C C to +5 C C to +25 C Unit Test Conditions/Comments ANALOG WITCH Analog ignal Range V to V V On Resistance, RON 6.5 Ω typ V = ± V, I = ma; see Figure 2 2 Ω max V = +3.5 V, V = 3.5 V On-Resistance Flatness, RFLAT (ON) Ω typ V = ± V, I = ma..7 2 Ω max LEAKAGE CURRENT V = +6.5 V, V = 6.5 V ource Off Leakage, I (Off ) ±. na typ V = ± V, V = V; see Figure 2 ±.5 ±2 ±2 na max rain Off Leakage, I (Off ) ±. na typ V = ± V, V = V; see Figure 2 ±.5 ±2 ±2 na max Channel On Leakage, I (On), I (On) ±.2 na typ V = V = ± V; see Figure 23 ± ± ± na max IGITAL INPUT Input High Voltage, VINH 2. V min Input Low Voltage, VINL. V max Input Current, IINL or IINH.2 µa typ VIN = VGN or V ±. µa max igital Input Capacitance, CIN 6 pf typ YNAMIC CHARACTERITIC ton 6 ns typ RL = 3 Ω, CL = 35 pf ns max V = V; see Figure 26 toff 75 ns typ RL = 3 Ω, CL = 35 pf ns max V = V; see Figure 26 Charge Injection, QINJ 22 pc typ V = V, R = Ω, CL = nf; see Figure 27 Off Isolation 5 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 22 Total Harmonic istortion + Noise (TH + N). % typ RL = kω, 5 V p-p, f = 2 Hz to 2 khz; see Figure 2 3 db Bandwidth 7 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 25 Insertion Loss. db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 25 C (Off ) 22 pf typ V = V, f = MHz C (Off ) 2 pf typ V = V, f = MHz C (On), C (On) 75 pf typ V = V, f = MHz POWER REQUIREMENT V = +6.5 V, V = 6.5 V I 5 µa typ igital inputs = V or V 55 7 µa max I. µa typ igital inputs = V or V µa max V/V ±9/±22 V min/v max GN = V Guaranteed by design; not subject to production test. Rev. A Page 3 of 7

4 AG5 ata heet ±2 V UAL UPPLY V = +2 V ± %, V = 2 V ± %, GN = V, unless otherwise noted. Table 2. Parameter 25 C C to +5 C C to +25 C Unit Test Conditions/Comments ANALOG WITCH Analog ignal Range V to V V On Resistance, RON 6 Ω typ V = ±5 V, I = ma; see Figure Ω max V = + V, V = V On-Resistance Flatness, RFLAT (ON).2 Ω typ V = ±5 V, I = ma Ω max LEAKAGE CURRENT V = +22 V, V = 22 V ource Off Leakage, I (Off ) ±. na typ V = ±5 V, V = 5 V; see Figure 2 ±.5 ±2 ±2 na max rain Off Leakage, I (Off ) ±. na typ V = ±5 V, V = 5 V; see Figure 2 ±.5 ±2 ±2 na max Channel On Leakage, I (On), I (On) ±.2 na typ V = V = ±5 V; see Figure 23 ± ± ± na max IGITAL INPUT Input High Voltage, VINH 2. V min Input Low Voltage, VINL. V max Input Current, IINL or IINH.2 µa typ VIN = VGN or V ±. µa max igital Input Capacitance, CIN 6 pf typ YNAMIC CHARACTERITIC ton 5 ns typ RL = 3 Ω, CL = 35 pf ns max V = V; see Figure 26 toff 7 ns typ RL = 3 Ω, CL = 35 pf ns max V = V; see Figure 26 Charge Injection, QINJ 275 pc typ V = V, R = Ω, CL = nf; see Figure 27 Off Isolation 5 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 22 Total Harmonic istortion + Noise (TH + N). % typ RL = kω, 2 V p-p, f = 2 Hz to 2 khz; see Figure 2 3 db Bandwidth 7 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 25 Insertion Loss.5 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 25 C (Off ) 2 pf typ V = V, f = MHz C (Off ) 23 pf typ V = V, f = MHz C (On), C (On) 75 pf typ V = V, f = MHz POWER REQUIREMENT V = +22 V, V = 22 V I 5 µa typ igital inputs = V or V 7 µa max I. µa typ igital inputs = V or V µa max V/V ±9/±22 V min/v max GN = V Guaranteed by design; not subject to production test. Rev. A Page of 7

5 ata heet AG5 2 V INGLE UPPLY V = 2 V ± %, V = V, GN = V, unless otherwise noted. Table 3. Parameter 25 C C to +5 C C to +25 C Unit Test Conditions/Comments ANALOG WITCH Analog ignal Range V to V V On Resistance, RON Ω typ V = V to V, I = ma; see Figure Ω max V =. V, V = V On-Resistance Flatness, RFLAT (ON) 2. Ω typ V = V to V, I = ma Ω max LEAKAGE CURRENT V = +3.2 V, V = V ource Off Leakage, I (Off ) ±. na typ V = V to V, V = V to V; see Figure 2 ±.5 ±2 ±2 na max rain Off Leakage, I (Off ) ±. na typ V = V to V, V = V to V; see Figure 2 ±.5 ±2 ±2 na max Channel On Leakage, I (On), I (On) ±.2 na typ V = V = V to V; see Figure 23 ± ± ± na max IGITAL INPUT Input High Voltage, VINH 2. V min Input Low Voltage, VINL. V max Input Current, IINL or IINH.2 µa typ VIN = VGN or V ±. µa max igital Input Capacitance, CIN 6 pf typ YNAMIC CHARACTERITIC ton 26 ns typ RL = 3 Ω, CL = 35 pf ns max V = V; see Figure 26 toff 2 ns typ RL = 3 Ω, CL = 35 pf ns max V = V; see Figure 26 Charge Injection, QINJ 95 pc typ V = 6 V, R = Ω, CL = nf; see Figure 27 Off Isolation 5 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 22 Total Harmonic istortion + Noise (TH + N).2 % typ RL = kω, 6 V p-p, f = 2 Hz to 2 khz; see Figure 2 3 db Bandwidth 9 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 25 Insertion Loss.9 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 25 C (Off ) 2 pf typ V = 6 V, f = MHz C (Off ) 3 pf typ V = 6 V, f = MHz C (On), C (On) 6 pf typ V = 6 V, f = MHz POWER REQUIREMENT V = 3.2 V I µa typ igital inputs = V or V 5 65 µa max V 9/ V min/v max GN = V, V = V Guaranteed by design; not subject to production test. Rev. A Page 5 of 7

6 AG5 ata heet 36 V INGLE UPPLY V = 36 V ± %, V = V, GN = V, unless otherwise noted. Table. Parameter 25 C C to +5 C C to +25 C Unit Test Conditions/Comments ANALOG WITCH Analog ignal Range V to V V On Resistance, RON 7 Ω typ V = V to 3 V, I = ma; see Figure Ω max V = 32. V, V = V On-Resistance Flatness, RFLAT (ON). Ω typ V = V to 3 V, I = ma Ω max LEAKAGE CURRENT V = V, V = V ource Off Leakage, I (Off ) ±. na typ V = V to 3 V, V = 3 V to V; see Figure 2 ±.5 ±2 ±2 na max rain Off Leakage, I (Off ) ±. na typ V = V to 3 V, V = 3 V to V; see Figure 2 ±.5 ±2 ±2 na max Channel On Leakage, I (On), I (On) ±.2 na typ V = V = V to 3 V; see Figure 23 ± ± ± na max IGITAL INPUT Input High Voltage, VINH 2. V min Input Low Voltage, VINL. V max Input Current, IINL or IINH.2 µa typ VIN = VGN or V ±. µa max igital Input Capacitance, CIN 6 pf typ YNAMIC CHARACTERITIC ton 6 ns typ RL = 3 Ω, CL = 35 pf ns max V = V; see Figure 26 toff ns typ RL = 3 Ω, CL = 35 pf ns max V = V; see Figure 26 Charge Injection, QINJ 255 pc typ V = V, R = Ω, CL = nf; see Figure 27 Off Isolation 5 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 22 Total Harmonic istortion + Noise (TH + N). % typ RL = kω, V p-p, f = 2 Hz to 2 khz; see Figure 2 3 db Bandwidth 7 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 25 Insertion Loss.55 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 25 C (Off ) 26 pf typ V = V, f = MHz C (Off ) 2 pf typ V = V, f = MHz C (On), C (On) 65 pf typ V = V, f = MHz POWER REQUIREMENT V = 39.6 V I µa typ igital inputs = V or V 3 µa max V 9/ V min/v max GN = V, V = V Guaranteed by design; not subject to production test. Rev. A Page 6 of 7

7 ata heet AG5 CONTINUOU CURRENT PER CHANNEL, OR Table 5. Parameter 25 C 5 C 25 C Unit Test Condition/Comments -LEA MOP θja = 33. C/W V = 5 V, V = 5 V ma maximum V = 2 V, V = 2 V ma maximum V = 2 V, V = V ma maximum V = 36 V, V = V 7 ma maximum -LEA LFCP θja = 6. C/W V = 5 V, V = 5 V ma maximum V = 2 V, V = 2 V ma maximum V = 2 V, V = V ma maximum V = 36 V, V = V ma maximum Rev. A Page 7 of 7

8 AG5 ata heet ABOLUTE MAXIMUM RATING TA = 25 C, unless otherwise noted. Table 6. Parameter Rating V to V V V to GN.3 V to + V V to GN +.3 V to V Analog Inputs V.3 V to V +.3 V or 3 ma, whichever occurs first igital Inputs V.3 V to V +.3 V or 3 ma, whichever occurs first Peak Current, or Pin 63 ma (pulsed at ms, % duty cycle maximum) Continuous Current, or 2 ata + 5% Temperature Range Operating C to +25 C torage 65 C to +5 C Junction Temperature 5 C Thermal Impedance, θja -Lead MOP (-Layer Board) 33. C/W -Lead LFCP 6. C/W Reflow oldering Peak As per JEEC J-T-2 Temperature, Pb Free Human Body Model (HBM) E kv Overvoltages at the IN,, and pins are clamped by internal diodes. Limit current to the maximum ratings given. 2 ee Table 5. tresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Only one absolute maximum rating can be applied at any one time. E CAUTION Rev. A Page of 7

9 ata heet AG5 PIN CONFIGURATION AN FUNCTION ECRIPTION NC GN V 2 3 AG5 TOP VIEW (Not to cale) 7 V 6 IN 5 NC NOTE. NC = NO CONNECT. NOT INTERNALLY CONNECTE. 2. THE EXPOE PA I TIE TO UBTRATE, V NC 2 GN 3 V AG5 TOP VIEW (Not to cale) 7 6 V IN NC NOTE. NC = NO CONNECT. NOT INTERNALLY CONNECTE Figure 2. -Lead LFCP Pin Configuration Figure 3. -Lead MOP Pin Configuration Table 7. Pin Function escriptions Pin No. -Lead LFCP -Lead MOP Mnemonic escription ource Terminal. This pin can be an input or output. 2 2 NC No Connect. Not internally connected. 3 3 GN Ground ( V) Reference. V Most Positive Power upply Potential. 5 5 NC No Connect. Not internally connected. 6 6 IN Logic Control Input. 7 7 V Most Negative Power upply Potential. rain Terminal. This pin can be an input or output. Not applicable EPA The exposed pad is tied to substrate, V. Table. Truth Table IN witch Condition On Off Rev. A Page 9 of 7

10 AG5 ata heet TYPICAL PERFORMANCE CHARACTERITIC ON REITANCE (Ω) T A = 25 C ±3.5V ±5.V ±6.5V ±.V ±2.V ±22.V ON REITANCE (Ω) C +5 C +25 C C V, V (V) Figure. On Resistance as a Function of V, V (ual upply) V, V (V) Figure 7. On Resistance as a Function of V (V) for ifferent Temperatures, ±2 V ual upply 72-6 ON REITANCE (Ω) T A = 25 C +.V +2.V +3.2V +32.V +36.V +39.6V ON REITANCE (Ω) C +5 C +25 C C V, V (V) Figure 5. On Resistance as a Function of V, V (ingle upply) Figure. On Resistance as a Function of V (V) for ifferent Temperatures, 2 V ingle upply 2 V, V (V) C +5 C +25 C C +25 C +5 C +25 C C ON REITANCE (Ω) 6 ON REITANCE (Ω) V, V (V) Figure 6. On Resistance as a Function of V (V) for ifferent Temperatures, ±5 V ual upply V, V (V) Figure 9. On Resistance as a Function of V (V) for ifferent Temperatures, 36 V ingle upply 72- Rev. A Page of 7

11 ata heet AG5 LEAKAGE CURRENT (na) I (OFF) + I (OFF) + I (OFF) + I (OFF) + I, I (ON) + + I, I (ON) LEAKAGE CURRENT (na) I (OFF) + I (OFF) + I (OFF) + I (OFF) + I, I (ON) + + I, I (ON) TEMPERATURE ( C) Figure. Leakage Currents as a Function of Temperature, ±5 V ual upply TEMPERATURE ( C) Figure 3. Leakage Currents as a Function of Temperature, 36 V ingle upply 72-2 LEAKAGE CURRENT (na) I (OFF) + I (OFF) + I (OFF) + I (OFF) + I, I (ON) + + I, I (ON) OFF IOLATION (db) 2 6 T A = 25 C V = +5V V = 5V TEMPERATURE ( C) Figure. Leakage Currents as a Function of Temperature, ±2 V ual upply k k k M M M G FREQUENCY (Hz) Figure. Off Isolation vs. Frequency LEAKAGE CURRENT (na).6..2 I (OFF) + I (OFF) + I (OFF) + I (OFF) + I, I (ON) + + I, I (ON) CHARGE INJECTION (pc) V = 5V, V = 5V V = 2V, V = 2V V = 2V, V = V V = 36V, V = V TEMPERATURE ( C) Figure 2. Leakage Currents as a Function of Temperature, 2 V ingle upply V (V) Figure 5. Charge Injection vs. ource Voltage (V) 72- Rev. A Page of 7

12 AG5 ata heet.5. T A = 25 C 3 25 TH + N (%).3.2. V = 2V, V = V, V = 6V p-p V = 36V, V = V, V = V p-p V = 5V, V = 5V, V = 5V p-p V = 2V, V = 2V, V = 2V p-p TIME (ns) V = 2V, V = V = 36V, V = V V = 5V, V = 5V V = 2V, V = 2V FREQUENCY (khz) Figure 6. TH + N vs. Frequency TEMPERATURE ( C) Figure. ttranition Times vs. Temperature 72-7 OFF IOLATION (db) T A = 25 C V = +5V V = 5V ACPRR (db) 2 6 T A = 25 C V = +5V V = 5V NO ECOUPLING CAPACITOR..5 ECOUPLING CAPACITOR 5. k k M M M G FREQUENCY (Hz) k k k M M FREQUENCY (Hz) 72-9 Figure 7. Bandwidth Figure 9. ACPRR vs. Frequency Rev. A Page 2 of 7

13 ata heet AG5 TET CIRCUIT I (OFF) A I (OFF) A NC I (ON) A V Figure 2. Off Leakage V 72- NC = NO CONNECT Figure 23. On Leakage V 72-2 V.µFV.µF V V AUIO PRECIION R V IN V V p-p V IN GN R L kω V OUT I V R ON = V I Figure 2. On Resistance 72-9 Figure 2. TH + N V.µFV.µF V.µFV.µF V V NETWORK ANALYZER V V NETWORK ANALYZER V IN IN GN 5Ω 5Ω R L 5Ω V V OUT V IN IN GN 5Ω R L 5Ω V V OUT Figure 22. Off Isolation OFF IOLATION = 2 log V OUT V 72-2 V OUT WITH WITCH INERTION LO = 2 log V OUT WITHOUT WITCH Figure 25. Bandwidth V.µFV.µF V V 3V V IN V AG5 5% 5% V OUT V IN GN R L 3Ω C L 35pF V V OUT V t ON.9 V 9%. V t OFF 72-2 Figure 26. witching Times, ton and toff Rev. A Page 3 of 7

14 AG5 ata heet V V R V V V OUT V IN AG5 ON OFF V IN C L nf GN V OUT Figure 27. Charge Injection Q INJ = C L V OUT V OUT Rev. A Page of 7

15 ata heet TERMINOLOGY I I represents the positive supply current. I I represents the negative supply current. V, V V and V represent the analog voltage on Terminal and Terminal, respectively. RON RON is the ohmic resistance between Terminal and Terminal. RFLAT (ON) RFLAT (ON) represents the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. I (Off) I (Off) is the source leakage current with the switch off. I (Off) I (Off) is the drain leakage current with the switch off. I (On), I (On) I (On) and I (On) represent the channel leakage currents with the switch on. VINL VINL is the maximum input voltage for Logic. VINH VINH is the minimum input voltage for Logic. IINL, IINH IINL and IINH represent the low and high input currents of the digital inputs. C (Off) C (Off) represents the off switch drain capacitance, which is measured with reference to ground. AG5 C (Off) C (Off) represents the off switch source capacitance, which is measured with reference to ground. C (On), C (On) C (On) and C (On) represent the on switch capacitances, which are measured with reference to ground. CIN CIN represents digital input capacitance. ton ton represents the delay time between the 5% and 9% points of the digital input and switch on condition. toff toff represents the delay time between the 5% and 9% points of the digital input and switch off condition. Off Isolation Off isolation is a measure of unwanted signal coupling through an off channel. Charge Injection Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. Bandwidth Bandwidth is the frequency at which the output is attenuated by 3 db from its dc value. Total Harmonic istortion + Noise (TH + N) The ratio of the harmonic amplitude plus noise of the signal to the fundamental is represented by TH + N. AC Power upply Rejection Ratio (ACPRR) ACPRR measures the ability of the device to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of.62 V p-p. The ratio of the amplitude of the signal on the output to the amplitude of the modulation is the ACPRR (see Figure 9). Rev. A Page 5 of 7

16 AG5 ata heet APPLICATION INFORMATION The AG5xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. The AG5 high voltage switch allows single-supply operation from 9 V to V and dual-supply operation from ±9 V to ±22 V. The AG5 (as well as other select devices within this family) achieves an kv human body model E rating, which provides a robust solution, eliminating the need for separate protection circuitry designs in some applications. TRENCH IOLATION In the AG5, an insulating oxide layer (trench) is placed between the NMO and the PMO transistors of each CMO switch. Parasitic junctions, which occur between the transistors in junction-isolated switches, are eliminated, and the result is a latch-up immune switch. In junction isolation, the N and P wells of the PMO and NMO transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode can become forward-biased. The two transistors form a silicon-controlled rectifier (CR) type circuit, causing a significant amplification of the current that, in turn, leads to latch-up. With trench isolation, this diode is removed, and the result is a latch-up immune switch. TRENCH NMO PMO P-WELL N-WELL BURIE OXIE LAYER HANLE WAFER Figure 2. Trench Isolation Rev. A Page 6 of 7

17 ata heet AG5 OUTLINE IMENION PIN IENTIFIER.65 BC COPLANARITY MAX 6 5 MAX.23.9 COMPLIANT TO JEEC TANAR MO-7-AA Figure 29. -Lead Mini mall Outline Package [MOP] (RM-) imensions shown in millimeters B 2. BC EATING PLANE INEX AREA.5 TOP VIEW IE VIEW BC.2 MIN REF COPLANARITY..5 MAX.2 NOM EXPOE PA BOTTOM VIEW Figure 3. -Lead Lead Frame Chip cale Package [LFCP_W] 2 mm 3 mm Body, Very Very Thin, ual Lead (CP--) imensions shown in millimeters PIN INICATOR FOR PROPER CONNECTION OF THE EXPOE PA, REFER TO THE PIN CONFIGURATION AN FUNCTION ECRIPTION ECTION OF THI ATA HEET. 6-A ORERING GUIE Model Temperature Range Package escription Package Option Branding AG5BRMZ C to +25 C -Lead Mini mall Outline Package [MOP] RM- 2M AG5BRMZ-RL7 C to +25 C -Lead Mini mall Outline Package [MOP] RM- 2M AG5BCPZ-RL7 C to +25 C -Lead Lead Frame Chip cale Package [LFCP_W] CP-- BR Z = RoH Compliant Part Analog evices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 72--/5(A) Rev. A Page 7 of 7

Low Capacitance, Low Charge Injection, ±15 V/+12 V icmos SPST in SOT-23 ADG1201/ADG1202

Low Capacitance, Low Charge Injection, ±15 V/+12 V icmo PT in OT-23 AG121/AG122 FEATURE 2.4 pf off capacitance