Low Cost 6-Channel HD/SD Video Filter ADA4420-6

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1 Low Cost 6-Channel HD/SD Video Filter FEATURES Sixth-order filters Transparent input sync tip clamp 1 db bandwidth of 26 MHz typical for HD HD 75 MHz: 48 db typical NTSC differential gain:.19% NTSC differential phase:.76 Rail-to-rail outputs Low quiescent current: 32 ma typical Disable feature Output dc offset APPLICATIONS Set-top boxes DVD players and recorders HDTVs Projectors Personal video recorders GENERAL DESCRIPTION The is a low cost video reconstruction filter specifically designed for consumer applications. It consists of six independent sixth-order Butterworth filters/buffers, three for standard definition (Y/C or CVBS) and three for high definition component signals (YPrPb or RGB). The operates from a single 5 V supply and has a low quiescent current of 32 ma, making it ideal for applications where power consumption is critical. A disable feature allows for further power conservation by reducing the supply current to less than 8 μa typical when the device is not in use. INSD1 INSD2 INSD3 DIS INHD1 INHD2 INHD3 FUNCTIONAL BLOCK DIAGRAM CLAMP CLAMP CLAMP CLAMP CLAMP CLAMP Figure 1. SD SD SD HD HD HD OUTSD1 OUTSD2 OUTSD3 OUTHD1 OUTHD2 OUTHD3 Each channel features a transparent sync tip clamp, allowing ac coupling of the inputs without requiring dc restoration. The output drivers on the have rail-to-rail output capabilities with 6 db gain. A built-in offset of 25 mv allows the outputs to be dc-coupled, eliminating the need for large coupling capacitors. Each output is capable of driving two 75 Ω doubly terminated cables. The is available in either a 16-lead QSOP or a 2-lead TSSOP, and operates in the extended industrial temperature range of 4 C to +85 C Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 916, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 * PRODUCT PAGE QUICK LINKS Last Content Update: 2/23/217 COMPARABLE PARTS View a parametric search of comparable parts. DOCUMENTATION Data Sheet : Low Cost 6-Channel HD/SD Video Filter Data Sheet DESIGN RESOURCES Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints DISCUSSIONS View all EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

3 TABLE OF CONTENTS Features... 1 Applications... 1 General Description... 1 Functional Block Diagram... 1 Revision History... 2 Specifications... 3 Absolute Maximum Ratings... 4 Thermal Resistance... 4 Maximum Power Dissipation... 4 ESD Caution... 4 Pin Configuration and Function Descriptions... 5 Typical Performance Characteristics...7 Test Circuits... 1 Applications Information Overview Disable Input and Output Coupling Printed Circuit Board (PCB) Layout Video Encoder Reconstruction Filter Outline Dimensions Ordering Guide REVISION HISTORY 5/11 Rev. to Rev. A Added 2-Lead TSSOP Package...Universal Changes to General Description Section... 1 Changes to Disable Assert Voltage, Disable Assert Time, Disable De-Assert Time Parameters... 3 Changes to Table 3, Maximum Power Dissipation Section, and Figure Added Figure 4 and Table Changes to Figure 18, Figure 19, and Figure Updated Outline Dimensions Changes to Ordering Guide /8 Revision : Initial Version Rev. A Page 2 of 16

4 SPECIFICATIONS VS = 5 V, TA = 25 C, VO = 2. V p-p, RL = 15 Ω, dc-coupled inputs, ac-coupled outputs, unless otherwise noted. See Figure 18, Figure 19, and Figure 2 for the test circuits. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit OVERALL PERFORMANCE DC Voltage Gain All channels db Input Voltage Range, All Inputs to 2.1 V Output Voltage Range, All Outputs.25 to 4.6 V Linear Output Current per Channel 3 ma Filter Input Bias Current 1 μa SD CHANNEL DYNAMIC PERFORMANCE 1 db Bandwidth 8.6 MHz 3 db Bandwidth MHz Out-of-Band Rejection f = 27 MHz db Crosstalk f = 1 MHz 68 db Total Harmonic Distortion f = 1 MHz, VO = 1.4 V p-p, dc-coupled outputs.2 % Signal-to-Noise Ratio f = 1 khz to 6 MHz, unweighted 7 db Propagation Delay 57 ns Group Delay Variation f = 1 khz to 5 MHz 16 ns Differential Gain NTSC; ac-coupled inputs, dc-coupled outputs;.19 % see Figure 19 Differential Phase NTSC; ac-coupled inputs, dc-coupled outputs;.76 Degrees see Figure 19 HD CHANNEL DYNAMIC PERFORMANCE 1 db Bandwidth 26 MHz 3 db Bandwidth MHz Out-of-Band Rejection f = 75 MHz db Crosstalk f = 1 MHz 68 db Total Harmonic Distortion f = 1 MHz, VO = 1.4 V p-p, dc-coupled outputs.57 % Signal-to-Noise Ratio f = 1 khz to 3 MHz, unweighted 66 db Propagation Delay 15 ns Group Delay Variation f = 1 khz to 3 MHz 11 ns DC CHARACTERISTICS Operating Voltage 4.75 to 5.25 V Quiescent Supply Current Active, DIS = ma Disabled, DIS = 7 13 μa PSRR HD channel, referred to output db SD channel, referred to output 4 45 db Output DC Offset All channels mv Disable Assert Voltage DIS = to V Disable Assert Time DIS = to 1 2 ns Disable De-Assert Time DIS = 1 to 45 ns Disable Input Bias Current Disabled, DIS = 6.8 μa Input-to-Output Isolation Disabled, DIS =, f = 5 MHz 96 db Rev. A Page 3 of 16

5 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage 5.5 V Power Dissipation See Figure 2 Storage Temperature Range 65 C to +125 C Operating Temperature Range 4 C to +85 C Lead Temperature (Soldering, 1 sec) 3 C Junction Temperature 15 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is specified for the device soldered to a high thermal conductivity 4-layer (2s2p) circuit board, as described in EIA/JESD Table 3. Package Type θja θjc Unit 16-Lead QSOP C/W 2-Lead TSSOP C/W MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 15 C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the. Exceeding a junction temperature of 15 C for an extended time can result in changes in the silicon devices, potentially causing failure. The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The power dissipated due to load drive depends on the particular application. For each output, the power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. The power dissipated due to the loads is equal to the sum of the power dissipations due to each individual load. RMS voltages and currents must be used in these calculations. Airflow increases heat dissipation, effectively reducing θja. Figure 2 shows the maximum power dissipation in the package vs. the ambient temperature for the 16-lead QSOP (15 C/W) and the 2-lead TSSOP (143 C/W) on a JEDEC standard 4-layer board. θja values are approximate. MAXIMUM POWER DISSIPATION (W) ESD CAUTION 16-LEAD QSOP 2-LEAD TSSOP AMBIENT TEMPERATURE ( C) Figure 2. Maximum Power Dissipation vs. Ambient Temperature for a 4-Layer Board Rev. A Page 4 of 16

6 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INSD OUTSD1 INSD OUTSD2 INSD3 VCC DIS INHD TOP VIEW (Not to Scale) OUTSD3 GND GND OUTHD1 INHD2 7 1 OUTHD2 INHD3 8 9 OUTHD3 Figure Lead QSOP Pin Configuration Table Pin QSOP Pin Function Descriptions Pin No. Mnemonic Description 1 INSD1 Standard Definition Input 1 2 INSD2 Standard Definition Input 2 3 INSD3 Standard Definition Input 3 4 VCC Power Supply 5 DIS Disable/Power-Down Input 6 INHD1 High Definition Input 1 7 INHD2 High Definition Input 2 8 INHD3 High Definition Input 3 9 OUTHD3 High Definition Output 3 1 OUTHD2 High Definition Output 2 11 OUTHD1 High Definition Output 1 12 GND Ground 13 GND Ground 14 OUTSD3 Standard Definition Output 3 15 OUTSD2 Standard Definition Output 2 16 OUTSD1 Standard Definition Output 1 Rev. A Page 5 of 16

7 INSD1 1 2 OUTSD1 INSD OUTSD2 INSD OUTSD3 NC 4 17 GND VCC DIS 5 6 TOP VIEW (Not to Scale) GND NC INHD OUTHD1 INHD OUTHD2 INHD OUTHD3 NC 1 11 NC NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Figure 4. 2-Lead TSSOP Pin Configuration Table 5. 2-lead TSSOP Pin Function Descriptions Pin No. Mnemonic Description 1 INSD1 Standard Definition Input 1. 2 INSD2 Standard Definition Input 2. 3 INSD3 Standard Definition Input 3. 4 NC Do not connect to this pin. 5 VCC Power Supply. 6 DIS Disable/Power Down Input. 7 INHD1 High Definition Input 1. 8 INHD2 High Definition Input 2. 9 INHD3 High Definition Input 3. 1 NC Do not connect to this pin. 11 NC Do not connect to this pin. 12 OUTHD3 High Definition Output OUTHD2 High Definition Output OUTHD1 High Definition Output NC No Connection. 16 GND Ground. 17 GND Ground. 18 OUTSD3 Standard Definition Output OUTSD2 Standard Definition Output 2. 2 OUTSD1 Standard Definition Output 1. Rev. A Page 6 of 16

8 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25 C, VO = 2. V p-p, RL = 15 Ω, dc-coupled inputs, ac-coupled outputs, unless otherwise noted. See Figure 18, Figure 19, and Figure 2 for the test circuits. GAIN (db) SD CHANNELS, R L = 15Ω HD CHANNELS, R L = HD CHANNELS, R L = 15Ω SD CHANNELS, R L = NORMALIZED GAIN (db) SD CHANNELS, R L = SD CHANNELS, R L = 15Ω HD CHANNELS, R L = HD CHANNELS, R L = 15Ω Figure 5. Frequency Response vs. Load (RL) Figure 8. Flatness vs. Load (RL) GAIN (db) HD 4 C 6 HD +25 C HD +85 C SD 4 C 7 SD +25 C SD +85 C Figure 6. Frequency Response vs. Temperature NORMALIZED GAIN (db) HD 4 C HD +25 C HD +85 C 2.5 SD 4 C SD +25 C SD +85 C Figure 9. Flatness vs. Temperature HD DC-COUPLED HD AC-COUPLED GAIN (db) 3 4 GAIN (db) SD V O = 1mV p-p 7 SD V O = 2.V p-p HD V O = 1mV p-p HD V O = 2.V p-p Figure 7. Frequency Response vs. Amplitude SD AC-COUPLED 7 SD DC-COUPLED Figure 1. Frequency Response vs. Output Coupling Rev. A Page 7 of 16

9 1 6 GROUP DELAY (ns) SD CHANNELS HD CHANNELS DIS VOLTAGE (V) HD CHANNELS SD CHANNELS Figure 11. Group Delay vs. Frequency TIME (ns) Figure 13. Enable Time k DIS = OUTPUT IMPEDANCE (Ω) 1k 1 SUPPLY CURRENT (ma) Figure 12. Output Impedance vs. Frequency TEMPERATURE ( C) Figure 14. Supply Current vs. Temperature Rev. A Page 8 of 16

10 CROSSTALK (db) SD CHANNELS HD CHANNELS OUTPUT SATURATION VOLTAGE (V) Figure 15. Crosstalk vs. Frequency TEMPERATURE ( C) Figure 17. Output Saturation Voltage vs. Temperature DIS VOLTAGE (V) SD CHANNELS HD CHANNELS TIME (ns) Figure 16. Disable Time Rev. A Page 9 of 16

11 TEST CIRCUITS AGILENT E3631A POWER SUPPLY +6V + + ±25V COM VCC TEST CIRCUIT (SEE FIGURE 18) VCC GND DIS.1µF 1µF INxDx OUTxDx 5Ω V IN 49.9Ω 118Ω 22µF 86.6Ω V OUT BIAS CONNECT PORT 1 PORT 1 PORT 2 DIS GND Figure 18. DC-Coupled Input, AC-Coupled Output AGILENT 8753D VECTOR NETWORK ANALYZER Figure 2. Test Circuit for Frequency Response and Group Delay VCC.1µF 1µF V IN 49.9Ω.1µF 118Ω 86.6Ω V OUT DIS GND Figure 19. AC-Coupled Input, DC-Coupled Output Rev. A Page 1 of 16

12 APPLICATIONS INFORMATION OVERVIEW With its high impedance inputs and high output drive, the is ideally suited to video reconstruction and antialias filtering applications. The high impedance inputs give designers flexibility with regard to how the input signals are terminated. Devices with DAC current source outputs that feed the can be loaded in whatever resistance provides the best performance, and devices with voltage outputs can be optimally terminated as well. The outputs can each drive up to two source-terminated, 75 Ω loads and; therefore, can directly drive the outputs from set-top boxes and DVDs without the need for a separate output buffer. DISABLE The includes a disable feature that can be used to save power when a particular device is not in use. When disabled, the typically draws only 7 μa from the supply. The disable feature is asserted by pulling the DIS pin low. Table 6 summarizes the operation of the disable feature. Table 6. Disable Function DIS Pin Connection VCC or Floating GND Status Enabled Disabled INPUT AND OUTPUT COUPLING Inputs to the can be ac- or dc-coupled. For dc-coupled inputs, the signal must be completely contained within the input range of V to 2.1 V. When using ac-coupled inputs, the lowest point of the signal is clamped to approximately V. The outputs can be either ac- or dc-coupled. When driving single ac-coupled loads in standard 75 Ω video distribution systems, a minimum capacitance of 22 μf is recommended to avoid line and field droop. There are two ac coupling options when driving two loads from one output. One option simply uses the same value capacitor on the second load, while the other option uses a common coupling capacitor that is at least twice the value used for the single load (see Figure 21 and Figure 22). When driving two parallel 15 Ω loads (75 Ω effective load), the 3 db bandwidth of the filters typically varies from that of the filters with a single 15 Ω load (see Figure 5). 22µF 22µF CABLE CABLE Figure 21. Driving Two AC-Coupled Loads with Two Coupling Capacitors 47µF CABLE CABLE Figure 22. Driving Two AC-Coupled Loads with One Common Coupling Capacitor PRINTED CIRCUIT BOARD (PCB) LAYOUT As with all high speed applications, attention to the PCB layout is of paramount importance. When designing with the, adhere to standard high speed layout practices. A solid ground plane is recommended, and surface-mount, ceramic power supply decoupling capacitors should be placed as close as possible to the supply pins. Connect all of the GND pins to the ground plane with traces that are as short as possible. Controlled impedance traces of the shortest length possible should be used to connect to the signal I/O pins and should not pass over any voids in the ground plane. A 75 Ω impedance level is typically used in video applications. When driving transmission lines, include series termination resistors on the signal outputs of the. When the receives its inputs from a device with current outputs, the required load resistor value for the output current is often different from the characteristic impedance of the signal traces. In this case, if the interconnections are short (<<.1 wavelength), the trace does not have to be terminated in its characteristic impedance. Traces of 75 Ω can be used in this instance, provided their lengths are an inch or two at most. This is easily achieved because the and the device feeding it are usually adjacent to each other, and connections can be made that are less than one inch in length. VIDEO ENCODER RECONSTRUCTION FILTER The is easily applied as a reconstruction filter at the DAC outputs of a video encoder. Figure 23 illustrates how to use the in this type of application following an ADV734x series video encoder, with a single-supply and ac-coupled outputs Rev. A Page 11 of 16

13 ADV734x MULTIFORMAT VIDEO ENCODER DAC 1 3Ω INHD1 1 HD 2 OUTHD1 22μF + Y DAC 2 3Ω INHD2 1 HD 2 22μF OUTHD2 + Pb DAC 3 3Ω INHD3 DIS 1 HD 2 22μF OUTHD3 + Pr DAC 4 3Ω INSD1 1 SD 2 22μF OUTSD1 + CVBS R SET1 R SET2 DAC 5 DAC 6 3Ω 3Ω INSD2 INSD3 1 SD 2 1 SD 2 22μF OUTSD2 + 22μF OUTSD3 + S-VIDEO 4.12kΩ 4.12kΩ Figure 23. The Applied as a Reconstruction Filter Following an ADV734x Series Video Encoder Rev. A Page 12 of 16

14 OUTLINE DIMENSIONS.197 (5.).193 (4.9).189 (4.8) (4.1).154 (3.91).15 (3.81).244 (6.2).236 (5.99).228 (5.79).65 (1.65).49 (1.25).69 (1.75).53 (1.35).1 (.25).6 (.15).2 (.51).1 (.25).1 (.25).4 (.1) COPLANARITY.4 (.1).25 (.64) BSC.12 (.3).8 (.2) SEATING PLANE 8.5 (1.27).16 (.41).41 (1.4) REF COMPLIANT TO JEDEC STANDARDS MO-137-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches and (millimeters) A BSC.15.5 PIN 1 COPLANARITY.1.65 BSC MAX SEATING PLANE.45 COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure Lead Thin Shrink Small Outline Package [TSSOP] (RU-2) Dimensions shown in millimeters Rev. A Page 13 of 16

15 ORDERING GUIDE Model 1 Temperature Range Package Description Package Option Ordering Quantity ARQZ 4 C to +85 C 16-Lead Shrink Small Outline Package (QSOP) RQ-16 Tube (98) ARQZ-R7 4 C to +85 C 16-Lead Shrink Small Outline Package (QSOP) RQ-16 1, ARQZ-RL 4 C to +85 C 16-Lead Shrink Small Outline Package (QSOP) RQ-16 2,5 ARUZ 4 C to +85 C 2-Lead Thin Shrink Small Outline Package (TSSOP) RU-2 Tube (75) ARUZ-R7 4 C to +85 C 2-Lead Thin Shrink Small Outline Package (TSSOP) RU-2 1, ARUZ-RL 4 C to +85 C 2-Lead Thin Shrink Small Outline Package (TSSOP) RU-2 2,5 1 Z = RoHS Compliant Part. Rev. A Page 14 of 16

16 NOTES Rev. A Page 15 of 16

ADA Integrated Triple Video Filter and Buffer with Selectable Cutoff Frequencies and Multiplexed Inputs for RGB, HD/SD FUNCTIONAL BLOCK DIAGRAM

ADA Integrated Triple Video Filter and Buffer with Selectable Cutoff Frequencies and Multiplexed Inputs for RGB, HD/SD FUNCTIONAL BLOCK DIAGRAM Integrated Triple Video Filter and Buffer with Selectable Cutoff Frequencies and Multiplexed Inputs for RGB, HD/SD ADA4411-3 FEATURES Sixth-order adjustable video filters 36 MHz, 18 MHz, and 9 MHz Many