Low Cost, Precision JFET Input Operational Amplifiers ADA4000-1/ADA4000-2/ADA4000-4

Transcription

1 Low Cost, Precision JFET Input Operational Amplifiers ADA-/ADA-/ADA- FEATURES High slew rate: V/μs Fast settling time Low offset voltage:.7 mv maximum Bias current: pa maximum ± V to ±8 V operation Low voltage noise: 6 nv/ Hz Unity gain stable Common-mode voltage includes +VS Wide bandwidth: 5 MHz APPLICATIONS Reference gain/buffers Level shift/driving Active filters Power line monitoring/control Current/voltage sense or monitoring Data acquisition Sample-and-hold circuits Integrators GENERAL DESCRIPTION The ADA-/ADA-/ADA- are JFET input operational amplifiers featuring precision, very low bias current, and low power. Combining high input impedance, low input bias current, wide bandwidth, fast slew rate, and fast settling time, the ADA-/ADA-/ADA- are ideal amplifiers for driving analog-to-digital inputs and buffering digital-to-analog converter outputs. The input common-mode voltage includes the positive power supply, which makes the part an excellent choice for high-side signal conditioning. Additional applications for the ADA-/ADA-/ ADA- include electronic instruments, ATE amplification, buffering, integrator circuits, instrumentation-quality photodiode amplification, and fast precision filters (including PLL filters). The parts also include utility functions, such as reference buffering, level shifting, control I/O interface, power supply control, and monitoring functions. PIN CONFIGURATIONS OUT V +IN 3 ADA- TOP VIEW (Not to Scale) 5 V+ IN Figure. 5-Lead TSOT (UJ-5) NC IN +IN 3 V OUT A IN A +IN A 3 V OUT A IN A +IN A 3 V ADA- TOP VIEW (Not to Scale) 8 NC 7 V+ 6 OUT 5 NC NC = NO CONNECT Figure. 8-Lead SOIC (R-8) ADA- TOP VIEW (Not to Scale) V 7 OUT B 6 IN B 5 +IN B Figure 3. 8-Lead SOIC (R-8) ADA- TOP VIEW (Not to Scale) 8 +V 7 OUT B 6 IN B 5 +IN B Figure. 8-Lead MSOP (RM-8) OUT A OUT D IN A 3 IN D +IN A 3 ADA- +IN D +V TOP VIEW V +IN B 5 (Not to Scale) +IN C IN B 6 9 IN C OUT B 7 8 OUT C Figure 5. -Lead SOIC (R-) OUT A OUT D IN A +IN A +V +IN B IN B OUT B ADA- TOP VIEW (Not to Scale) IN D +IN D V +IN C IN C OUT C Figure 6. -Lead TSSOP (RU-) Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 ADA-/ADA-/ADA- TABLE OF CONTENTS Features... Applications... General Description... Pin Configurations... Revision History... Specifications... 3 Electrical Characteristics... 3 Absolute Maximum Ratings... 5 Thermal Resistance... 5 Power Sequencing...5 ESD Caution...5 Typical Performance Characteristics...6 Applications... Output Phase Reversal and Input Noise... Capacitive Load Drive... Settling Time... Outline Dimensions... Ordering Guide... REVISION HISTORY 3/9 Rev. to Rev. A Changes to Input Voltage Range Parameter... Changes to Common-Mode Rejection Ration Parameter... Updated Outline Dimensions... Changes to Ordering Guide... 5/7 Revision : Initial Version Rev. A Page of 6

3 ADA-/ADA-/ADA- SPECIFICATIONS ELECTRICAL CHARACTERISTICS VS = ±5. V, VCM = VS/ V, TA = 5 C, unless otherwise specified. Table. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS..7 mv C TA +5 C 3. mv Input Bias Current IB 5 pa C TA +85 C 7 pa C TA +5 C.5 na Input Offset Current IOS pa C TA +85 C 8 pa C TA +5 C 5 pa Input Voltage Range IVR +5 V Common-Mode Rejection Ratio CMRR V VCM +5 V 8 db C TA +5 C db Open-Loop Gain AVO RL = kω, VO = ± V db Offset Voltage Drift ΔVOS/ΔT C TA +5 C μv/ C OUTPUT CHARACTERISTICS Output Voltage High VOH RL = kω to ground V C TA +5 C 3. V Output Voltage Low VOL RL = kω to ground V C TA +5 C.8 V Short-Circuit Current ISC ±8 ma POWER SUPPLY Power Supply Rejection Ratio PSRR VS = ±. V to ±8. V 8 9 db Supply Current/Amplifier ISY ma C TA +5 C.8 ma DYNAMIC PERFORMANCE Slew Rate SR VI = V, RL = kω V/μs Gain Bandwidth Product GBP 5 MHz Phase Margin ΦM 6 Degrees NOISE PERFORMANCE Voltage Noise en p-p. Hz to Hz μv p-p Voltage Noise Density en f = khz 6 nv/ Hz Current Noise Density in f = khz. pa/ Hz INPUT IMPEDANCE Differential Mode (R C)IN-DIFF GΩ pf Common Mode (R C)INCM GΩ pf Rev. A Page 3 of 6

4 ADA-/ADA-/ADA- VS = ±5 V, VCM = VS/ V, TA = 5 C, unless otherwise specified. Table. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS..7 mv C TA +5 C 3. mv Input Bias Current IB 5 pa C TA +85 C 7 pa C TA +5 C 3 na Input Offset Current IOS pa C TA +85 C 8 pa C TA +5 C 5 pa Input Voltage Range IVR. +5. V Common-Mode Rejection Ratio CMRR. V VCM +5. V 7 8 db C TA +5 C 8 db Open-Loop Gain AVO RL = kω, VO = ±.5 V 6 db Offset Voltage Drift ΔVOS/ΔT C TA +5 C μv/ C OUTPUT CHARACTERISTICS Output Voltage High VOH RL = kω to ground.. V C TA +5 C 3.8 V Output Voltage Low VOL RL = kω to ground V C TA +5 C 3. V Short-Circuit Current ISC ±8 ma POWER SUPPLY Supply Current/Amplifier ISY.5.65 ma C TA +5 C.8 ma DYNAMIC PERFORMANCE Slew Rate SR VI = V, RL = kω V/μs Gain Bandwidth Product GBP 5 MHz Phase Margin ΦM 55 Degrees NOISE PERFORMANCE Voltage Noise en p-p. Hz to Hz μv p-p Voltage Noise Density en f = khz 6 nv/ Hz Current Noise Density in f = khz. pa/ Hz INPUT IMPEDANCE Differential Mode (R C)IN-DIFF GΩ pf Common Mode (R C)INCM GΩ pf Rev. A Page of 6

5 ADA-/ADA-/ADA- ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Supply Voltage ±8 V Input Voltage ±V supply Differential Input Voltage ±V supply Output Short-Circuit Duration to GND Indefinite Storage Temperature Range 65 C to +5 C Operating Temperature Range C to +5 C Junction Temperature Range 65 C to +5 C Lead Temperature (Soldering, sec) 3 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table. Thermal Resistance Package Type θja θjc Unit 5-Lead TSOT (UJ-5) C/W 8-Lead SOIC (R-8) C/W 8-Lead MSOP (RM-8) C/W -Lead SOIC (R-) C/W -Lead TSSOP (RU-) 3.3 C/W POWER SEQUENCING The op amp supply voltages must be established simultaneously with, or before, any input signals are applied. If this is not possible, the input current must be limited to ma. ESD CAUTION Rev. A Page 5 of 6

6 ADA-/ADA-/ADA- TYPICAL PERFORMANCE CHARACTERISTICS 5 5 V CM = V 5 5 V CM = V NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS OFFSET VOLTAGE (mv) Figure 7. Input Offset Voltage Distribution, VS = ±5 V OFFSET VOLTAGE (mv) Figure. Input Offset Voltage Distribution, VS = ±5 V NUMBER OF AMPLIFIERS 8 6 NUMBER OF AMPLIFIERS TCV OS (µv/ C) Figure 8. Offset Voltage Drift Distribution, VS = ±5 V TCV OS (µv/ C) Figure. Offset Voltage Drift Distribution, VS = ±5 V C L = 35pF C L = 35pF 8 35 GAIN (db) PHASE MARGIN (Degrees) GAIN (db) PHASE MARGIN (Degrees) k k k M M FREQUENCY (Hz) 5 M Figure 9. Open-Loop Gain and Phase Margin vs. Frequency, VS = ±5 V 579- k k k M M FREQUENCY (Hz) 5 M Figure. Open-Loop Gain and Phase Margin vs. Temperature, VS = ±5 V 579- Rev. A Page 6 of 6

7 ADA-/ADA-/ADA- 8 CMRR (db) 8 6 CMRR (db) 6 k k k M M FREQUENCY (Hz) Figure 3. Common-Mode Rejection Ratio vs. Frequency, VS = ±5 V k k k M FREQUENCY (Hz) M Figure 6. Common-Mode Rejection Ratio vs. Frequency, VS = ±5 V 579- VOLTAGE (V) A V = + R L = kω VOLTAGE (V) 3 A V = R L = kω 3 5 TIME (µs/div) TIME (µs/div) Figure. Large Signal Transient Response, VS = ±5 V C L = 3pF A V = + VOLTAGE (mv/div) Figure 7. Large Signal Transient Response, VS = ±5 V C L = 3pF A V = + VOLTAGE (mv/div) TIME (µs/div) Figure 5. Small Signal Transient Response, VS = ±5 V TIME (µs/div) Figure 8. Small Signal Transient Response, VS = ±5 V 579- Rev. A Page 7 of 6

8 ADA-/ADA-/ADA NO LOAD INPUT BIAS CURRENT (pa).5..5 SUPPLY CURRENT (ma) ±5 ±6 ±7 ±8 ±9 ± ± ± ±3 ± ±5 SUPPLY VOLTAGE (V) Figure 9. Input Bias Current vs. Supply Voltage ± ±5 ±6 ±7 ±8 ±9 ± ± ± ±3 ± ±5 SUPPLY VOLTAGE (V) Figure. Supply Current vs. Supply Voltage V OL INPUT BIAS CURRENT (pa) OUTPUT VOLTAGE (V) 8 6 V OH V OL V OH TEMPERATURE ( C) Figure. Input Bias Current vs. Temperature LOAD CURRENT (ma) Figure 3. Output Voltage vs. Load Current , ±5V SUPPLY CURRENT (ma) PSRR (db) 8 6 PSRR+ PSRR TEMPERATURE ( C) Figure. Supply Current vs. Temperature 579- k k k M M FREQUENCY (Hz) Figure. PSRR vs. Frequency 579- Rev. A Page 8 of 6

9 ADA-/ADA-/ADA-, ±5V.6, ±5V VOLTAGE NOISE DENSITY (nv/ Hz) V p-p (µv).... k k FREQUENCY (Hz) TIME (Seconds) Figure 5. Voltage Noise Density vs. Frequency Figure 8.. Hz to Hz Input Voltage Noise 5 A V = +, ±5V Z OUT (Ω) 8 6 A v = + CLOSED-LOOP GAIN (db) 3 A V = + A V = + A v = + A v = + k k k M M FREQUENCY (Hz) Figure 6. Output Impedance vs. Frequency M k k k M M M FREQUENCY (Hz) Figure 9. Closed-Loop Gain vs. Frequency V IN = mv p-p, ±5V R L = A V = + OVERSHOOT (%) 3 +OVERSHOOT OVERSHOOT 6 LOAD CAPACITANCE (pf) Figure 7. Overshoot vs. Load Capacitance Rev. A Page 9 of 6

10 ADA-/ADA-/ADA- APPLICATIONS OUTPUT PHASE REVERSAL AND INPUT NOISE Phase reversal is a change of polarity in the transfer function of the amplifier. This can occur when the voltage applied at the input of the amplifier exceeds the maximum common-mode voltage. Phase reversal happens when the part is configured in the gain of. Most JFET amplifiers invert the phase of the input signal if the input exceeds the common-mode input. Phase reversal is a temporary behavior of the ADA-x family. Each part returns to normal operation by bringing back the commonmode voltage. The cause of this effect is saturation of the input stage, which leads to the forward-biasing of a drain-gate diode. In noninverting applications, a simple fix for this is to insert a series resistor between the input signal and the noninverting terminal of the amplifier. The value of the resistor depends on the application, because adding a resistor adds to the total input noise of the amplifier. The total noise density of the circuit is where: ntotal ( inrs ) ktrs e = e n + + en is the input voltage noise density of the part. in is the input current noise density of the part. RS is the source resistance at the noninverting terminal. k is Boltzmann s constant (.38 3 J/K). T is the ambient temperature in Kelvin (T = 73 + C). In general, it is good practice to limit the input current to less than 5 ma to avoid driving a great deal of current into the amplifier inputs. CAPACITIVE LOAD DRIVE The ADA-/ADA-/ADA- are stable at all gains in both inverting and noninverting configurations. The parts are capable of driving up to pf of capacitive loads without oscillations in unity gain configurations. However, as with most amplifiers, driving larger capacitive loads in a unity gain configuration can cause excessive overshoot and ringing. A simple solution to this problem is to use a snubber network (see Figure 3). mv p-p +5V 3 U SNUBBER NETWORK V V+ ADA- V R S C L C S 5pF 5V Figure 3. Snubber Network Configuration R L kω The advantage of this compensation method is that the swing at the output is not reduced because RS is out of the feedback network, and the gain accuracy does not change. Depending on the capacitive loading of the circuit, the values of RS and CS change, and the optimum value can be determined empirically. In Figure 3, the oscilloscope image shows the output of the ADA-x family in response to a mv pulse. The circuit is configured in the unity gain configuration with 5 pf in parallel with kω of load capacitive. VOLTAGE (mv/div) INPUT SIGNAL OUTPUT SIGNAL TIME (µs/div) Figure 3. Capacitive Load Drive Without Snubber Network When the snubber circuit is used, the overshoot is reduced from 3% to 6% with the same load capacitance. Ringing is virtually eliminated, as shown in Figure 3. In this circuit, RS is Ω and CS is nf. VOLTAGE (mv/div) INPUT SIGNAL OUTPUT SIGNAL TIME (µs/div) Figure 3. Capacitive Load with Snubber Network Rev. A Page of 6

11 ADA-/ADA-/ADA- SETTLING TIME Settling time is the amount of time it takes the amplifier output to reach and remain within a percentage of its final value. This is an important parameter in data acquisition systems. Because most bipolar DAC converters have current output, an external op amp is required to convert the current to voltage. Therefore, the amplifier settling time plays a role in the total settling time of the output signal. A good approximation for the total settling time is ( t DAC) ( t AMP) t S Total = S + S The ADA-/ADA-/ADA- settle to within.% of their final value in less than. μs. The settling time has been tested by using the configuration circuit in Figure 3. The input signal is a V pulse and the output is the error signal for the settling time shown in Figure 33. 5V/DIV mv/div ns/div Figure 33. Settling Time Measurement Using the False Summing Node Method V V p-p V kω 3 V+ ADA- V 5V kω kω kω kω +5V 8 V+ AD88 V 5V kω V OUT Figure 3. Settling Time Test Circuit Rev. A Page of 6

12 ADA-/ADA-/ADA- OUTLINE DIMENSIONS 5. (.968).8 (.89). (.57) 3.8 (.97) (.) 5.8 (.8).5 (.98). (.) COPLANARITY. SEATING PLANE.7 (.5) BSC.75 (.688).35 (.53).5 (.).3 (.) 8.5 (.98).7 (.67).5 (.96).5 (.99).7 (.5). (.57) 5 COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 7-A.9 BSC 5.6 BSC.8 BSC 3 *.9 MAX.7 MIN.9 BSC.95 BSC. MAX.5.3 *. MAX SEATING PLANE..8 *COMPLIANT TO JEDEC STANDARDS MO-93-AB WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. Figure Lead Thin Small Outline Transistor Package [TSOT] (UJ-5) Dimensions shown in millimeters A Rev. A Page of 6

13 ADA-/ADA-/ADA PIN.65 BSC.38. COPLANARITY.. MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-87-AA Figure Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters BSC 7 PIN BSC COPLANARITY.9.. MAX SEATING PLANE..9 COMPLIANT TO JEDEC STANDARDS MO-53-AB- Figure 38. -Lead Standard Small Outline Package [TSSOP] (RU-) Dimensions shown in millimeters A Rev. A Page 3 of 6

14 ADA-/ADA-/ADA (.35) 8.55 (.3366). (.575) 3.8 (.96) (.) 5.8 (.83).5 (.98). (.39) COPLANARITY..7 (.5) BSC.5 (.).3 (.).75 (.689).35 (.53) SEATING PLANE 8.5 (.98).7 (.67).5 (.97).5 (.98).7 (.5). (.57) 5 COMPLIANT TO JEDEC STANDARDS MS--AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 39. -Lead Standard Small Outline Package [SOIC_N] (R-) Dimensions shown in millimeters 666-A ORDERING GUIDE Model Temperature Range Package Description Package Option Branding ADA-ARZ C to +5 C 8-Lead SOIC_N R-8 ADA-ARZ-R7 C to +5 C 8-Lead SOIC_N R-8 ADA-ARZ-RL C to +5 C 8-Lead SOIC_N R-8 ADA-AUJZ-R C to +5 C 5-Lead TSOT UJ-5 A ADA-AUJZ-R7 C to +5 C 5-Lead TSOT UJ-5 A ADA-AUJZ-RL C to +5 C 5-Lead TSOT UJ-5 A ADA-ARZ C to +5 C 8-Lead SOIC_N R-8 ADA-ARZ-R7 C to +5 C 8-Lead SOIC_N R-8 ADA-ARZ-RL C to +5 C 8-Lead SOIC_N R-8 ADA-ARMZ C to +5 C 8-Lead MSOP RM-8 AH ADA-ARMZ-RL C to +5 C 8-Lead MSOP RM-8 AH ADA-ARZ C to +5 C -Lead SOIC_N R- ADA-ARZ-R7 C to +5 C -Lead SOIC_N R- ADA-ARZ-RL C to +5 C -Lead SOIC_N R- ADA-ARUZ C to +5 C -Lead TSSOP RU- ADA-ARUZ-RL C to +5 C -Lead TSSOP RU- Z = RoHS Compliant Part. Rev. A Page of 6

15 ADA-/ADA-/ADA- NOTES Rev. A Page 5 of 6

16 ADA-/ADA-/ADA- NOTES 7 9 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D579--3/9(A) Rev. A Page 6 of 6