Low Power, High Precision Operational Amplifier OP97

Transcription

1 Low Power, High Precision Operational Amplifier FEATURES Low supply current: μa maximum OP7 type performance Offset voltage: μv maximum Offset voltage drift:. μv/ C maximum Very low bias current 5 C: pa maximum 55 C to +5 C: 5 pa maximum High common-mode rejection: 4 db minimum Extended industrial temperature range: 4 C to +85 C NULL PIN CONNECTIONS IN +IN V NULL V+ OUT OVER 5 COMP Figure. 8-Lead PDIP (P Suffix) 8-Lead SOIC (S Suffix) 99- GENERAL DESCRIPTION The is a low power alternative to the industry-standard OP7 precision amplifier. The maintains the standards of performance set by the OP7 while utilizing only μa supply current, less than / that of an OP7. Offset voltage is an ultralow 5 μv, and drift over temperature is below. μv/ C. External offset trimming is not required in the majority of circuits. Improvements have been made over OP7 specifications in several areas. Notable is bias current, which remains below 5 pa over the full military temperature range. The is ideal for use in precision long-term integrators or sample-andhold circuits that must operate at elevated temperatures. Common-mode rejection and power supply rejection are also improved with the, at 4 db minimum over wider ranges of common-mode or supply voltage. Outstanding PSR, a supply range specified from ±.5 V to ± V, and the minimal power requirements of the combine to make the a preferred device for portable and battery-powered instruments. The conforms to the OP7 pinout, with the null potentiometer connected between Pin and Pin 8 with the wiper to V+. The upgrades circuit designs using AD75, OP5, OP7, OP, and PM type amplifiers. It may replace 74- type amplifiers in circuits without nulling or where the nulling circuitry has been removed. Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 * PRODUCT PAGE QUICK LINKS Last Content Update: //7 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS EVAL-OPAMP- Evaluation Board DOCUMENTATION Application Notes AN-49: Using the Analog Devices Active Filter Design Tool Data Sheet : Military Data Sheet : Low Power, High Precision Operational Amplifier Data Sheet TOOLS AND SIMULATIONS Analog Filter Wizard Analog Photodiode Wizard DESIGN RESOURCES Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints DISCUSSIONS View all EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

3 TABLE OF CONTENTS Features... Pin Connections... General Description... Revision History... Specifications... Electrical Characteristics... Absolute Maximum Ratings... 5 Thermal Resistance... 5 ESD Caution...5 Typical Performance Characteristics... Application Information... AC Performance... Guarding and Shielding... Outline Dimensions... 5 Ordering Guide... REVISION HISTORY /9 Rev. F to Rev. G Changes to Figure and Figure... 9 Changes to Figure and Figure 7... Updated Outline Dimensions... 5 Changes to Ordering Guide... /7 Rev. E to Rev. F Updated Format... Universal Changes to Ordering Guide... / Rev. C to Rev. D Edits to Absolute Maximum Ratings... Edits to Ordering Guide... Deleted DICE Characteristics... Deleted Wafer Test Limits... Edits to Applications Information / Rev. D to Rev. E Deleted H-8A... Universal Deleted Q-8... Universal Deleted E-A... Universal Deleted Die Characteristics... 4 Deleted Wafer Test Limits... 4 Updated TPC Updated Outline Dimensions... Rev. G Page of

4 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VS = ±5 V, VCM = V, TA = 5 C, unless otherwise noted. Table. E F Parameter Symbol Conditions Min Typ Max Min Typ Max Unit INPUT CHARACTERISTICS Input Offset Voltage VOS 5 75 μv Long-Term Offset Voltage Stability ΔVOS/Time.. μv/month Input Offset Current IOS 5 pa Input Bias Current IB ± ± ± ±5 pa Input Noise Voltage en p-p. Hz to Hz.5.5 μv p-p Input Noise Voltage Density en fo = Hz 7 7 nv/ Hz fo = Hz 4 4 nv/ Hz Input Noise Current Density in fo = Hz fa/ Hz Large Signal Voltage Gain AVO VO = ± V; RL = kω V/mV Common-Mode Rejection CMR VCM = ±.5 V 4 db Input Voltage Range IVR ±.5 ±4. ±.5 ±4. V OUTPUT CHARACTERISTICS Output Voltage Swing VO RL = kω ± ±4 ± ±4 V Differential Input Resistance 4 RIN MΩ POWER SUPPLY Power Supply Rejection PSR VS = ± V to ± V 4 db Supply Current ISY 8 8 μa Supply Voltage VS Operating range ± ±5 ± ± ±5 ± V DYNAMIC PERFORMANCE Slew Rate SR.... V/μs Closed-Loop Bandwidth BW AVCL = MHz Hz noise voltage density is sample tested. Devices % tested for noise are available on request. Sample tested. Guaranteed by CMR test. 4 Guaranteed by design. Rev. G Page of

5 VS = ±5 V, VCM = V, 4 C TA +85 C for the E/F, unless otherwise noted. Table. E F Parameter Symbol Conditions Min Typ Max Min Typ Max Unit Input Offset Voltage VOS 5 μv Average Temperature TCVOS S suffix.... μv/ C Coefficient of VOS. Input Offset Current IOS pa Average Temperature TCIOS pa/ C Coefficient of IOS Input Bias Current IB ± ±5 ±8 ±75 pa Average Temperature Coefficient of IB TCIB pa/ C Large Signal Voltage Gain AVO VO = V; RL = kω 5 V/mV Common-Mode Rejection CMR VCM = ±.5 V db Power Supply Rejection PSR VS = ±.5 V to ± V db Input Voltage Range IVR ±.5 ±4. ±.5 ±4. V Output Voltage Swing VO RL = kω ± ±4 ± ±4 V Slew Rate SR V/μs Supply Current ISY μa Supply Voltage VS Operating range ±.5 ±5 ± ±.5 ±5 ± V Guaranteed by CMR test. Rev. G Page 4 of

6 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. Table. Parameter Rating Supply Voltage ± V Input Voltage ± V Differential Input Voltage ± V Differential Input Current ± ma Output Short-Circuit Duration Indefinite Operating Temperature Range 4 C to +85 C E, F (P, S) Storage Temperature Range 5 C to +5 C Junction Temperature Range 5 C to +5 C Lead Temperature (Soldering, sec) C For supply voltages less than ± V, the absolute maximum input voltage is equal to the supply voltage. The inputs of the are protected by back-to-back diodes. Currentlimiting resistors are not used in order to achieve low noise. Differential input voltages greater than V cause excessive current to flow through the input protection diodes unless limiting resistance is used. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Package Type θja θjc Unit 8-Lead PDIP (P Suffix) 4 C/W 8-Lead SOIC (S Suffix) 58 4 C/W θja is specified for worst-case mounting conditions, that is, θja is specified for device in socket for PDIP package; θja is specified for device soldered to printed circuit board for SOIC package. ESD CAUTION Rev. G Page 5 of

7 TYPICAL PERFORMANCE CHARACTERISTICS UNITS V CM = V 4 V CM = V I B NUMBER OF UNITS INPUT CURRENT (pa) I B + I OS INPUT OFFSET VOLTAGE (µv) Figure. Typical Distribution of Input Offset Voltage TEMPERATURE ( C) Figure 5. Input Bias, Offset Current vs. Temperature UNITS V CM = V 4 I B NUMBER OF UNITS INPUT CURRENT (pa) I B + I OS INPUT BIAS CURRENT (pa) Figure. Typical Distribution of Input Bias Current COMMON-MODE VOLTAGE (V) Figure. Input Bias, Offset Current vs. Common-Mode Voltage 99- NUMBER OF UNITS UNITS V CM = V DEVIATION FROM FINAL VALUE (µv) ±5 ±4 ± ± ± V CM =V J PACKAGES Z, P PACKAGES 4 4 INPUT OFFSET CURRENT (pa) Figure 4. Typical Distribution of Input Offset Current TIME AFTER POWER APPLIED (Minutes) Figure 7. Input Offset Voltage Warmup Drift 99-7 Rev. G Page of

8 EFFECTIVE OFFSET VOLTAGE (µv) BALANCED OR UNBALANCED V CM = V 55 C T A +5 C SUPPLY CURRENT (µa) NO LOAD T A = +5 C T A = +5 C k k k k k k M M M SOURCE RESISTANCE (Ω) Figure 8. Effective Offset Voltage vs. Source Resistance SUPPLY VOLTAGE (±V) Figure. Supply Current vs. Supply Voltage 99- EFFECTIVE OFFSET VOLTAGE DRIFT (µv/ C) BALANCED OR UNBALANCED V CM = V COMMON-MODE REJECTION (db) V S =±5V V CM = ±V. k k k M M M SOURCE RESISTANCE (Ω) Figure 9. Effective TCVOS vs. Source Resistance k k k M Figure. Common-Mode Rejection vs. Frequency 99- SHORT-CIRCUIT CURRENT (ma) OUTPUT SHORTED TO GROUND T A = +5 C T A = +5 C T A = +5 C T A = +5 C POWER SUPPLY REJECTION (db) PSR PSR V S =±5V ΔV S =V p-p TIME FROM OUTPUT SHORT (Minutes) Figure. Short-Circuit Current vs. Time, Temperature 99-. k k k M Figure. Power Supply Rejection vs. Frequency 99- Rev. G Page 7 of

9 OPEN-LOOP GAIN (V/mV) k k V O = ±V T A = +5 C T A = +5 C DIFFERENTIAL INPUT VOLTAGE (µv/div) T A = +5 C T A = +5 C R L = kω V CM = V 5 LOAD RESISTANCE (kω) Figure 4. Open-Loop Gain vs. Load Resistance OUTPUT VOLTAGE (V) Figure 7. Open-Loop Gain Linearity 99-7 VOLTAGE NOISE DENSITY (nv/ Hz) k V S = ±V TO ±V CURRENT NOISE / CORNER.5Hz VOLTAGE NOISE / CORNER Hz k Figure 5. Noise Density vs. Frequency k CURRENT NOISE DENSITY (fa/ Hz) OUTPUT SWING (V p-p) A VCL = + % THD f O = khz k k LOAD RESISTANCE (Ω) Figure 8. Maximum Output Swing vs. Load Resistance 99-8 TOTAL NOISE DENSITY (µv/ Hz). V S = ±V TO ±V khz Hz R R R S = R OUTPUT SWING (V p-p) A VCL = + % THD R L = kω RESISTOR NOISE. k k k M M M SOURCE RESISTANCE (Ω) Figure. Total Noise Density vs. Source Resistance 99- k k k Figure 9. Maximum Output Swing vs. Frequency 99-9 Rev. G Page 8 of

10 8 8 GAIN PHASE OPEN-LOOP GAIN (db) 4 4 PHASE C L = pf R L = MΩ T A = +5 C T A = +5 C PHASE SHIFT (Degrees) OPEN-LOOP GAIN (db) 4 4 GAIN C L = pf R L = MΩ T A = +5 C T A = +5 C PHASE SHIFT (Degrees) k k k M M Figure. Open-Loop Gain, Phase vs. Frequency (COC = pf) 9 9- k k k M M Figure. Open-Loop Gain, Phase vs. Frequency (COC = pf) 99- THD + N (%).. R L = kω % THD V OUT = V rms A VCL = A VCL = SLEW RATE (V/µs).. T A = +5 C R L = kω C L = pf. A VCL =. k k FREQUENCY (Ω) Figure. Total Harmonic Distortion Plus Noise vs. Frequency k k OVERCOMPENSATION CAPACITOR (pf) Figure 4. Slew Rate vs. Overcompensation 99-4 OVERSHOOT (%) A VCL = + V OUT = mv p-p C OC = pf +EDGE EDGE GAIN BANDWIDTH (khz) C L = pf R L = MΩ A = V T A = +5 C k k LOAD CAPACITANCE (pf) Figure. Small Signal Overshoot vs. Capacitive Load 99- k k OVERCOMPENSATION CAPACITOR (pf) Figure 5. Gain Bandwidth Product vs. Overcompensation 99-5 Rev. G Page 9 of

11 8 T A = +5 C k V S =±5V OPEN-LOOP GAIN (db) 4 4 C L = pf R L = MΩ GAIN PHASE T A = +5 C T A = +5 C k k k M 9 M Figure. Open-Loop Gain, Phase vs. Frequency (COC = pf) PHASE SHIFT (Degrees) 9 9- OUTPUT IMPEDANCE (Ω) A VCL =. A VCL =.. k k k Figure 8. Closed-Loop Output Resistance vs. Frequency ` OPEN-LOOP GAIN (db) 4 4 C L = pf R L = MΩ GAIN PHASE T A = +5 C T A = +5 C T A = +5 C k k k M 9 M Figure 7. Open-Loop Gain, Phase vs. Frequency (COC =, pf) PHASE SHIFT (Degrees) 99-7 Rev. G Page of

12 APPLICATION INFORMATION The is a low power alternative to the industry-standard precision op amp, the OP7. The can be substituted directly into OP7, OP77, AD75, and PM sockets with improved performance and/or less power dissipation and can be inserted into sockets conforming to the 74 pinout if nulling circuitry is not used. Generally, nulling circuitry used with earlier generation amplifiers is rendered superfluous by the extremely low offset voltage of the and can be removed without compromising circuit performance. Extremely low bias current over the full military temperature range makes the attractive for use in sample-and-hold amplifiers, peak detectors, and log amplifiers that must operate over a wide temperature range. Balancing input resistances is not necessary with the. Offset voltage and TCVOS are degraded only minimally by high source resistance, even when unbalanced. The input pins of the are protected against large differential voltage by back-to-back diodes. Current-limiting resistors are not used to maintain low noise performance. If differential voltages above ± V are expected at the inputs, series resistors must be used to limit the current flow to a maximum of ma. Common-mode voltages at the inputs are not restricted and may vary over the full range of the supply voltages used. The requires very little operating headroom about the supply rails and is specified for operation with supplies as low as ± V. Typically, the common-mode range extends to within V of either rail. The output typically swings to within V of the rails when using a kω load. Offset nulling is achieved utilizing the same circuitry as an OP7. A potentiometer between 5 kω and kω is connected between Pin and Pin 8 with the wiper connected to the positive supply. The trim range is between μv and 85 μv, depending upon the internal trimming of the device. +V 4 R POT = 5kΩ TO kω C OC V Figure 9. Optional Input Offset Voltage Nulling and Overcompensation Circuit 99-9 Rev. G Page of

13 AC PERFORMANCE The ac characteristics of the are highly stable over its full operating temperature range. Unity-gain small-signal response is shown in Figure. Extremely tolerant of capacitive loading on the output, the displays excellent response even with pf loads (see Figure ). In large signal applications, the input protection diodes effectively short the input to the output during the transients if the amplifier is connected in the usual unity-gain configuration. The output enters short-circuit current limit, with the flow going through the protection diodes. Improved large signal transient response is obtained by using a feedback resistor between the output and the inverting input. Figure shows the large-signal response of the in unitygain with a kω feedback resistor. The unity-gain follower circuit is shown in Figure. 9 % V µs Figure. Large Signal Transient Response (AVCL = ) 99- The overcompensation pin (Pin 5) can be used to increase the phase margin of the or to decrease gain bandwidth product at gains greater than. V IN kω V OUT 99- Figure. Unity-Gain Follower 9 9 % mv 5µs Figure. Small Signal Transient Response (CLOAD = pf, AVCL = ) 99- % mv 5µs Figure 4. Small Signal Transient Response with Overcompensation (CLOAD = pf, AVCL =, COC = pf) % mv 5µs Figure. Small-Signal Transient Response (CLOAD = pf, AVCL = ) 99- Rev. G Page of

14 GUARDING AND SHIELDING To maintain the extremely high input impedances of the, care must be taken in circuit board layout and manufacturing. Board surfaces must be kept scrupulously clean and free of moisture. Conformal coating is recommended to provide a humidity barrier. Even a clean PCB can have pa of leakage currents between adjacent traces; therefore, use guard rings around the inputs. Guard traces are operated at a voltage close to that on the inputs, so that leakage currents are minimal. In noninverting applications, connect the guard ring to the commonmode voltage at the inverting input (Pin ). In inverting applications, both inputs remain at ground, so that the guard trace should be grounded. Make guard traces on both sides of the circuit board. High impedance circuitry is extremely susceptible to RF pickup, line frequency hum, and radiated noise from switching power supplies. Enclosing sensitive analog sections within grounded shields is generally necessary to prevent excessive noise pickup. Twisted-pair cable aid in rejection of line frequency hum. R FB AD7548 pf I O V OUT The is an excellent choice as an output amplifier for higher resolution CMOS DACs. Its tightly trimmed offset voltage and minimal bias current result in virtually no degradation of linearity, even over wide temperature ranges. Figure shows a versatile monitor circuit that can typically sense current at any point between the ±5 V supplies. This makes it ideal for sensing current in applications such as full bridge drivers where bidirectional current is associated with large common-mode voltage changes. The 4 db CMRR of the makes the contribution of the amplifier to commonmode error negligible, leaving only the error due to the resistor ratio inequality. Ideally, R/R4 = R/R5. V R kω R kω R kω R4 kω R5 kω +5V 7 4 5V Figure. Current Monitor I L R L V OUT 99- I O DIGITAL INPUTS Figure 5. DAC Output Amplifier 99-5 UNITY-GAIN FOLLOWER NONINVERTING AMPLIFIER INVERTING AMPLIFIER PDIP BOTTOM VIEW 8 Figure 7. Guard Ring Layout and Connections 99-7 Rev. G Page of

15 The digitally programmable gain amplifier shown in Figure 8 has -bit gain resolution with -bit gain linearity over the range of to 4. The low bias current of the maintains this linearity, while C limits the noise voltage bandwidth, allowing accurate measurement down to microvolt levels. Table 5. DIGITAL IN GAIN (Av) Open Loop Many high speed amplifiers suffer from less-than-perfect low frequency performance. A combination amplifier consisting of a high precision, slow device like the and a faster device such as the AD8 results in uniformly accurate performance from dc to the high frequency limit of the AD8, which has a gainbandwidth product of 5 MHz. The circuit shown in Figure 9 accomplishes this, with the AD8 providing high frequency amplification and the operating on low frequency signals and providing offset correction. Offset voltage and drift of the circuit are controlled by the. R FB V IN ±.5mV TO ±V 8 RANGE DEPENDING ON GAIN SETTING I OUT V REF 7 V IN I OUT AD754A +5V 5V Figure 8. Precision Programmable Gain Amplifier R kω.µf kω µf R kω kω 5.µF +5V 5pF AD8 C pf.µf.µf A V = R R.µF Figure 9. Combination High Speed, Precision Amplifier 5V V OUT 99-8 V OUT % V µs Figure 4. Combination Amplifier Transient Response 99-4 Rev. G Page 4 of

16 OUTLINE DIMENSIONS.4 (.).5 (9.7).55 (9.). (5.) MAX.5 (.8). (.).5 (.9). (.5).8 (.4).4 (.) 8. (.54) BSC 5.8 (7.).5 (.5) 4.4 (.).5 (.8) MIN SEATING PLANE.5 (.) MIN. (.5) MAX.5 (.8) GAUGE PLANE.5 (8.). (7.87). (7.).4 (.9) MAX.95 (4.95). (.).5 (.9).4 (.). (.5).8 (.).7 (.78). (.5).45 (.4) COMPLIANT TO JEDEC STANDARDS MS- CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 4. 8-Lead Plastic Dual In-Line Package [PDIP] P-Suffix (N-8) Dimensions shown in inches and (millimeters) 7-A 5. (.98) 4.8 (.89) 4. (.574).8 (.497) (.44) 5.8 (.84).5 (.98). (.4) COPLANARITY. SEATING PLANE.7 (.5) BSC.75 (.88).5 (.5).5 (.). (.) 8.5 (.98).7 (.7).5 (.9).5 (.99).7 (.5).4 (.57) 45 COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 4. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body S-Suffix (R-8) Dimensions shown in millimeters and (inches) 47-A Rev. G Page 5 of

17 ORDERING GUIDE Model Temperature Range Package Description Package Option EP 4 C to +85 C 8-Lead PDIP N-8 EPZ 4 C to +85 C 8-Lead PDIP N-8 FP 4 C to +85 C 8-Lead PDIP N-8 FPZ 4 C to +85 C 8-Lead PDIP N-8 FS 4 C to +85 C 8-Lead SOIC_N R-8 FS-REEL 4 C to +85 C 8-Lead SOIC_N R-8 FS-REEL7 4 C to +85 C 8-Lead SOIC_N R-8 FSZ 4 C to +85 C 8-Lead SOIC_N R-8 FSZ-REEL 4 C to +85 C 8-Lead SOIC_N R-8 FSZ-REEL7 4 C to +85 C 8-Lead SOIC_N R-8 Z = RoHS Compliant Part Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D99--/9(G) Rev. G Page of