Ultralow Offset Voltage Dual Op Amp AD708

Transcription

1 Ultralow Offset Voltage Dual Op Amp AD7 FEATURES Very high dc precision 3 μv maximum offset voltage.3 μv/ C maximum offset voltage drift.35 μv p-p maximum voltage noise (.1 Hz to 1 Hz) 5 million V/V minimum open-loop gain 13 db minimum CMRR 1 db minimum PSRR Matching characteristics 3 μv maximum offset voltage match.3 μv/ C maximum offset voltage drift match 13 db minimum CMRR match Available in -lead narrow body, PDIP, and hermetic CERDIP and CERDIP/3B packages OUTPUT A PIN CONFIGURATION IN A +IN A V S 1 3 A + AD7 +V S 7 OUTPUT B 6 5 IN B +IN B TOP VIEW (Not to Scale) Figure 1. PDIP (N) and CERDIP (Q) Packages B GENERAL DESCRIPTION The AD7 is a high precision, dual monolithic operational amplifier. Each amplifier individually offers excellent dc precision with maximum offset voltage and offset voltage drift of any dual bipolar op amp. The matching specifications are among the best available in any dual op amp. In addition, the AD7 provides 5 V/μV minimum open-loop gain and guaranteed maximum input voltage noise of 35 nv p-p (.1 Hz to 1 Hz). All dc specifications show excellent stability over temperature, with offset voltage drift typically.1 μv/ C and input bias current drift of 5 pa/ C maximum. The AD7 is available in four performance grades. The AD7J is rated over the commercial temperature range of C to 7 C and is available in a narrow body, PDIP. The AD7A and AD7B are rated over the industrial temperature range of C to +5 C and are available in a CERDIP. The AD7S is rated over the military temperature range of 55 C to +15 C and is available in a CERDIP military version processed to MIL-STD-3B. PRODUCT HIGHLIGHTS 1. The combination of outstanding matching and individual specifications make the AD7 ideal for constructing high gain, precision instrumentation amplifiers.. The low offset voltage drift and low noise of the AD7 allow the designer to amplify very small signals without sacrificing overall system performance. 3. The AD7 1 V/μV typical open-loop gain and 1 db common-mode rejection make it ideal for precision applications. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 916, Norwood, MA 6-916, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 AD7* Product Page Quick Links Last Content Update: 11/1/16 Comparable Parts View a parametric search of comparable parts Documentation Data Sheet AD7: Ultralow Offset Voltage Dual Op Amp Data Sheet Design Resources AD7 Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints Discussions View all AD7 EngineerZone Discussions Sample and Buy Visit the product page to see pricing options Technical Support Submit a technical question or find your regional support number * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. This content may be frequently modified.

3 AD7 TABLE OF CONTENTS Features... 1 Pin Configuration... 1 General Description... 1 Product Highlights... 1 Revision History... Specifications... 3 Absolute Maximum Ratings... 5 ESD Caution... 5 Typical Performance Characteristics... 6 Theory of Operation... 1 Crosstalk Performance... 1 Operation with a Gain of High Precision Programmable Gain Amplifier Bridge Signal Conditioner... 1 Precision Absolute Value Circuit... 1 Selection of Passive Components... 1 Outline Dimensions Ordering Guide Matching Characteristics... 9 REVISION HISTORY 1/6 Rev. B to Rev. C Updated Format...Universal Removed TO-99 Package...Universal Deleted AD77 References...Universal Deleted LT1 Reference... 1 Deleted Figure Deleted Metalization Photograph... 5 Moved Figure 5, Figure 6, and Figure 7 to Theory of Operation section... 1 Updated Outline Dimensions Changes to Ordering Guide /91 Rev. A to Rev. B Rev. C Page of 16

4 5 C and ±15 V dc, unless otherwise noted. AD7 Table 1. AD7J/AD7A AD7B AD7S Parameter Conditions Min 1 Typ Max 1 Min 1 Typ Max 1 Min 1 Typ Max 1 Unit INPUT OFFSET VOLTAGE μv TMIN to TMAX μv Drift μv/ C Long Term Stability μv/month INPUT BIAS CURRENT na TMIN to TMAX na Average Drift pa/ C OFFSET CURRENT VCM = V na TMIN to TMAX na Average Drift pa/ C MATCHING CHARACTERISTICS 3 Offset Voltage 5 3 μv TMIN to TMAX μv Offset Voltage Drift μv/ C Input Bias Current na TMIN to TMAX 5... na Common-Mode Rejection db TMIN to TMAX db Power Supply Rejection db TMIN to TMAX db Channel Separation db INPUT VOLTAGE NOISE.1 Hz to 1 Hz μv p-p f = 1 Hz nv/ Hz f = 1 Hz nv/ Hz f = 1 khz nv/ Hz INPUT CURRENT NOISE.1 Hz to 1 Hz pa p-p f = 1 Hz pa/ Hz f = 1 Hz pa/ Hz f = 1 khz pa/ Hz COMMON-MODE REJECTION RATIO VCM = ±13 V db TMIN to TMAX db OPEN-LOOP GAIN VO = ±1 V RLOAD kω V/μV TMIN to TMAX V/μV POWER SUPPLY REJECTION RATIO VS = ±3 V to ±1 V db TMIN to TMAX db FREQUENCY RESPONSE Closed-Loop Bandwidth MHz Slew Rate V/μs INPUT RESISTANCE Differential 6 MΩ Common Mode GΩ Rev. C Page 3 of 16

5 AD7 AD7J/AD7A AD7B AD7S Parameter Conditions Min 1 Typ Max 1 Min 1 Typ Max 1 Min 1 Typ Max 1 Unit OUTPUT VOLTAGE RLOAD 1 kω ±V RLOAD kω ±V RLOAD 1 kω ±V TMIN to TMAX ±V OPEN-LOOP OUTPUT RESISTANCE Ω POWER SUPPLY Quiescent Current ma Power Consumption VS = ±15 V mw VS = ±3 V mw Operating Range ±3 ±1 ±3 ±1 ±3 ±1 V 1 All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. Input offset voltage specifications are guaranteed after five minutes of operation at TA = 5 C. 3 Matching is defined as the difference between parameters of the two amplifiers. Rev. C Page of 16

6 AD7 ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Supply Voltage ± V Internal Power Dissipation 1 Input Voltage ±VS Output Short-Circuit Duration Indefinite Differential Input Voltage +VS and VS Storage Temperature Range (Q) 65 C to +15 C Storage Temperature Range (N) 65 C to +15 C Lead Temperature (Soldering 6 sec) 3 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 Thermal Characteristics -lead PDIP: θjc = 33 C/W, θja = 1 C/W -lead CERDIP: θjc = 3 C/W, θja = 11 C/W For supply voltages less than ± V, the absolute maximum input voltage is equal to the supply voltage. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C Page 5 of 16

7 AD7 TYPICAL PERFORMANCE CHARACTERISTICS VS = ±15 V and TA = 5 C, unless otherwise noted. +V S COMMON-MODE VOLTAGE LIMIT (V) (REFERRED TO SUPPLY VOLTAGES) V V V S SUPPLY VOLTAGE (±V) Figure. Input Common-Mode Range vs. Supply Voltage 579- SUPPLY CURRENT (ma) SUPPLY VOLTAGE (±V) Figure 5. Supply Current vs. Supply Voltage OUTPUT VOLTAGE SWING (±V) (REFERRED TO SUPPLY VOLTAGES) +V S V OUT V OUT V S SUPPLY VOLTAGE (±V) R L = 1kΩ R L = kω Figure 3. Output Voltage Swing vs. Supply Voltage NUMBER OF UNITS UNITS TESTED 55 C TO +15 C OFFSET VOLTAGE DRIFT (µv/ C) Figure 6. Typical Distribution of Offset Voltage Drift I O = 1mA 3 1 OUTPUT VOLTAGE (V p-p) ±15V SUPPLIES OUTPUT IMPEDANCE (Ω) A V = +1 A V = k 1k LOAD RESISTANCE (Ω) Figure. Output Voltage Swing vs. Load Resistance k 1k 1k FREQUENCY (Hz) Figure 7. Output Impedance vs. Frequency Rev. C Page 6 of 16

8 AD7 16 INVERTING OR NONINVERTING INPUT BIAS CURRENT (ma) DIFFERENTIAL VOLTAGE (±V) 579- OPEN-LOOP GAIN (V/µV) V OUT = ±1V R L = 1kΩ R L = kω TEMPERATURE ( C) Figure. Input Bias Current vs. Differential Input Voltage Figure 11. Open-Loop Gain vs. Temperature INPUT VOLTAGE NOISE (nv/ Hz) /F CORNER.7Hz OPEN-LOOP GAIN (V/µV) R LOAD = kω FREQUENCY (Hz) SUPPLY VOLTAGE (V) Figure 9. Input Noise Spectral Density Figure 1. Open-Loop Gain vs. Supply Voltage 1s 1 1 R L = kω C L = 1pF 3 VOLTAGE NOISE (1nV/DIV) OPEN-LOOP GAIN (db) 1 6 PHASE MARGIN = 3 GAIN PHASE (Degrees) TIME (1s/DIV) Figure 1..1 Hz to 1 Hz Voltage Noise k 1k 1k 1M 1M FREQUENCY (Hz) Figure 13. Open-Loop Gain and Phase vs. Frequency Rev. C Page 7 of 16

9 AD mv/div COMMON-MODE REJECTION (db) k 1k 1k 1M FREQUENCY (Hz) TIME (µs/div) CH Figure 1. Common-Mode Rejection vs. Frequency Figure 17. Small Signal Transient Response; AV = +1, RL = kω, CL = 5 pf 35 3 F MAX =.khz R L = kω 5 C V S = ±15V mv/div OUTPUT VOLTAGE (V p-p) k 1k 1k FREQUENCY (Hz) 1M TIME (µs/div) CH Figure 15. Large Signal Frequency Response Figure 1. Small Signal Transient Response; AV = +1, RL = kω, CL = 1 pf 16 1 POWER SUPPLY REJECTION (db) k 1k 1k FREQUENCY (Hz) Figure 16. Power Supply Rejection vs. Frequency Rev. C Page of 16

10 AD7 MATCHING CHARACTERISTICS 3 5 C 16 1 PERCENTAGE OF UNITS (%) 16 1 PERCENTAGE OF UNITS (%) OFFSET VOLTAGE MATCH (µv) OFFSET CURRENT MATCH (na) 579- Figure 19. Typical Distribution of Offset Voltage Match Figure. Typical Distribution of Input Offset Current Match 3 55 C TO +15 C 16 1 PERCENTAGE OF UNITS (%) 16 1 PSRR MATCH (db) OFFSET DRIFT MATCH (µv/ C) TEMPERATURE ( C) Figure. Typical Distribution of Offset Voltage Drift Match Figure 3. PSRR Match vs. Temperature PERCENTAGE OF UNITS (%) CMRR MATCH (db) INPUT BIAS CURRENT MATCH (na) Figure 1. Typical Distribution of Input Bias Current Match TEMPERATURE ( C) Figure. CMRR Match vs. Temperature 579- Rev. C Page 9 of 16

11 AD7 THEORY OF OPERATION CROSSTALK PERFORMANCE The AD7 exhibits very low crosstalk as shown in Figure 5, Figure 6, and Figure 7. Figure 5 shows the offset voltage induced on Side B of the AD7 when Side A output is moving slowly (. Hz) from 1 V to +1 V under no load. This is the least stressful situation to the part because the overall power in the chip does not change. Only the location of the power in the output device changes. Figure 6 shows the input offset voltage change to Side B when Side A is driving a kω load. Here the power changes in the chip with the maximum power change occurring at 7.5 V. Figure 7 shows crosstalk under the most severe conditions. Side A is connected as a follower with V input, and is forced to sink and source ±5 ma of output current. Power = (3 V)(5 ma) = 15 mw Even this large change in power causes only an μv (linear) change in the input offset voltage of Side B. ΔV OSB = 1µV/DIV V IN = ±1V 1Ω 1Ω A 1kΩ B V OUTA kω V OUTB V V IN = ±1V A V OUTA kΩ V OUTA = V/DIV Figure 6. Crosstalk with kω Load B V OUTB 1Ω 1Ω I IN = ±5mA A kω V IN = ±1V V 1kΩ B V OUTB ΔV OSB = 1µV/DIV 1Ω 1Ω V V OUTA = V/DIV Figure 5. Crosstalk with No Load ΔV OSB = µv/div IN A = 1mA/DIV Figure 7. Crosstalk Under Forced Source and Sink Conditions Rev. C Page 1 of 16

12 AD7 OPERATION WITH A GAIN OF 1 To show the outstanding dc precision of the AD7 in a real application, Table 3 shows an error budget calculation for a gain of 1. This configuration is shown in Figure. Table 3. Maximum Error Contribution AV = 1 (S Grade) Error Sources (Full Scale: VOUT = 1 V, VIN = 1 mv) VOS 3 μv/1 mv = 3 ppm IOS (1 kω)(1 na)/1 V = 1 ppm Gain ( kω Load) 1 V/(5 16)/1 mv = ppm Noise.35 mv/1 mv = ppm VOS Drift (.3 mv/ C)/1 mv = 3 ppm/ C Total Unadjusted 5 C = 33 ppm > 11 bits 55 C to +15 C = 63 ppm > 1 bits With Offset Calibrated 5 C = 3 ppm > 1 bits 55 C to +15 C = 33 ppm > 11 bits V IN 1kΩ 1kΩ 1kΩ 3 1/ AD7 + +V S.1µF 7 V S.1µF Figure. Gain of 1 Configuration 6 V OUT This error budget assumes no error in the resistor ratio and no error from power supply variation (the 1 db minimum PSRR of the AD7S makes this a good assumption). The external resistors can cause gain error from mismatch and drift over temperature. HIGH PRECISION PROGRAMMABLE GAIN AMPLIFIER The three op amp programmable gain amplifier shown in Figure 9 takes advantage of the outstanding matching characteristics of the AD7 to achieve high dc precision V INA A A1 V S +V S V INB OUT 1 S1 S S3 S AD75 OUT 5 1/ AD7 S S7 S6 S5 1/ AD7 1Ω 1kΩ 6.1Ω 1kΩ 1kΩ 1kΩ 6.1Ω 1kΩ 1kΩ 1kΩ 6.1Ω 1kΩ Figure 9. Precision PGA 1kΩ 1kΩ 9.9kΩ AD77 9.9kΩ The gains of the circuit are controlled by the select lines, A and A1, of the AD75 multiplexer, and are 1, 1, 1, and 1 in this design. The input stage attains very high dc precision due to the 3 μv maximum offset voltage match of the AD7S and the 1 na maximum input bias current match. The accuracy is maintained over temperature because of the ultralow drift performance of the AD7. To achieve.1% gain accuracy, along with high common-mode rejection, the circuit should be trimmed. To maximize common-mode rejection 1. Set the select lines for gain = 1 and ground VINB.. Apply a precision dc voltage to VINA and trim RA until VO = VINA to the required precision. 3. Connect VINB to VINA and apply an input voltage equal to the full-scale common mode expected.. Trim RB B until VO = V. To minimize gain errors 1. Select gain = 1 with the control lines and apply a differential input voltage.. Adjust the 1 Ω potentiometer to VO = 1 VIN (adjust VIN magnitude as necessary). R B R A Repeat Step 1 and Step for gain = 1 and gain = 1, adjusting the 1 kω and 1 kω potentiometers, respectively. The design shown in Figure 9 should allow for.1% gain accuracy and.1 μv/v common-mode rejection when ±1% resistors and ±5% potentiometers are used. Rev. C Page 11 of 16

13 AD7 BRIDGE SIGNAL CONDITIONER The AD7 can be used in the circuit shown in Figure 3 to produce an accurate and inexpensive dynamic bridge conditioner. The low offset voltage match and low offset voltage drift match of the AD7 combine to achieve circuit performance better than all but the best instrumentation amplifiers. The outstanding specifications of the AD7, such as open-loop gain, input offset currents, and low input bias currents, do not limit circuit accuracy. As configured, the circuit only requires a gain resistor, RG, of suitable accuracy and a stable, accurate voltage reference. The transfer function is VO = VREF [ΔR/(R + ΔR)][RG/R] The only significant errors due to the AD7S are VOS_OUT = (VOS_MATCH)(RG/R) = 3 mv VOS_OUT (T) = (VOS_DRIFT)(RG/R) =.3 mv/ C To achieve high accuracy, Resistor RG should be.1% or better with a low drift coefficient. +15V AD5.5V V REF R R R = 35Ω R + ΔR R G 175kΩ 1/ AD7 V O AD7 enables this circuit to accurately resolve the input signal. In addition, the tight offset voltage drift match maintains the resolution of the circuit over the full military temperature range. The high dc open-loop gain and exceptional gain linearity allows the circuit to perform well at both large and small signal levels. In this circuit, the only significant dc errors are due to the offset voltage of the two amplifiers, the input offset current match of the amplifiers, and the mismatch of the resistors. Errors associated with the AD7S contribute less than.1% error over 55 C to +15 C. Maximum error at 5 C 3 μv + ( 1 kω)( 1 na) 1 V Maximum error at +15 C or 55 C 5 μv + ( na)( 1 kω) 1 V = μv/1 μv = ppm = C Figure 3 shows VOUT vs. VIN for this circuit with a ±3 mv input signal at.5 Hz. Note that the circuit exhibits very low offset at the zero crossing. This circuit can also produce VOUT = VIN by reversing the polarity of the two diodes. 1mV 1mV 15V 7Ω 1/ AD7 Figure 3. Bridge Signal Conditioning Circuit V OUT = 1mV/DIV 1kΩ 1kΩ V IN 1kΩ 5kΩ 1kΩ IN59 1 IN59 1 1/ AD7 5kΩ 3.75kΩ NOTE 1 LOW LEAKAGE DIODES 1/ AD7 Figure 31. Precision Absolute Value Circuit PRECISION ABSOLUTE VALUE CIRCUIT V O = V IN The AD7 is ideally suited to the precision absolute value circuit shown in Figure 31. The low offset voltage match of the V IN = 1mV/DIV Figure 3. Absolute Value Circuit Performance (Input Signal =.5 Hz) SELECTION OF PASSIVE COMPONENTS Use high quality passive components to take full advantage of the high precision and low drift characteristics of the AD7. Discrete resistors and resistor networks with temperature coefficients of less than 1 ppm/ C are available from Vishay, Caddock, Precision Replacement Parts (PRP), and others Rev. C Page 1 of 16

14 AD7 OUTLINE DIMENSIONS PIN 1.1 (5.33) MAX.15 (3.1).13 (3.3).115 (.9). (.56).1 (.6).1 (.36). (1.16).365 (9.7).355 (9.) 1.1 (.5) BSC.7 (1.7).6 (1.5).5 (1.1) 5. (7.11).5 (6.35). (6.1).15 (.3) MIN SEATING PLANE.5 (.13) MIN.6 (1.5) MAX.15 (.3) GAUGE PLANE.35 (.6).31 (7.7).3 (7.6).3 (1.9) MAX COMPLIANT TO JEDEC STANDARDS MS-1-BA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 33. -Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-) Dimensions shown in inches and (millimeters).195 (.95).13 (3.3).115 (.9).1 (.36).1 (.5). (.). (5.) MAX.5 (.13) MIN.55 (1.) MAX.1 (.5) BSC.5 (1.9) MAX. (5.).15 (3.1).3 (.5).1 (.36).7 (1.7).3 (.76) (7.7). (5.59).6 (1.5).15 (.3).15 (3.1) MIN SEATING PLANE CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN (.13).9 (7.37) Figure 3. -Lead Ceramic Dual In-Line Package [CERDIP] (Q-) Dimensions shown in inches and (millimeters).15 (.3). (.) ORDERING GUIDE Model Temperature Range Package Description Package Option AD7JN C to +7 C -Lead Plastic Dual In-Line Package [PDIP] N- AD7JNZ 1 C to +7 C -Lead Plastic Dual In-Line Package [PDIP] N- AD7AQ C to +5 C -Lead Ceramic Dual In-Line Package [CERDIP] Q- AD7BQ C to +5 C -Lead Ceramic Dual In-Line Package [CERDIP] Q- AD7SQ/3B 55 C to +15 C -Lead Ceramic Dual In-Line Package [CERDIP] Q- 1 Z = Pb-free part. Rev. C Page 13 of 16

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17 AD7 NOTES 6 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C579--1/6(C) Rev. C Page 16 of 16