Intermediate Frequency Transmitter, 800 MHz to 4000 MHz HMC8200LP5ME

Transcription

1 TX_IFIN DGA_S1_OUT DGA_S_IN LOG_IF SLPD_OUT VCC_BG LOG_RF VCC_LOG SCLK SEN LO_P LO_N VCC_IRM VCC_ENV ENV_P FEATURES High linearity: supports modulations to 4 QAM Tx IF range: MHz to 7 MHz Tx RF range: 8 MHz to MHz Tx power control: db SPI controlled interface 3-lead, mm mm LFCSP package APPLICATIONS Point to point communications Satellite communications Wireless microwave backhaul systems Intermediate Frequency Transmitter, 8 MHz to MHz FUNCTIONAL BLOCK DIAGRAM SDO DVDD RST BB_IP BB_IN VCC_DGA BB_QN BB_QP SDI SPI HMC8 BAND GAP ENV_N DS_OUT VCC_DS VVA_IN VGA_VCTRL VCC_VGA TX_OUT VCC_AMP PACKAGE BASE GENERAL DESCRIPTION The is a highly integrated intermediate frequency (IF) transmitter chip that converts the industry standard MHz to MHz IF input signals to an 8 MHz to MHz single-ended radio frequency (RF) signal at its output. The IF transmitter chip is housed in a compact mm mm LFCSP package and supports complex modulations up to 4 QAM. The simultaneously reduces the design complexity of traditional microwave radios while realizing significant size and cost improvements. With IF input power ranges from 31 dbm to +4 dbm, the Figure 1. provides 3 db of digital gain control in 1 db steps and an analog voltage gain amplifier (VGA) continuously controls the transmitter output power from dbm to + dbm. The device also features three integrated power detectors. The first detector (LOG_IF) can be utilized to monitor the IF input power. The second detector (SLPD_OUT) is a square law power detector that monitors the power entering the mixer. The third power detector (LOG_RF) is used to monitor the output power, which can be used for fine output power adjustment Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 TABLE OF CONTENTS Features... 1 Applications... 1 Functional Block Diagram... 1 General Description... 1 Revision History... Specifications... 3 Electrical Characteristics: 8 MHz to 18 MHz RF Frequency Range... 3 Electrical Characteristics: 18 MHz to 8 MHz RF Frequency Range... 4 Electrical Characteristics: 8 MHz to MHz RF Frequency Range... Absolute Maximum Ratings... 6 ESD Caution...6 Pin Configuration and Function Descriptions...7 Typical Performance Characteristics...8 Theory of Operation Register Array Assignments and Serial Interface Register Descriptions... Register Array Assignments... Evaluation Printed Circuit Board (PCB)... 3 Evaluation PCB Schematic... 4 Outline Dimensions... Ordering Guide... REVISION HISTORY /17 Rev. B to Rev. C Changes to Figure Updated Outline Dimensions... This Hittite Microwave Products data sheet has been reformatted to meet the styles and standards of Analog Devices, Inc. 6/16 v1.16 to Rev. B Updated Format... Universal Added Pin Configuration Diagram; Renumbered Sequentially... 7 Added Ordering Guide... Rev. C Page of

3 SPECIFICATIONS TA = C, IF frequency = 3 MHz, local oscillator (LO) input signal level = dbm, RF input signal level = 31 dbm per tone, DGA setting (dec) = 3 (maximum gain), VGA setting = 3.3 V (maximum gain), sideband select = lower sideband, unless otherwise noted. ELECTRICAL CHARACTERISTICS: 8 MHz TO 18 MHz RF FREQUENCY RANGE Table 1. Parameter Min Typ Max Unit OPERATING CONDITIONS LO Frequency Range MHz IF Frequency Range 7 MHz IF INPUT INTERFACE Input Impedance Ω Return Loss db LOG IF Power Detector1 db Dynamic Range db LOG IF Power Detector Range + dbm LOG IF Power Detector Slope 37 mv/db Square Log Power Detector Range 17 db RF OUTPUT INTERFACE Input Impedance Ω Return Loss 7 13 db LOG Power Detector1 db Dynamic Range db LOG Power Detector Range + dbm LOG Power Detector Slope 37 mv/db LO INPUT INTERFACE Input Impedance Ω Return Loss 7 1 db DYNAMIC PERFORMANCE Conversion Gain 34 db Digital VGA Dynamic Range 3 db Analog VGA Dynamic Range 3 7 db Sideband Rejection dbc Noise Figure 6 db Output Third-Order Intercept (OIP3) 8 31 dbm Output 1 db Compression Point (OP1dB) 11 dbm LO to RF Rejection 1 dbc IF to RF Rejection 6 63 dbc POWER SUPPLY Supply Voltage VCCx 3.3 V VCC_VGA 3.3 V Supply Current VCCx ma VCC_VGA 11 μa 1 Measurement was taken uncalibrated. VCC_VGA can be adjusted from 3.3 V (maximum gain) to V (minimum gain) to control the RF VGA. Rev. C Page 3 of

4 ELECTRICAL CHARACTERISTICS: 18 MHz TO 8 MHz RF FREQUENCY RANGE Table. Parameter Min Typ Max Unit OPERATING CONDITIONS LO Frequency Range 1 3 MHz IF Frequency Range 7 MHz IF INPUT INTERFACE Input Impedance Ω Return Loss db LOG IF Power Detector1 db Dynamic Range db LOG IF Power Detector Range + dbm LOG IF Power Detector Slope 37 mv/db Square Log Power Detector Range 17 db RF OUTPUT INTERFACE Input Impedance Ω Return Loss 1 db LOG Power Detector1 db Dynamic Range db LOG Power Detector Range + dbm LOG Power Detector Slope 37 mv/db LO INPUT INTERFACE Input Impedance Ω Return Loss 8 db DYNAMIC PERFORMANCE Conversion Gain 8 3 db Digital VGA Dynamic Range 3 db Analog VGA Dynamic Range 6 db Sideband Rejection dbc Noise Figure. db Output Third-Order Intercept (OIP3) 8 dbm Output 1 db Compression Point (OP1dB) dbm LO to RF Rejection 1 34 dbc IF to RF Rejection 8 dbc POWER SUPPLY Supply Voltage VCCx 3.3 V VCC_VGA 3.3 V Supply Current VCCx ma VCC_VGA 11 μa 1 Measurement was taken uncalibrated. VCC_VGA can be adjusted from 3.3 V (maximum gain) to V (minimum gain) to control the RF VGA. Rev. C Page 4 of

5 ELECTRICAL CHARACTERISTICS: 8 MHz TO MHz RF FREQUENCY RANGE Table 3. Parameter Min Typ Max Unit OPERATING CONDITIONS LO Frequency Range MHz IF Frequency Range 7 MHz IF INPUT INTERFACE Input Impedance Ω Return Loss db LOG IF Power Detector1 db Dynamic Range db LOG IF Power Detector Range + dbm LOG IF Power Detector Slope 37 mv/db Square Log Power Detector Range 17 db RF OUTPUT INTERFACE Input Impedance Ω Return Loss 3 db LOG Power Detector1 db Dynamic Range db LOG Power Detector Range + dbm LOG Power Detector Slope 37 mv/db LO INPUT INTERFACE Input Impedance Ω Return Loss 1 17 db DYNAMIC PERFORMANCE Conversion Gain db Digital VGA Dynamic Range 3 db Analog VGA Dynamic Range db Sideband Rejection 1 dbc Noise Figure. db Output Third-Order Intercept (OIP3) 6 dbm Output 1 db Compression Point (OP1dB) 7 14 dbm LO to RF Rejection 1 3 dbc IF to RF Rejection dbc POWER SUPPLY Supply Voltage VCCx 3.3 V VCC_VGA 3.3 V Supply Current VCCx ma VCC_VGA 11 μa 1 Measurement was taken uncalibrated. VCC_VGA can be adjusted from 3.3 V (maximum gain) to V (minimum gain) to control the RF VGA. Rev. C Page of

6 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating IF Input dbm LO Input dbm VCCx. V to +. V Digital Input/Output.3 V to +3.6 V Maximum Junction Temperature to C Maintain 1 Million Hour MTTF Thermal Resistance (RTH), Junction to 11 C/W Ground Paddle Temperature Operating C to +8 C Storage 6 C to + C Maximum Peak Reflow Temperature 6 C (MSL3) ESD Sensitivity (Human Body Model) V (Class ) Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. C Page 6 of

7 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SDO DVDD RST BB_IP BB_IN VCC_DGA BB_QN BB_QP ENV_N 3 DS_OUT VCC_DS 1 VVA_IN VGA_VCTRL 19 VCC_VGA 18 TX_OUT 17 VCC_AMP TX_IFIN DGA_S1_OUT DGA_S_IN LOG_IF SLPD_OUT VCC_BG LOG_RF VCC_LOG SDI SCLK SEN LO_P LO_N VCC_IRM VCC_ENV ENV_P HMC8 TOP VIEW (Not to Scale) NOTES 1. CONNECT EXPOSED GROUND PADDLE TO RF/DC GROUND. Figure. Pin Configuration Table. Pin Function Descriptions Pin No. Mnemonic Description 1 SDO SPI Serial Data Output. DVDD SPI Digital Supply. Refer to Figure 64 for the required external components. 3 RST SPI Reset. Connect to logic high for normal operation. 4, BB_IP, BB_IN Positive and Negative Filter Baseband IF I Inputs. 6 VCC_DGA Power Supply for the Digital Variable Gain Amplifier. Refer to Figure 64 for the required external components. 7, 8 BB_QN, BB_QP Negative and Positive Filter Baseband IF Q Inputs. 9 TX_IFIN Transmit (Tx) IF Input, Intermediate Frequency Input Port. This pin is matched to Ω. DGA_S1_OUT Power Supply for the First Stage Digital Gain Amplifier. This pin is matched to Ω. Refer to Figure 64 for the required external components. 11 DGA_S_IN Second Stage Digital Gain Amplifier Input. 1 LOG_IF IF Log Detector Output. 13 SLPD_OUT Square Law Detector Output. 14 VCC_BG Band Gap Supply. Power Supply Voltage for the Bias Controller. Refer to Figure 64 for the required external components. LOG_RF RF Log Detector Output. 16 VCC_LOG RF Log Detector Supply. Refer to Figure 64 for the required external components. 17 VCC_AMP Power Supply for the RF Output Amplifier. Refer to Figure 64 for the required external components. 18 TX_OUT Tx Chip Output. 19 VCC_VGA Power Supply for the Variable Gain Amplifier. Refer to Figure 64 for the required external components. VGA_VCTRL VGA Control Voltage. Refer to Figure 64 for the required external components. 1 VVA_IN VVA Intermediate Frequency Input Port. This pin is matched to Ω. VCC_DS Differential to Single Amplifier Supply. Refer to Figure 64 for the required external components. 3 DS_OUT Differential to Single Amplifier Intermediate Frequency Output Port. This pin is matched to Ω. 4, ENV_N, ENV_P Envelope Detector Outputs. 6 VCC_ENV Envelope Detector Supply. Refer to Figure 64 for the required external components. 7 VCC_IRM Power Supply for the Mixer Output. Refer to Figure 64 for the required external components. 8, 9 LO_N, LO_P Local Oscillator Inputs. These pins are ac-coupled and matched to Ω. SEN SPI Serial Enable. 31 SCLK SPI Clock Digital Input. 3 SDI SPI Serial Data Input. EPAD Exposed Pad. Connect exposed ground paddle to RF/dc ground Rev. C Page 7 of

8 TYPICAL PERFORMANCE CHARACTERISTICS DGA MAX, T A = +8 C DGA MAX, T A = + C DGA MAX, T A = C DGA MIN, T A = +8 C DGA MIN, T A = + C DGA MIN, T A = C CONVERSION GAIN (db) CONVERSION GAIN (db) DGA MAX, T A = +8 C DGA MAX, T A = + C DGA MAX, T A = C DGA MIN, T A = +8 C DGA MIN, T A = + C DGA MIN, T A = C Figure 3. Conversion Gain vs. RF Frequency over Temperature, Lower Sideband Figure 6. Conversion Gain vs. RF Frequency over Temperature, Upper Sideband C + C C C + C C SIDEBAND REJECTION (dbc) 3 SIDEBAND REJECTION (dbc) Figure 4. Sideband Rejection vs. RF Frequency over Temperature, Lower Sideband Figure 7. Sideband Rejection vs. RF Frequency over Temperature, Upper Sideband C + C C 3 +8 C + C C IP3 (dbm) IP3 (dbm) Figure. Output IP3 vs. RF Frequency over Temperature, Lower Sideband Figure 8. Output IP3 vs. RF Frequency over Temperature, Upper Sideband Rev. C Page 8 of

9 IM3 (dbc) C + C C Figure 9. IM3 vs. RF Frequency over Temperature, Lower Sideband IM3 (dbc) C + C C Figure 1. IM3 vs. RF Frequency over Temperature, Upper Sideband C + C C C + C C P1dB (dbm) 1 8 P1dB (dbm) Figure. Output P1dB vs. RF Frequency over Temperature, Lower Sideband Figure 13. Output P1dB vs. RF Frequency over Temperature, Upper Sideband C + C C C + C C 1 1 NOISE FIGURE (db) 8 6 NOISE FIGURE (db) Figure 11. Noise Figure vs. RF Frequency over Temperature, Lower Sideband Figure 14. Noise Figure vs. RF Frequency over Temperature, Upper Sideband Rev. C Page 9 of

10 CONVERSION GAIN (db) 4 3 4dBm dbm dbm +dbm +4dBm Figure. Conversion Gain vs. RF Frequency at Various LO Powers SIDEBAND REJECTION (dbc) 4 3 4dBm dbm dbm +dbm +4dBm Figure 18. Sideband Rejection vs. RF Frequency at Various LO Powers IP3 (dbm) 3 4dBm dbm dbm +dbm +4dBm IM3 (dbc) dBm dbm dbm +dbm +4dBm Figure 16. Output IP3 vs. RF Frequency at Various LO Powers Figure 19. IM3 vs. RF Frequency at Various LO Powers NOISE FIGURE (db) dBm dbm dbm +dbm +4dBm CONVERSION GAIN (db) 4 3.9V 3.13V 3.V 3.46V 3.63V Figure 17. Noise Figure vs. RF Frequency at Various LO Powers Figure. Conversion Gain vs. RF Frequency at Various VCCx Rev. C Page of

11 3 +8 C + C C IP3 (dbm).9v 3.13V 3.V 3.46V 3.63V RETURN LOSS (db) Figure 1. Output IP3 vs. RF Frequency at Various VCCx Figure 4. RF Return Loss vs. RF Frequency over Temperature SIDEBAND REJECTION (dbc) 4 3.9V 3.13V 3.V 3.46V 3.63V RETURN LOSS (db) +8 C + C C IF FREQUENCY (GHz) Figure. Sideband Rejection vs. RF Frequency at Various VCCx Figure. IF Return Loss vs. RF Frequency over Temperature IM3 (dbc) 3 4.9V 3.13V 3.V 3.46V 3.63V REJECTION (dbc) Figure 3. IM3 vs. RF Frequency at Various VCCx Figure 6. IF to RF Rejection vs. RF Frequency at C Rev. C Page 11 of

12 RETURN LOSS (db) +8 C + C C LO FREQUENCY (GHz) Figure 7. LO Return Loss vs. RF Frequency over Temperature CONVERSION GAIN (db) 3 DGA = DGA = DGA = DGA = DGA = DGA = DGA = DGA = Figure. Conversion Gain vs. RF Frequency over DGA Word, Measurement Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA C + C C 3 REJECTION (dbc) CONVERSION GAIN (db) LO FREQUENCY (GHz) Figure 8. LO to RF Rejection vs. LO Frequency over Temperature, Measurement Uncalibrated for LO Leakage C + C C 3 Figure 31. Conversion Gain vs. DGA Word over Temperature, Measurement Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA, RF = GHz REJECTION (dbc) C + C C DGA CONVERSION GAIN STEP (db) GHz 1.GHz.GHz 3.GHz 4.GHz Figure 9. IF to RF Rejection vs. RF Frequency over Temperature, Measured at the Input of the External Low-Pass Filter After C, see Figure Figure 3. Conversion Gain Step vs. DGA Word over RF Frequency Rev. C Page 1 of

13 CONVERSION GAIN (db) 3 +8 C + C C 3 Figure 33. Conversion Gain vs. DGA Word over Temperature, RF = 1 GHz, Measurement Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA DGA CONVERSION GAIN STEP (db) C + C C Figure 36. Conversion Gain Step vs. DGA Word over Temperature, RF = GHz CONVERSION GAIN (db) 3 +8 C + C C 3 Figure 34. Conversion Gain vs. DGA Word over Temperature, RF = 4 GHz, Measurement Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA IP3 (dbm) DGA = 3 DGA = DGA = DGA = DGA = DGA = DGA = DGA = Figure 37. Output IP3 vs. RF Frequency over DGA Word, Measurement Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA DGA CONVERSION GAIN STEP (db) C + C C Figure 3. Conversion Gain Step vs. DGA Word over Temperature, RF = 1 GHz, Measurement Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA IP3 (dbm) 3 +8 C + C C 3 Figure 38. Output IP3 vs. DGA Word over Temperature, RF = GHz, Measurement Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA Rev. C Page 13 of

14 DGA CONVERSION GAIN STEP (db) C + C C Figure 39. Conversion Gain Step vs. DGA Word over Temperature, RF = 4 GHz IM3 (dbm) DGA = DGA = DGA = DGA = DGA = DGA = DGA = DGA = Figure 4. IM3 vs. RF Frequency over DGA Word, Measurement Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA IP3 (dbm) 3 +8 C + C C 3 Figure. Output IP3 vs. DGA Word over Temperature, RF = 1 GHz, Measurement Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA IP3 (dbm) 3 +8 C + C C 3 3 Figure 41. Output IP3 vs. DGA Word over Temperature, RF = 4 GHz, Measurement Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA IM3 (dbc) C + C C Figure 43. IM3 vs. DGA Word over Temperature, RF = GHz, Measurement Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA NOISE FIGURE (db) DGA = DGA = 9 DGA = 18 DGA = 7 DGA = 3 Figure 44. Noise Figure vs. RF Frequency over DGA Word at VCC_VGA = 3.3 V Rev. C Page 14 of

15 IM3 (dbc) C + C C 3 Figure 4. IM3 vs. DGA Word over Temperature, RF = 1 GHz, Measurement Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA IM3 (dbc) C + C C 3 Figure 46. IM3 vs. DGA Word over Temperature, RF = 4 GHz, Measurement Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA DGA = DGA = 7 DGA = 9 DGA = 3 DGA = Figure 48. Noise Figure vs. RF Frequency over DGA Word at VCC_VGA = V NOISE FIGURE (db) IF LOG OUT SENSITIVITY (V/dB) INPUT POWER (dbm) RF = 1GHz AT +8 C RF = 1GHz AT + C RF = 1GHz AT C RF = 1GHz AT +8 C RF = 1GHz AT + C RF = 1GHz AT C RF = 1GHz AT +8 C RF = 1GHz AT + C RF = 1GHz AT C Figure 49. Log IF Detector Sensitivity vs. Input Power over Temperature and RF Frequency NOISE FIGURE (db) 4 3 DGA = DGA = 9 DGA = 18 DGA = 7 DGA = 3 RF LOG OUT (V) GHz 1GHz GHz 3GHz 4GHz Figure 47. Noise Figure vs. RF Frequency over DGA Word at VCC_VGA = 1. V OUTPUT POWER (dbm) Figure. Log RF Detector vs. Output Power over RF Frequency Rev. C Page of

16 ..8 IF LOG OUT (V) RF = 1GHz AT +8 C RF = 1GHz AT + C RF = 1GHz AT C RF = 1GHz AT +8 C RF = 1GHz AT + C RF = 1GHz AT C RF = 1GHz AT +8 C RF = 1GHz AT + C RF = 1GHz AT C RF LOG OUT (V) C + C C INPUT POWER (dbm) Figure 1. Log IF Detector Output vs. Input Power over Temperature and RF Frequency OUTPUT POWER (dbm) Figure 4. Log RF Detector vs. Output Power over Temperature, RF = GHz SLPD OUT (V) RF = 1GHz AT +8 C RF = 1GHz AT + C RF = 1GHz AT C RF = 1GHz AT +8 C RF = 1GHz AT + C RF = 1GHz AT C RF = 1GHz AT +8 C RF = 1GHz AT + C RF = 1GHz AT C CONVERSION GAIN (db) 3.8GHz 1.GHz.GHz 3.GHz 4.GHz INPUT POWER (dbm) Figure. Square Law Detector Output vs. Input Power over Temperature and RF Frequency CONTROL VOLTAGE (V) Figure. Conversion Gain vs. VGA Control Voltage over RF Frequency, Measurement Conducted with DGA = 3 (Maximum Gain) on IF DGA RF LOG OUT (V) C + C C CONVERSION GAIN (db) 3 +8 C + C C OUTPUT POWER (dbm) Figure 3. Log RF Detector vs. Output Power over Temperature, RF =.8 GHz CONTROL VOLTAGE (V) Figure 6. Conversion Gain vs. VGA Control Voltage over Temperature, RF = GHz, Measurement Conducted with DGA = 3 (Maximum Gain) on IF DGA Rev. C Page 16 of

17 .8 RF LOG OUT (V) C + C C CONVERSION GAIN (db) 3 +8 C + C C OUTPUT POWER (dbm) Figure 7. Log RF Detector vs. Output Power over Temperature, RF = 4 GHz CONTROL VOLTAGE (V) Figure 9. Conversion Gain vs. VGA Control Voltage over Temperature, RF = 4 GHz, Measurement Conducted with DGA = 3 (Maximum Gain) on IF DGA CONVERSION GAIN (db) 3 +8 C + C C CONTROL VOLTAGE (V) Figure 8. Conversion Gain vs. VGA Control Voltage over Temperature, RF = 1 GHz, Measurement Conducted with DGA = 3 (Maximum Gain) on IF DGA Rev. C Page 17 of

18 THEORY OF OPERATION The is a highly integrated intermediate frequency (IF) transceiver chip that converts intermediate frequency to a single-ended radio frequency (RF) signal at its output. The intermediate frequency (IF) can be supplied to the singled ended or through the baseband differential inputs. The single-ended input of the utilizes an input digital gain amplifier (DGA) that is controlled via SPI, which feeds the IF signals to an image reject mixer. At the input of the device before the DGA, an intermediate log power detector can be used to monitor input power levels into the device. A square law detector follows the DGA to monitor the power entering the mixer. See the Register Array Assignments and Serial Interface section for more information regarding the DGA. The baseband differential inputs of the feed the intermediate frequency directly into the image reject mixer. It is recommended that when using the single-ended input, do not leave the baseband differential inputs connected. The local oscillator port can either be driven single ended through LO_N or differentially through the combination of LO_N and LO_P. If Driving the local oscillator port differentially improves the LO to RF rejection. The IF is then converted to RF, which is followed by an amplifier. Next, the amplified RF signal is fed off chip to a lowpass filter. The external filter path feeds back into a variable gain amplifier (VGA) that is voltage controlled. The output of the VGA drives a final amplifier that is the output of the device. An RF log detector is connected to the output of the final amplifier to monitor the output power of the. The utilizes an input low noise amplifier (LNA) cascaded with a VGA, which can either be controlled by the internal AGC or external voltages, that feeds the RF signals to an image reject mixer. The local oscillator port can either be driven single ended through LO_N or differentially through the combination of LO_N and LO_P. The radio frequency is then converted to intermediate frequencies, which can either feed off chip via baseband differential outputs or feed on chip into a programmable bandpass filter. It is recommended during IF mode operation that the baseband outputs be unconnected. The programmable band-pass filter on chip has four programmable bandwidths (14 MHz, 8 MHz, 6 MHz, and 11 MHz). The programmable band-pass filter has the capability to adjust the center frequency. From the factory, a filter calibration is conducted and the center frequency of the filter is set to 1 MHz. This calibration can be recalled via SPI control or the customer can adjust the center frequency, but the calibration value must be stored off chip (see the Register Array Assignments section). An external filter option can be utilized to allow the customer to select other filter bandwidths/responses that are not available on chip. The external filter path coming from the image reject mixer feeds into an amplifier that has differential outputs. The output of the external filter can be fed back into the chip, which is then connected to another amplifier. A VGA follows immediately after the band-pass filter. Control the IF VGA either by the AGC or external voltages. The output of the variable gain amplifier is the output of the device. REGISTER ARRAY ASSIGNMENTS AND SERIAL INTERFACE The register arrays for the are organized into seven registers of 16 bits. Using the serial interface, the arrays are written or read one row at a time, as shown in Figure 61 and Figure 6. Figure 61 shows the sequence of signals on the enable (SEN), CLK, and data (SDI) lines to write one 16-bit array of data to a single register. The enable line goes low, the first of 4 data bits is placed on the data line, and the data is sampled on the rising edge of the clock. The data line should remain stable for at least ns after the rising edge of CLK. The device supports a serial interface running up to MHz, the interface is 3.3 V CMOS logic. A write operation requires 4 data bits and 4 clock pulses, as shown in Figure 61. The 4 data bits contain the 3-bit chip address, followed by the -bit register array number, and finally the 16-bit register data. After the 4th clock pulses of the write operation, the enable line returns high to load the register array on the IC. A read operation requires 4 data bits and 48 clock pulses, as shown in Figure 6. For every register read operation, a write to Register 7 is required first. The data written should contain the 3-bit chip address, followed by the -bit register number for Register 7, and finally the -bit number of the register to be read. The remaining 11 bits should be logic zeroes. When the read operation is initiated, the data is available on the data output (SDO) pin. Read Example If reading Register, write the following 4 bits to initiate the read operation ZERO BITS (11 BITS) REGISTER 7 ADDRESS ( BITS) REGISTER TO BE READ ( BITS) CHIP ADDRESS (3 BITS) Figure 6. Sample Bits to Initiate Read Rev. C Page 18 of

19 SEN 4 CLOCK CYCLES 1 4 CLK SDI MSB WRITE DATA LSB MSB REGISTER ADDRESS LSB CHIP ADDRESS MSB LSB Figure 61. Timing Diagram, SPI Register Write SEN 4 CLOCK CYCLES 4 CLOCK CYCLES CLK SDI SDO MSB ALL ZEROS LSB MSB READ REGISTER ADDRESS LSB MSB CHIP REG 7 ADDRESS ADDRESS MSB LSB MSB READ DATA LSB Figure 6. Timing Diagram, SPI Register Read Rev. C Page 19 of

20 REGISTER DESCRIPTIONS REGISTER ARRAY ASSIGNMENTS In the Access columns (Table 6 through Table 1), R means read, W means write, and R/W means read/write. Enable Bits Table 6. Enable Register, (Address x1) Bit No. Bit Name Description Reset Access [:13] Reserved Not used x6 R/W 1 LOG_IF_EN Log intermediate frequency (IF) detector enable x1 R/W = disable 1 = enable 11 DSE_EN Differential to single (after mixer) enable x1 R/W = disable 1 = enable Factory diagnostics = Logic for normal operation x R/W 9 CM_BUFFER_EN Common-mode buffer enable x R/W = disable 1 = enable 8 Factory Diagnostics 1 = Logic 1 for normal operation x1 R/W 7 LOG_DET_EN Log detector enable x1 R/W = disable 1 = enable 6 MS_EN Square detector enable x1 R/W = disable 1 = enable ENVELOPE_EN Envelope detector enable x1 R/W = enable 1 = disable 4 VGA_EN Variable gain amplifier (VGA) enable x1 R/W = disable 1 = enable 3 IRM_EN Image reject mixer enable x1 R/W = disable 1 = enable IRM_IQ_EN IQ line enable x R/W = disable 1 = enable 1 DGA_EN Digital gain amplifier (DGA) enable x1 R/W = disable 1 = enable LPF_EN Low-pass filter enable x R/W = disable 1 = enable Rev. C Page of

21 Digital Gain Amplifier: DGA Control Table 7. Digital Gain Amplifier (Address x3) Bit No. Bit Name Description Reset Access Reserved Not used x R/W [14:9] DGA_CTRL Override SPI FIL_FRQ_SET and use 8-bit word from OTP x R/W = minimum gain 1 = 11 = maximum gain [8:] Reserved Not used x R/W Digital Gain Amplifier: Amplifier Current, Envelope Level, and VGA Attenuation Bias Table 8. Digital Gain Amplifier, (Address x4) Bit No. Bit Name Description Reset Access [:9] Reserved Not used 111 R/W [8:7] AMP_CUR Amplifier current 11 R/W [6:] ENV_LVL Envelope level 11 R/W [1:] VGA_ATT_BIAS VGA attenuation bias R/W Image Reject Mixer: Sideband, and Polarity and Offset for I Table 9. Image Reject Mixer Register, (Address x) Bit No. Bit Name Description Reset Access [:1] Reserved Reserved Logic for normal operation 11 IRM_IS Image sideband 1 R/W = upper sideband 1 = lower sideband [:9] Reserved Reserved 1 R/W Logic 1 for normal operation 8 OFFSET_POLARITY_I Offset Polarity I R/W [7:] IRM_OFFSET_I Image reject mixer offset for I x R/W Image Reject Mixer: Polarity and Offset for Q Table. Image Reject Mixer Register, (Address x6) Bit No. Bit Name Description Reset Access [:9] Reserved Not used 111 R/W 8 OFFSET_POLARITY_Q Offset Polarity Q R/W [7:] IRM_OFFSET_Q Image reject mixer offset for Q x R/W Rev. C Page 1 of

22 Phase I: Adjust Table 11. Phase I Register, (Address x8) Bit No. Bit Name Description Reset Access [:9] Reserved Not used 111 R/W [8:] I_PHASE_ADJ I phase adjust x R/W Phase Q: Adjust Table 1. Phase Q Register, (Address x9) Bit No. Bit Name Description Reset Access [:9] Reserved Not used 111 R/W [8:] Q_PHASE_ADJ Q phase adjust x R/W Rev. C Page of

23 EVALUATION PRINTED CIRCUIT BOARD (PCB) LON ENV P ENV N LOP BB IP GND C6 LOG RF VGA CTRL LOG IF GND SLPD OUT J C31 R C36 C34 C1 C3 U C C R4 R6 C4 C R7 C3 C33 C49 C7 C61 C8 C C R R17 C11 C C C3 C4 C6 L C63 C64 C6 C7 F1 C4 R13 JP1 J3 BB IN C14 C6 C6 C9 R14 R16 C17 C C C3 C R3 L1 C18 C19 C8 C1 C9 C C6 C4 C43 C44 C4 C47 C37 C38 C46 C48 TX_OUT BB QN GND BB QP C16 J1 GND TX IF IN VCC_3P3V Figure 63. Evaluation PCB Rev. C Page 3 of

24 EVALUATION PCB SCHEMATIC SCLK LO_N LO_P SEN C pf C6 nf V CC 3 C pf V CTRL SDI V CC 9 V CC C µf C nf RST C14 nf SDO C11 pf C pf SPI L nh C pf C63 pf RF OUT C64 nf V CC 4 C6 pf C6 pf R13 1kΩ C4 pf C7 nf V CC JP1 V CC 1/DGA_S1 C43 µf C19 nf C18 pf L1 3nH IF IN R3 4.9Ω C17 pf DET1 C pf C4 pf C3 nf C8 pf C nf C4 µf C9 nf C46 µf V CC 7 DET3 C48 µf V CC 6 V CC 8 DET C pf V CC R7 kω C3 pf C33 nf C49 µf V CC _AGC R6 kω C34 pf C33 nf C µf DET3 R kω 3 4 V V 1 R kω C31 pf Figure 64. PCB Schematic/Typical Applications Circuit Rev. C Page 4 of

25 OUTLINE DIMENSIONS PIN 1 INDICATOR.. SQ DETAIL A (JEDEC 9) PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A). BSC 4 EXPOSED PAD SQ SEATING PLANE TOP VIEW MAX. NOM COPLANARITY.8. REF BOTTOM VIEW 3. REF 9. MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. ORDERING GUIDE PKG- COMPLIANT TO JEDEC STANDARDS MO--VHHD- Figure 6. 3-Lead Lead Frame Chip Scale Package [LFCSP] mm mm Body,.8 mm Package Height (CP-3-7) Dimensions shown in millimeters Model 1, Temperature Range MSL Rating 3 Package Description Option Branding 4 Quantity Package C to +8 C MSL3 3-Lead LFCSP, Tape and Reel CP-3-7 H8 XXXX TR C to +8 C MSL3 3-Lead LFCSP, Tape and Reel CP-3-7 H8 XXXX EK1HMC8LPM Evaluation Kit A 1 All products listed in the ordering guide are RoHS compliant. The lead finish is NiPdAu. 3 See the Absolute Maximum Ratings section. 4 XXXX is the 4-digit lot number Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D /17(C) Rev. C Page of