A 1.6-to-3.2/4.8 GHz Dual Modulus Injection-Locked Frequency Multiplier in

Transcription

1 RTU1D-2 LAICS A 1.6-to-3.2/4.8 GHz Dual Modulus Injection-Locked Frequency Multiplier in 0.18µm CMOS L. Zhang, D. Karasiewicz, B. Ciftcioglu and H. Wu Laboratory for Advanced Integrated Circuits and Systems Department of Electrical and Computer Engineering University of Rochester RFIC Atlanta June 15-17, 2008

2 Motivation Outline Injection-locked frequency multiplier (ILFM) Prototype design Measurement results Conclusion

3 Frequency Multiplier Applications LO Generation in TRx Local Clock Scaling in SoC PA N f 0 VCO IF f 0 N 1 N 1 f 0 f 0 LCD LCD N f 0 N2 N 2 f 0 LCD LO generation in RF and microwave transceivers Avoid VCO pulling Reach higher frequency than VCO Frequency scaling in local clock generation Multi-clock domain (MCD)

4 Effects of Undesired Harmonics for LO Signal Desired signal RF Interferer ω LNA Undesired harmonics LO IF Desired signal Interferer with undesired LO harmonics Interferer w/o undesired LO harmonics ω Exacerbate the nonlinear effects of mixer, increasing noise figure ω

5 Effects of Undesired Harmonics for Clock Generation Ideal clock waveform Clock waveform with second sub harmonics Time Periodic jitter that may causes logic error

6 Effects of Undesired Harmonics for Clock Generation Clock waveform with strong second harmonics Ideal clock waveform Time Periodic jitter that may causes logic error

7 Conventional Frequency Multipliers Band Pass Filter 3 f 0 f 0 Low Q Lossy Inductor in CMOS Harmonic generation followed by filtering Undesired harmonics suppressed Output power direct proportional to harmonic generator power

8 Harmonic Suppression vs. Q Harmonic suppressions of a parallel LC filter (db) Fundamental suppression 2 nd order suppression 2 f 0 f 0 3 f 0 4 f 0 5 f Q Suppression of undesired harmonics proportional to the quality factor of the filter network For CMOS implementations, low Q passive devices means poor undesired harmonics suppression

9 Injection-Locked Frequency Multiplier (ILFM) f 0 Band Pass Filter Low Q ILO 3 f 0 Harmonic Generator ILO act as a high-q, high-gain band pass amplifier after the harmonic generator Achieves good undesired harmonic suppression with low Q passive devices Decouples output power and harmonic generator power

10 Harmonic Suppression in ILFM Resonator spectrum res ω Line width compression Oscillator spectrum osc ω 0 res ~ ω Q 1 k T ω B 0 osc ~ 2 v0 C QL Harmonics suppression improves when replace the resonator with an ILO Donhee Ham, IEEE JSSC, March 2003.

11 Pros & Cons Better suppression of undesired harmonics Capable of multi-modulus operation Decouples output power with harmonic generator power Capable of implementation on lossy processes like CMOS without performance degradation

12 Dual-Modulus ILFM L 1 Buffer Modulus Control C s1 V out M M 2 3 V in R 1 Harmonic Generator M 1 C t1 C s2 T 1 ILO M tail V bias Multiply by 2/3 by modulus control

13 Chip Photo Ou utput Osc M 1 T 1 Input 100um Core circuitry occupies only 0.4 by 0.1 mm 2

14 Doubler Output Spectrum Spect trum (dbm) dB Frequency (GHz) Measured at 5% locking range.

15 Tripler Output Spectrum Spec ctrum (dbm) dB 32dB Frequency (GHz) Measured at 5% locking range.

16 Output Harmonics vs. Input Output Harmon nics Power (dbm) Doubler st (input) 2 nd (output) 3 rd th 5 th Input Amplitude (V) st (input) 2 nd 3 rd (output) 4 th 5 th Tripler Input Amplitude (V) Output harmonics strength increases as the input increases

17 Harmonic Suppression (db) Harmonic Suppression vs. Input Doubler 70 1 st 3 rd 4 th 60 5 th Tripler 1 st 2 nd 4 th 5 th Input Amplitude (V) Input Amplitude (V) Harmonic suppressions reduce as input increases

18 Locking Range Bounds of Loc cking Range (GHz) Upper Bound Lower Bound Locking Range Upper Bound Lower Bound Locking Range Tripler Doubler Locking Range (%) Input Amplitude (V) Locking ranges increase with input

19 Power & Locking Range Tradeoff Doubler Tripler Range (%) Locking Power Consumption (mw) Locking range and power consumption both proportional to injection level.

20 Phase Noise Measured input Doubler Tripler Doubler freerun Tripler freerun Phase Noi ise (dbc) dB Noise floor of spectrum analyzer Ideal phase noise of signal source from the manual Offset Frequency (Hz)

21 Performance Comparison Ref Process xn f out (GHz) BW Pdc (mw) V 1 /V 2,3 (db) V 2 /V 3 (db) Chip size * (mm 2 ) This work* 1 CMOS x NA This work* 2 CMOS x [7] CMOS x2 5 NA NA [8] SOI CMOS x NA [1] SiGe x3 60 NA NA NA [5] SiGe HBT x NA [5] SiGe HBT x NA [6] InGaAs PHEMT x3 36 NA [11] InGaP HBT x NA [12] SiGe HBT x NA [13] [14] GaAs PHEMT GaAs HEMT x NA x NA * without pads

22 Conclusion A dual modulus injection-locked frequency multiplier (ILFM) topology proposed; The new topology achieves good suppression on undesired harmonics on lossy CMOS process; A circuit prototype for 1.6-to-3.2/4.8 GHz operation fabricated and measured to demonstrate the new ILFM topology.

23 Acknowledgement National Semiconductor Bijoy Chatterjee, Peter Holloway, Babatunde Akinpelu, Peter Misich, Carlos Hinojosa, Jun Wan, Sonnet Software LAICS members Yunliang Zhu, Jianyun Hu, Shang Wang

24 RTU1D-2 LAICS Thank you!