A 484µm 2, 21GHz LC-VCO Beneath a Stacked-Spiral Inductor
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1 A 484µm, GHz LC-VCO Beneath a Stacked-Spiral Inductor Rui Murakami, Kenichi Okada, and Akira Tokyo Institute of Technology, Japan 00/09/8
2 Contents Background Downsizing of LC-VCO Circuit Stacking Beneath the Inductor Measurement Result Summary 00/09/8 R.Murakami, Tokyo Tech
3 Scaling of Supply Voltage Supply Voltage [V] ITRS000 ITRS Year As supply voltage is scaled down, low voltage circuits are needed. 00/09/8 R.Murakami, Tokyo Tech
4 Jitter (Phase noise) of Oscillators LC-VCO L LC = Ring-VCO L Ring [] 0 offset ω k T + γ ω V I Q [] DD bias n k:boltzmann s constant T: Absolute temperature 0:freq. offset: Offset freq. VTH:Threshold voltage M:Number of stages Q:Quality factor of LC-tank Ibias:Bias current n, p:noise factor ω 0 k T VDD = M (γ n + γp ) + ω VDDIbias VDD V offset TH 3 Ring oscillators are more susceptible to the effect of downscaling the supply voltage. []A. Mazzanti, et al., JSSC 008 []A. Abidi, JSSC /09/8 R.Murakami, Tokyo Tech
5 Problem of Clock Generator Clock [GHz]5 Clock Ring-VCO LC-VCO Year 3.6x V DD σ Jitter/Clock [%] [3] 4 Ring-VCOs must be replaced with LC-VCOs [3] K.Okada, et al., VLSIC /09/8 R.Murakami, Tokyo Tech
6 Comparison of Oscillators 5 Ring Bad Large Very small Noise Power freq. Area LC Good Small Large inductor core To replace Ring-VCO by LC-VCO Increasing chip area will become a problem. A very small LC-VCO is desired. The inductor occupies the dominant area in a LC-VCO. It is needed to miniaturize the Inductor 00/09/8 R.Murakami, Tokyo Tech
7 Oscillation Frequency frequency = π LC At a higher frequency, smaller inductance is needed. VCO can be designed using a small inductor. 6 Over 0GHz, quality factor degradation is caused by the skin effect. Poor phase noise and high power consumption. A 0GHz LC-VCO results in a good balance between area and phase noise 00/09/8 R.Murakami, Tokyo Tech
8 Stacked-spiral Inductor 7 Mono-layer inductor Single layer Wide line width Large diameter Low R, High Q Large area Stacked-spiral inductor 00/09/8 R.Murakami, Tokyo Tech Multi layer Narrow line width Small diameter High R, Low Q Ultra low space
9 Comparison the Inductors 8 Area /44 5µm 00µm Stacked-spiral Mono-layer R S C L L Stacked-spiral Mono-layer L S [nh] R S [Ohm] C L [ff] Q /09/8 R.Murakami, Tokyo Tech
10 Placement of Core-circuit 9 When the Inductor is miniaturized, the core-circuit size becomes close to the area of the inductor. Insert core-circuit under the inductor. Inductive coupling is a problem. 00/09/8 R.Murakami, Tokyo Tech
11 00/09/8 R.Murakami, Tokyo Tech 0 Inductive Coupling parallel line eddy current Inductance and quality factor will be degraded by inductive coupling = ln m d m d d m d m m M [4] H.M.Greenhouse, TOPHAP 974 m d + = + = Q Q k L L R L k L L ω ω [4]
12 Reducing coupling To reduce coupling, some layout techniques are applied. Slit shaping interconnections Placing inductor trace and interconnections orthogonally 00/09/8 R.Murakami, Tokyo Tech
13 Analysis of Interconnection Effects The model of the interconnections is created and simulated the influence on L S and Q by HFSS. Normal Normal Beneath L S [nh].6.4 Q.8.67 L S 3%, Q 5%down It corresponds 0.4dB in FoM. 00/09/8 R.Murakami, Tokyo Tech
14 Chip Micrograph() CMOS 65nm 3 Output Buffer µm VCO core µm 00/09/8 R.Murakami, Tokyo Tech
15 Chip Micrograph() 4 VCO core 00µm 00µm 00/09/8 R.Murakami, Tokyo Tech
16 Measurement Result 5 FoMA f o { f } 0log f 00/09/8 R.Murakami, Tokyo Tech P DC Area + 0log 0log mw mm = [5]Shih-An Yu, et al., IEEE TCAS-II 009 [5]
17 Performance Summary 6 µ FoM [6]A.Tanabe, et al., RFIC 009 [7]I.Hwang, et al., JSSC 004 [3]K.Okada, et al., VLSIC /09/8 R.Murakami, Tokyo Tech
18 Summary 7 A very compact LC-VCO with a stackedspiral inductor and the core-circuit being placed beneath the inductor is proposed. To reduce coupling, interconnections are slit shaped and orthogonalized with the coil trace. This VCO achieves a chip area of 484µm equaling ring-oscillator and FoMA of 06dBc/Hz. 00/09/8 R.Murakami, Tokyo Tech
19 8 Thank you!! 00/09/8 R.Murakami, Tokyo Tech
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