Ping Gui, Member, IEEE, Peiqing Zhu, Wickham Chen, Student Member, IEEE, Dennis Wu, Sungyong Jung, Senior Member, IEEE

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1 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1 A TID Tolerant, Wide Band and Low Jitter Phase-Locked Loop in 0.25 m CMOS Silicon-on-Sapphire Technology Ping Gui, Member, IEEE, Peiqing Zhu, Wickham Chen, Student Member, IEEE, Dennis Wu, Sungyong Jung, Senior Member, IEEE Abstract This paper describes the design, analysis, and measurement results of a TID tolerant, wide band, and low jitter LCPLL in 0.25 m SOS CMOS technology. The PLL has a central frequency of 3.0 GHz and a bandwidth of 1.2 GHz. The measurement results after total irradiation of 100 Krad (Si) show that the LCPLL has superior TID tolerance compared to a self-biased ring oscillator based PLL. Index Terms PLL, LC-VCO, wide band, radiation tolerant, TID, self-biased PLL, tuning range, jitter, silicon-on-sapphire. P I. INTRODUCTION Phase-locked loops (PLLs) are widely used in many applications as frequency generators or part of clock data recovery circuits. Although there has been much research on radiation-tolerant PLL designs [1-8], most of the designs employ either ring configured voltage-controlled-oscillator (VCO) which has rather high phase noise, or inductor-capacitor (LC) based VCO which exhibits low phase noise but a very narrow bandwidth. In addition, there remains no report on the comparison of the radiation tolerance between these two PLL architectures. In this paper, we describe the design, analysis and measurement results of a TID tolerant, wide band, and low jitter LC-tank based PLL (LCPLL) using 0.25 m Silicon-on-Sapphire (SOS) CMOS technology (UltraCMOS ). A cross-coupled oscillator architecture is employed to achieve a very wide frequency range of 1.2 GHz with a central frequency of 3 GHz. For comparison purposes, we also designed a self-biased, ring oscillator based PLL [9] in the same technology. Both circuits were irradiated with a total dose of 100 Krad (Si) and the PLL characteristics such as operating frequency range and jitter were measured before and after irradiation. The comparison of the measurement results between the two designs shows that the wide band LCPLL is much more tolerant to TID effects compared to the self-biased ring oscillator based PLL. this paper we focus only on the TID tolerance of the circuits. The technology has a nominal supply voltage of 2.5 V, a gate oxide thickness of 6 nm, 3 metal layers and Local Oxidation of Silicon (LOCOS) device isolation. A test chip was designed and fabricated to characterize the TID tolerance of this technology. The test chip contained transistor test structures and was irradiated with a Co-60 gamma source up to about 100 Krad (Si) with 1.2 Krad/hr dose rate. Detailed TID results of the test chip were reported in [12]. Shown in Figure 1 are the measured I-V curves of the regular NMOS (RN) and PMOS (RP) transistors for both the pre-radiation and post-radiation cases. It was observed that, after irradiation, the I-V curves of RN devices shifted toward right with a 0.2 V increase in V tn whereas the I-V curves of RP devices shifted with a 0.17 V decrease in V tp. It was noticed that the amount of the increase in V tn and the decrease in V tp did not vary much with respect to transistor size. The RP devices experienced a 1 µa of leakage current during irradiation whereas the leakage current in NMOS was negligible. The leakage current vanished for both NMOS and PMOS after a 120-day annealing at room temperature, indicating that the leakage current would not be a problem in realistic dose rate. II. SILICON-ON-SAPPHIRE (SOS) CMOS TECHNOLOGY The SOS CMOS technology was selected for its SEE immunity due to the reduced silicon volume [10-11]; thus in Manuscript received July 17, P. Gui and W. Chen are with the Department of Electrical Engineering, Southern Methodist University, Dallas, TX USA (phone: ; fax: ; pgui@lyle.smu.edu). P. Zhu and D. Wu are with Texas Instruments, Dalas, TX USA. S. Jung is with the Department of Electrical Engineering, University of Texas at Arlington, USA. Figure 1. (a) The I-V curves of RN devices before and after irradiation. (b) The I-V curves of RP devices before and after irradiation.

2 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 2 To simulate the TID effects on the circuit level, the V tn and V tp in the transistors models are modified according to the above measurement. III. THE DESIGN OF WIDE BAND LCPLL An LCPLL typically has a very narrow frequency range due to the limited tuning range of the varactors. The very narrow frequency band presents a challenge in LCPLL design as it relies on precision of the process and very accurate modeling of the on-chip inductors; otherwise the PLL may not be able to achieve lock due to process variations or radiation-induced device parameter variations. A wide band PLL alleviates this problem thus making the design more robust to process or radiation-induced variations. In addition, a wide frequency range can provide ample flexibility in frequency generations for a variety of applications. In the proposed wide band LCPLL, a cross-coupled VCO architecture [11] is adopted where two identical oscillators and two cross-coupled circuits are employed to provide a wide tuning range. Figure 2 shows the block diagram of the LC-VCO design. The design consists of two identical oscillators G 1 and G 2 plus two identical cross-coupled circuits M 1 and M 2, producing an output frequency based on both the resonant frequency of the individual oscillators ω 0 and the coupling coefficient m. The oscillation condition for the cross-coupled LC-VCO is given by [13]: Z jω 1 = ± tan 1 m (1) where Z jω 1 is the impedance at the output node of the LC-VCO, is the phase of the impedance Z, and ω 1 is the oscillating frequency. The outputs at nodes X and Y have the same amplitude and frequency, but with a phase difference of ± π 2. Vcont Y G 2 M 1 M 2 + G 1 Figure 2. Block diagram of the cross-coupled LC-VCO. The detailed schematic of the cross-coupled LC-VCO is shown in Figure 3, where the circuit blocks G 1, G 2, M 1 and M 2 are outlined. The differential output nodes labeled as (V out1, V out2 ), and (V out3, V out4 ) in the figure correspond to node X and Y in Figure 2. Based on (1), the overall oscillation frequency can be tuned from ω 0 to ω 1 by changing m through the control voltage V cont. The coupling coefficient m is defined as: m = m1 = m2, m1 = g m7 g m0 = g m8 g m1, (2) m2 = g m9 g m3 = g m10 g m2. (3) + Vcont X g m7,8, g m9,10, g m0,1, g m2,3 are transcondutance determined by the current provided by the tail current sources M 11 M 12, M 5, and M 6 respectively, which in turn are proportional to the control voltage (V gs V tn ) 2 of each tail source transistor. Thus we have m = W L 11 W L 5 V gs 11 V tn 11 V gs 5 V tn 5. (4) V gs11 in (4) is the same as the PLL control signal V cont, shown in Figure 3. Transistors M17, M18 and M4 generates V gs5 such that a large ratio of (V gs11 V tn 11 )/(V gs5 V tn 5 ) is achievable. Compared to the conventional LC-tanks that use varactors to tune the frequency range, this LC-VCO can achieve a much wider tuning range and thus a wide frequency tracking range for the PLL. M 1 8 V o u t 2 V o u t 1 V c o n t M 1 7 M 4 C a p M 8 M 1 1 M1 M 7 L 0 M 0 C v 0 L 1 M 1 Figure 3. Schematic of the cross-coupled LC-VCO. Table I lists the size of the devices used in the LC-VCO depicted in Figure 3. A tuning range of 1.2 GHz (40%) is achieved with a central frequency at 3.0 GHz. In addition, the LC passive components in the resonator results in low phase noise. A phase noise of 130 dbc/hz at 1 MHz offset from a central frequency of 3.0 GHz is realized in the VCO. The inductance value is chosen as 5.1 nh. It is designed using the top metal layer of 5.25 turns, a width of 12 m and spacing of 6m. TABLE I The Sizes (W/L) of Transistor Used in Figure 3. L0 L3 5.1 nh Cv0 Cv3 600 µm / 1 µm M0 M3 25 µm / 0.25 µm M4 1.2 µm / 1 µm M5 M6 40 µm / 0.25 µm M7 M µm / 0.25 µm M11 M µm / 0.25 µm M17 3 µm / 1 µm M µm / 1 µm M19 M µm / 0.25 µm V o u t 3 IV. ANALYSIS OF THE RADIATION EFFECTS ON PLL PERFORMANCE V o u t 4 In this section we analyze the TID effects on the PLL C v 1 M 9 M 1 2 M 1 0 M 2 L 2 C v 2 A B C D M 5 G 1 M 2 G 2 M 6 L 3 M 3 R c a p V c a p C v 3 M 1 9 M 2 0

3 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 3 performance such as frequency operating range and random jitter. A. Frequency Operating Range For a charge pump based PLL, the operating frequency range of the overall PLL is determined by the VCO tuning range. The proposed LC-VCO has a theoretical tuning range from ω 0 to ω 1 determined by the coupling coefficient m. Two attributes of the wide band LC-VCO design make its tuning range less susceptible to TID effects. First, ω 0 is determined by L (inductance) and C (capacitance) of the LC tank. Since L is made of metal layers in spiral squares, once it is implemented on the chip, its value will not be affected by TID. Second, from (4), the coupling coefficient m is proportional to (V gs11 V tn 11 )/(V gs5 V tn 5 ). Transistors M 5 and M 11 are of the same type NMOS devices. The TID effects on the coupling coefficient m are mitigated because the threshold voltage variation of V tn 11 and V tn 5 caused by TID are roughly the same. We can give an estimate as to the percentage change of the frequency operating range after the total irradiation of 100 Krad (Si). From Figure 3, notice I DS17 = I DS18 +I DS4, we have 1 μ W17 2 0C (V ox L17 dd V gs5 V tn 11 ) 2 = Figure 4 is the simulated tuning range for the pre-radiation and post-radiation cases in Cadence. The post-radiation cases were simulated using the modified transistor models. The simulated post-radiation results agree reasonably well with the analysis above and the measured post-radiation results (presented in section VI). B. Phase Noise Since TID only affects transistor characteristics, we focus on the thermal noise of the device. Among all the components, the VCO contributes the most to the total phase noise of the PLL. An LC-tank based PLL typically has much lower phase noise due to the reduced number of active devices in the oscillator stages, compared to PLLs using multi-stage ring VCO. The LCPLL phase noise for the pre-radiation and post-radiation cases were simulated as shown in Figure 5. The top curve in the figure represents the phase noise for the post-radiation scenario, with V tn increased by 0.2 V and V tp decreased by 0.2 V, whereas the bottom curve represents the pre-radiation case. As can be seen, the TID effects result in an increase in the phase noise of the LCPLL by about 2.5 db, from -130 dbc/hz to dbc/hz at 1 MHz offset. W18 L18 1 μ W C (V ox L18 cont V tn 18 ) μ W 4 2 0C (V ox L4 gs4 V tn 4 ) 2. (5) With V gs4 = V gs5 and further plugging in the value of W17 W4, and, we have L4 V gs5 = 1 3 (5V dd 5V tn 11 2V tn 4 + (6) L17, 6(V cont V tn 18 ) (V tn 11 V tn 4 ) V dd 2 20V dd V tn V dd V tn 11. Substituting (6) in (4) yields a simplified expression for m as a function of V cont. We can give an estimate of m /m, where m is the coupling coefficient after irradiation, if we consider a simplified model of the effect of the irradiation - that the threshold voltage V tn being increased by 0.2 V for NMOS devices, as described in section II. For this design where V cont is in the range from 1.0 V to 2.5 V, we found that m /m is within the range of [0.9, 1.1], which indicates that the LC-VCO would be able to keep about 90% of the tuning range after irradiation. Figure 5. Simulated phase noise of the LCPLL. For the self-biased PLL, the total noise in the VCO is mainly determined by the differential transistors, the symmetrical loads, and the tail current source. The VCO phase noise can be estimated by the following formula [14]: L min 8 KT 3 I V V g g m3 m5 0 f 2 tail gs tn I tail I tail f f 2. (7) A decrease in V tp will cause the second and the third terms to increase, due to the increased PMOS transconductance in the symmetrical load. An increase in V tn not only causes the first item in (10) to increase, but also reduces the current in the tail current source (M7 in Figure 5), which will further increase the total VCO phase noise according to equation (10). Figure 4. Simulated LCPLL output frequency vs. V control.

4 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 4 Figure 6. Simulated phase noise of the self-biased PLL with variation in the transistor threshold voltages. Figure 6 is the phase noise simulation that illustrates the effects of V tn and V tp variation on VCO phase noise. The bottom curve represents the case of pre-radiation. The top curve depicts the phase noise with V tn increased by 0.2 V and Vtp decreased by 0.2 V due to TID. Under this condition, the phase noise has increased by about 10 db from -90 dbc/hz to -80 The increase in phase noise is 7.5 db higher than that of the LCVCO. was measured and the VCO control voltage was monitored. The in-lab test results showed that the LCPLL has a tuning range from 2.2 GHz to 3.4 GHz, whereas the self-biased PLL has a tuning range from 0.6 GHz to 2.4 GHz. The RMS jitter was measured to be 1.8 ps for the LCPLL at 3 GHz and 4.2 ps for the self-biased PLL at 2 GHz. Figure 8 displays the jitter measurement on both PLLs. It is noted that an on-chip divide-by-2 circuit was added to lower the VCO output frequency to facilitate a direct measurement on the signal, thus we anticipate that the real jitter of the VCO should be better than the measured number. V. CHIP IMPLEMENTATION Both PLLs, one employing a cross-coupled wide-band LC-VCO and the other a self-biased architecture, were designed and implemented in the 0.25 µm SOS process. A three-state PFD, charge-pump and the high-performance current-mode-logic (CML) divider were used for both designs. The micrograph of the chip is shown in Figure 7. The LCPLL occupies 1280 µm x 1280 µm with on-chip inductors whereas the area of the self-biased PLL takes 690 µm x 530 µm. (a) (b) Figure 8. Measured jitter for (a) LC-PLL and (b) self-biased PLL. Fig. 7. The chip microphotograph. VI. MEASUREMENT RESULTS An in-lab test was conducted on the operating frequency range and jitter. The frequency of the input reference clock was swept from low to high while the corresponding VCO output Five test boards with the chips exposed were then irradiated at Brookhaven National Labs with a Co-60 gamma source with the chips powered on with 2.5 V power supply. The total dose was 100 Krad (Si) at the dose rate of 1.2 Krad/hr. The measurements were done right after the radiation. Both PLLs were able to achieve lock after irradiation. The changes on the locking time for both PLLs are negligible. The post-radiation results are summarized below. A. Frequency Range Measurements Figure 9 shows the measured LCPLL frequency range before and after the irradiation. As can be seen, the tuning range after irradiation stayed almost the same as in the pre-radiation case, roughly from 2 GHz to 3.2 GHz. This agrees with our analysis and simulation results. By contrast, the frequency range of the

5 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 5 self-biased ring based PLL had a large shift after the irradiation. The tuning range shifted from 600 MHz GHz to 1.25 GHz GHz as shown in Figure 10. B. Jitter Measurements The random jitter, which is the equivalent of the phase noise, of the LCPLL output clock was measured. Figure 11 depicts the RMS jitter of the output clock, before and after the irradiation. The LCPLL jitter was quite small, less than 2 ps both before and after irradiation at the center frequency of 3 GHz. In addition, the jitter measured from frequencies 2.6 GHz to 3.2 GHz remained almost the same after irradiation and went up by about 0.4 ps at relatively low frequency from 2.2 GHz to 2.6 GHz. In contrast, the self-biased PLL had higher jitter before irradiation and the TID further increased it, which is apparent in Figure 12. The small jitter change after irradiation in the LCPLL is mainly attributed to the LC-VCO whose passive components are insensitive to the TID effect. These results agree with the analysis and simulations on the phase noise described in Section IV. Figure 11. The measured jitter for LCPLL. VII. CONCLUSION A wide-band and low jitter LCPLL was designed in 0.25 m SOS CMOS technology for radiation-tolerant applications. The LCPLL has a random jitter of less than 2 ps and a wide frequency range of 2 GHz to 3.2 GH. The pre-radiation and post-radiation measurements show that the jitter and PLL frequency range are very insensitive to TID effects. A comparison between this LCPLL and a self-biased ring oscillator based PLL demonstrates the LCPLL s superior performance in terms of TID tolerance. Figure 12. The measured jitter for self-biased PLL. ACKNOWLEDGEMENT The authors would like to thank T. Liu, A.C. Xiang, D. Gong, J. Ye, and R. Stroynowski of SMU, and J. Kierstead, and F. Lanni of BNL for their help with the testing. Figure 9. The measured output frequency range for LCPLL. Figure 10. The measured output frequency range for self-biased PLL. REFERENCES [1] G. Lyons, G. Wu, T. Mellissinos, J. Cable, A High Performance Rad Hard 2-3GHz Integer N CMOS Phase Lock Loop, Radiation Effects Data Workshop, pp.41-45, [2] G. Cervelli, A. Marchioro, and P.Moreira, A 0.13um CMOS Serializer for Data and Trigger Optical Links in Particle Physics Experiments, IEEE Trans Nucl. Sci., vol. 51, no. 3, Jun [3] T. D. Loveless, L. W. Massengill, B. L. Bhuva, W. T. Holman, R. A. Reed, D. McMorrow, J. S. Melinger, and P. Jenkins, A Single-Event-Hardened Phase-Locked Loop Fabricated in 130 nm CMOS, IEEE Trans. Nucl. Sci., vol. 54, no. 6, Dec [4] W. Chen, V. Pouget, H. J. Barnaby, J. D. Cressler, G. Niu, P. Fouillat, Y. Deval, and D. Lewis, Investigation of Single-Event Transients in Voltage-Controlled Oscillators, IEEE Trans. Nucl. Sci., vol. 50, no. 6, pp , Dec [5] H. H. Chung, W. Chen, B. Bakkaloglu, H. J. Barnaby, B. Vermeire, and S. Kiaei, Analysis of Single Events Effects on Monolithic PLL Frequency Synthesizers, IEEE Trans. Nucl. Sci., vol. 53, no. 6, Dec [6] M. Vandepas, K. Ok, A.N. Nemmani, M. Brownlee, K. Mayaram, and U.-K. Moon, Characterization of 1.2 GHz Phase Locked Loops and Voltage Controlled Oscillators in a Total Dose Radiation Environment, Proceedings of 2005 MAPLD International Conference, Sept [7] A. Reed, D. McMorrow, J. S. Melinger, and P. Jenkins, A Single-Event-Hardened Phase-Locked Loop Fabricated in 130 nm CMOS, IEEE Trans. Nucl. Sci., vol. 54, no. 6, Dec

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