A 60GHz CMOS Power Amplifier Using Varactor Cross-Coupling Neutralization with Adaptive Bias
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1 A 6GHz CMOS Power Amplifier Using Varactor Cross-Coupling Neutralization with Adaptive Bias Ryo Minami,Kota Matsushita, Hiroki Asada, Kenichi Okada,and Akira Tokyo Institute of Technology, Japan
2 Outline Background Capacitor cross-coupling method Proposed varactor cross-coupling method Applied capacitor cross-coupling The optimal capacitance is designed by using adaptive bias Measurement result Power gain Power added efficiency (PAE) Power consumption Performance comparison Conclusion 1 211/12/7
3 Background 2 Advantage of 6GHz Enable communication distance is short. High speed wireless communication can be realized without lisence. IEEE c QPSK 3.5Gbps/ch 16QAM 7.Gbps/ch Gbps Wireless Communication Wireless Transmission of uncompressed HDTV
4 A 6GHz wireless transceiver[1], [2] 3 [1] K. Okada, et al., ISSCC 211 [2] A. Musa, et al., ASSCC 21 At 6GHz wireless communication High output power High efficiency
5 Transmission Line At 6GHz, the size of component is not negligible comparing the wavelength. lumped constant distributed constant transmission line is used. 4 AC inductance(1 [H]) inductance(1 [H]) DC capacitance(.999 [µf]) capacitance(.999 [µf]) The structure of TL. Model and photo.
6 MIM Transmission Line Z [Ohm] De-coupling use Modeling accuracy Avoiding self-resonance of parallel-plate capacitors Frequency [GHz] [3] T. Suzuki, et al., ISSCC 28 Measured Model MIM capacitor GND MIM TL GND MIM transmission line GND TL GND 5Ω transmission line & Okada 5Lab. 5
7 Parasitic capacitance between gate and drain 6 Parasitic Capacitance 3 C GD = CGD Im[ Y 12 ] jω Maximum available gain [db] 25 2 lower MAG W=4µm Frequency [GHz] Parasitic capacitances causes low reverse isolation and low gain.
8 Capacitor cross-coupling[3] 7 Vdd C x C x OUT OUT -C x -C x IN IN A cross-coupled capacitor between gate and drain of the opposite-side transistor works as negative capacitor. The reverse isolation is improved. [4] W. L. Chan, et al., ISSCC 29
9 Simulation result of CCC 8 Stablity factor w/ CCC w/o CCC Frequency [GHz] MAG, MSG [db] Frequency [GHz] w/ CCC w/o CCC Stability Factor is improved across entire frequency. The maximum available gain is improved about 2dB at 6GHz.
10 Simulation result of PAE Smaller C 9 1 PAE [%] Larger C Input power [dbm] The optimal capacitance is depended on the input power. Smaller input power Larger C than C x is better Larger input power Smaller C than C x is better Varactor is used as a cross coupled capacitor
11 Varactor cross coupling differential PA 1 TL MIM TL in+ adaptive bias Vdd V dd adaptive bias inout+ out- in V g V dd MIM TL out CMOS 65nm process Two-stage differential PA Low loss transmission line 1.2V power supply Adaptive bias circuit
12 Simulation result of varactor 11 Capacitance [ff] Varactor capacitance Adaptive bias Input power [dbm] Voltage [V] Optimal capacitance is realized by varying the bias of varactor using feedback of input power.
13 Die photo 12
14 Measurement result (small signal) S 11 [db] -6-8 S 22 [db] Sim. (old) Sim. (new) Meas Sim. (old) Sim. (new) Meas Frequency [GHz] Frequency [GHz] Sim.(old) shows the result of using old models. Sim.(new) shows the result of using update models. About 1GHz frequency error is generated between simulation and measurement. The accuracy of models were not good.
15 Measurement result (large signal) 14 Output power [dbm], Gain [db] Output power -5 Gain PAE Input power [dbm] Gain: 12.1dB P sat : 12.2dBm PAE at P 1dB : 7.7% P DC : 86mW Peak PAE: 12.5% V DD : 1.2V PAE [%]
16 Performance comparison ISSCC 28[5] ISSCC 29[4] Tech. Gain [db] P 1dB [dbm] P sat [dbm] PAE@P 1dB [dbm] Power [mw] V DD [V] 65nm nm ISSCC 21[6] ISSCC 21[7] ISSCC 211[8] 65nm nm nm This Work 65nm Very good PAE at P 1dB is realized. [4] W. L. Chan, et al., ISSCC 29 [5] D. Chowdhury, et al., ISSCC 28 [6] B. Martineau, et al., ISSCC 21 [7] J. Lai, et al., ISSCC 21 [8] J. Chen, et al., ISSCC 211
17 Conclusion 16 A 6GHz varactor cross coupled 2-stage differential power amplifier is implemented by using CMOS 65nm process. Very good power added efficiency (PAE) at 1-dB power compression point is realized in proposed CMOS power amplifier.
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