Introduction to CMOS RF Integrated Circuits Design

Transcription

1 VII. ower Amplifiers VII-1

2 Outline Functionality Figures of Merit A Design Classical Design (Class A, B, C) High-Efficiency Design (Class E, F) Matching Network Linearity T/R Switches VII-2

3 As and TRs Switching in Transceiver Matching Networks Z Rx Z BF T/R Switch Z A Tx VII-3

4 Functionality of As To Amplify and Deliver Required Signal ower to Antenna at Frequency of Interest To Achieve Desired Output ower with Maximum ower Efficiency To rovide Output Impedance Matching to Antenna To Have Clean Spectrum Not to Affect Receivers VII-4

5 Figures of Merit of As Frequency Output ower ower Efficiency Linearity (-1dB, II3, ACR) Conversion Gain Spur VII-5

6 Output ower o v 2 2 o, rms o, amp o, p R L v 2 R L v 8 R p L 2 For a Load of 50 Ohm, Need an Output Amplitude of 10 V to Achieve an Output ower of 1W! For a Low Supply, Need Small Load for Large Output ower, i.e. A 3.3-V Output Amplitude Can Only Deliver 1W to a Load of 5 Ohm! VII-6

7 Output ower Need an Output Impedance Matching to Convert 50 Ώ to a Smaller Load! As Supply and Load Decrease, A Would Need to Deliver Much Larger Current Loss Due to arasitic (R, L) Becomes Significant => Low Efficiency! 5 50 A IMN VII-7

8 ower Gain and Efficiency o A in o DC o AE DC in With a High ower Gain A, Drain Efficiency η is Approximately the Same as ower-added Efficiency AE VII-8

9 Linearity 1-dB Compression oint Intermodulation Intercept oint II3 Conventional Definition and Measurement Not Sufficient Because Most As Operate Near 1-dB Compression oint for Maximum Efficiency => Higher- Order Distortion Becomes Significant and Needs to Be Included => Adjacent-Channel ower Rejection ACR VII-9

10 Adjacent-Channel ower Rejection (ACR) A Modulated Signal is Applied to Include High-Order Distortion ACR is Defined and Measured as the ower of the Adjacent Channel Relative to the Carrier Output Spectrum ACR VII-10

11 Typical Figures of Merit Output ower ~ 0 35 dbm Efficiency ~ % Gain Linearity, IMD Linearity, ACR Spurs > 20 db - 30 dbc - 25 dbc < - 50 dbc Supply Voltage ~ 1.8 V Current > 300 ma VII-11

12 Linear ower Amplifiers Linear Relationship between Input and Output Signals Critical for Applications with Non-Constant Envelope Modulation Scheme Classical Linear As Include Class-A, Class-B, and Class C Classification is Made Based on Conduction Angle, Defined as the Fraction of eriod when Active Device is On Spectrum at output of nonlinear A Original Signal Spectrum VII-12

13 Non-Linear ower Amplifiers Constant envelop modulation Nonconstant envelop modulation GMSK FSK BSK QSK QAM Nonlinear A High Efficiency Linear A Low Efficiency VII-13

14 Conduction Angle o sin 1 cos( / 2 ) 1 o 4 sin( / DC sin 2 ) ( / 2 ) cos( / 2 ) Class A B C % 78% 100% REF: H. Kraus, et al, Solid State Radio Engineering, Wiley, 1980 VII-14

15 Conduction Angle REF: H. Kraus, et al, Solid State Radio Engineering, Wiley, 1980 VII-15

16 Class-A A ower Amplifiers V DD v IN θ v IN θ v D θ RFC i D θ v OUT θ i OUT θ v D θ V TH θ i D θ V DD v D θ V DD RFC i D θ v OUT θ i OUT θ v OUT θ θ 0 θ θ i OUT θ 0 θ VII-16

17 Class-A A ower Amplifiers Single Transistor as Amplifier to Minimize Loss and Maximize Efficiency Transistor Always Conducts => Conduction Angle is 360 Degrees Highest Linearity Lowest Efficiency VII-17

18 Class-A A ower Amplifiers RF Choke LC rovides Constant Bias Current Source While Doubling Output Voltage and Efficiency (as Compared to Resistive Load) Capacitor Cb Blocks DC Current from Flowing to the Output => No DC ower Consumption for the Load Resonant Tank Filters Harmonics Due to Non- Linearity to Obtain Single Tone at Output VII-18

19 Class-A A ower Amplifiers For Resistive Load, Maximum Output Voltage is Limited to V DD For Inductive Load, Maximum Output Voltage is Increased to 2V DD For Same Loading and Same Supply, Output ower is Increased By 4 Times and Efficiency is Increased By 2 Times For Same Loading and Same Output ower, Supply Can Be Reduced By 2 Times VII-19

20 Class-A A A with Resistive Load i d I B V DD /2 DC v o o t t t o,max DC max V I o,max o,max 2 V I DD B 4 V DD I D, ave V DD o,max 25 % DC I B VII-20

21 Class-A A A with Inductive Load V DD I B DC i d v o o t t t o,max DC max V I o,max o,max 2 V I DD B 2 V DD I D, ave V DD o,max 50 % DC I B VII-21

22 Class-B B ower Amplifiers v IN θ v D θ V DD i D2 θ v OUT θ i OUT θ v IN θ V T θ i D1 θ i D1 θ i D2 θ I η RFout DC Drain 2 Vom 2R 1 2 π 2π 0 I RFout DC 2 VDD 2R D 2I D 2 Vom sinθdθ π π R 2 Vom 2R π Vom π 2 Vom 4 VDD 4 VDD π R θ v OUT θ 0 θ i OUT θ 0 0 θ VII-22

23 Class-B B ower Amplifiers Two Transistors as ush-ull Amplifier Transistors Conduct Only HALF CYCLE => Conduction Angle is 180 Degrees Higher Efficiency Compared to Class-A Compromised Linearity Due to Speed Limitation of MOS, Two NMOS Can Be Used In arallel with Their Currents Combined By a Transformer VII-23

24 Class-B B ower Amplifier I o,max D, ave DC max V V R V DD o,max DD o,max DC L I 2 I D, ave o,max V DD 4 R 2 2 V DD R L 78 % 4 L VII-24

25 Class-C C ower Amplifiers V DD v IN θ v IN θ v D θ RFC i D θ v OUT θ i OUT θ V TH i D θ θ θ RFout sin 1 cos 2 v OUT θ i OUT θ η Drain RFout DC 1 4 sin sin 2 2 cos θ VII-25

26 Class-C C ower Amplifiers Transistor Conducts Much Less Than Half of Cycle => Conduction Angle is Close to Zero Degree Higher Efficiency Compared to Class-A and Class-B Much Degraded Linearity Lower Output ower VII-26

27 Non-Linear ower Amplifiers Operate Active Devices as Switches Instead of Amplifying Linear Devices Highly Non-Linear Highest Efficiency (~ 100%) Most Suitable for Applications with Constant-Envelope Modulation For Linear Applications, Need Linearization Techniques Includes Class-E, Class-F VII-27

28 Non-Linear ower Amplifiers In ractice, Efficiency is Limited to ~ 60% Due to: High Speed => Not Too Large Device Size => Finite Turn-On Resistance of the Switch Finite Turn-On Transition Times Low-Q Inductors => Off-Chip Inductors or Bond Wires For High Output ower, Device Stress is Critical VII-28

29 Class-E E ower Amplifiers V DD v IN θ v IN θ v D θ L 1 i D θ C 1 v OUT θ i OUT θ v D θ θ V DD Switch mode Approaching 100% efficiency i D θ θ v D θ L 1 C 1 v OUT θ i OUT θ v OUT θ 0 θ VII-29

30 Class-E E ower Amplifiers Operate Active Device as Switch To Minimize ower Loss and Maximize Efficiency (~ 100%) : Small Transition Times Between ON and OFF Small Voltage when Conducting Current Small Current when Sustaining Large Voltage Change of Voltage with Time is Close to Zero when Starting Conducting arasitic Capacitance of Device Can Be Conveniently Absorbed in Cd VII-30

31 Class-E E ower Amplifiers. v in i d v ds OFF ON OFF ON OFF t t t L r C R d opt V 2 DD o 2 V DD V DD o 4 2 VII-31

32 Class-F F ower Amplifiers v IN θ v D θ V DD RFC i D θ L 3 C 3 L1 C1 L 3 C 3 tuned to the 2nd or 3rd harmonics eak efficiency 88% for 3 rd harmonics peaking 85% for for 2 nd harmonics peaking. v OUT θ v D θ V DD i OUT θ v IN θ V TH i D θ θ v OUT θ 0 θ θ VII-32

33 Class-F F ower Amplifiers Employ Harmonics to Simulate a Square Waveform to Minimize Transition Times and thus to Reduce Loss A arallel Tank Lr3Cr3 is Included to Obtain a Third-Order Harmonic and to Add to the Fundamental to Approximate a Square Wave VII-33

34 Challenges for CMOS As Trade-Off Among All arameters Speed Device Size Current and Output ower Supply Voltage Loss and Efficiency Device Stress Low-Q On-Chip Inductors => Off-Chip Inductors or Bond Wires for Inductors in Resonant Tanks and Matching Network VII-34

35 Linearization Techniques Critical for Both High Efficiency and High Linearity Use Non-Linear ower Amplifiers (Class E and/or F) for High Efficiency Use Linearization Techniques to Improve Linearity: Feed-Forward Envelope Elimination and Restoration VII-35

36 Feed-Forward Forward Techniques A v x + v in - v o 1/A + A - v y VII-36

37 Feed-Forward Forward Techniques v o v x A v v y v x A v v in v v y A v v in A v v v in v A v v o v x A v v y A v v in VII-37

38 Feed-Forward Forward Techniques Open Loop Without Feedback => Unconditional Stability Limited Linearity Improvement Due to: Gain Mismatches hase Mismatches Errors of Subtractors Can Be Extended to Nested Feed-Forward Loops to Improve Linearity at A Cost of More Complexity VII-38

39 Envelope Elimination and Restoration (EER) Techniques Envelope Detector A v1 v x v in Limiter v y A V DD v o VII-39

40 Envelope Elimination and Restoration (EER) Techniques Decompose Input Signal into An Envelope and a hase- Modulated Signal, both of which are Amplified Separately and Recombined Constant-Envelope High-Frequency hase-modulated Component is Generated by Eliminating from Input s Envelope Using a Limiter and then Applied as Input to a High-Efficiency Switching A VII-40

41 Envelope Elimination and Restoration (EER) Techniques Non-Constant Low-Frequency Envelope Can Be Extracted by an Envelope Detector, Amplified by a Switching Supply Voltage, and then Recombined with RF hase- Modulated Component By Modulating the A s Supply Voltage Achieve Linearization without Sacrificing Efficiency VII-41

42 Envelope Elimination and Restoration (EER) Techniques Operating Frequencies of the Two aths are Quite Different Suffer from hase and Gain Mismatches => Limited Linearity Improvement ower Consumption Can Be High => ower Efficiency Can Be Degraded VII-42