A Dual-Step-Mixing ILFD using a Direct Injection Technique for High- Order Division Ratios in 60GHz Applications
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1 A Dual-Step-Mixing ILFD using a Direct Injection Technique for High- Order Division Ratios in 60GHz Applications Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, and Akira Matsuzawa Tokyo Institute of Technology, Japan 2014/3/18 IEICE General Conference 2014
2 Outline 1 Motivation Conventional ILFDs Proposed Dual-Step-Mixing ILFD using a Direct Injection Technique Performance Comparison Frequency Drift over PVT variations Integration with 20GHz PLL Conclusion
3 Background 2 9-GHz unlicensed bandwidth at 60 GHz Several Gbps wireless communication IEEE ad/WiGig IEEE c Wireless HD ECMA-387 ISO/IEC13156 [1]
4 Direct 60GHz Frequency Synthesizer 3 60GHz VCO Ref. Clock Phase/ Frequency Detector Charge Pump Low Pass Filter Digital Divider N M High speed frequency dividers Direct 60GHz VCO suffers from inferior phase noise due to Q of tank at 60GHz Power-hungry frequency divider is required
5 60GHz Frequency Synthesizers 4 Sub-harmonic injection REF PFD CP single-stage divide-by-4 ILFD 4 LPF 20GHz VCO 60GHz ILO 2 divide-by-2 CML divider consumes 15mW (40% of PLL) Digital Divider 2 2 [1] A. Musa, et al., JSSC GHz push-push VCO REF PFD CP single-stage divide-by-6 ILFD 6 LPF 30GHz VCO 60GHz Divide-by-3 ILFD + divider chain consumes more than 50% of PLL Digital Divider 2 3 [2] T. Tsukizawa, et al., ISSCC 2013
6 High-speed Ring ILFD chains 5 30GHz 15GHz 5GHz Large power 2 ILFD 3 ILFD Digital Dividers Locking range mismatch 30GHz 6 ILFD 5GHz Digital Dividers Narrow locking range 20-GHz PLL needs a divide-by-4 ILFD 30-GHz PLL needs a divide-by-6 ILFD A technique to increase locking range of high-orderdivision in ILFDs is necessary
7 Conventional Direct Mixing Ring ILFD 6 LPF f out f inj = Nf out Nonlinearity f out 2f out (N-1)f out f Divide by N directly in one step Injection signal is directly divide by N Low power consumption Narrow Locking range
8 Progressive Mixing Ring ILFD (I) 7 2f out LPF f out f inj =4f out Nonlinearity X2 Multi-step mixing mechanism divide-by-2 n operation, e.g., 2, and 4 Locking range is enhanced through the use of stronger harmonics [3] A. Musa, et al., A-SSCC 2011
9 Progressive Mixing Ring ILFD (II) 8 High division ratio ILFD by reusing higher harmonic in cascoded configuration f o 5GHz M1 M2 M3 M4 M5 M6 M7 M8 M T1 M T2 M T3 M T4 2f o 10GHz V bias V bias V bias V bias M T5 M INJ+ INJ- T6 4f o V bias V bias [3] A. Musa, et al., A-SSCC 2011 Tail Injection 20GHz
10 Free Run Frequency (GHz) Issues of Conventional PMILFD (I) 9 Large headroom Impractical for low voltage design For 1.2 V supply, higher than 8 division is hard to be achieved RF8 injection (For divide-by-8) 4 x NMOS 4 overdrive voltage required Sensitive to PVT due to PMOS tuning ±10% supply pushing leads to a drift of free running frequency GHz Difference Supply Voltage (V)
11 Injection Power (dbm) Issues of Conventional PMILFD (II) 10 Asymmetric Locking Range in+ in- V bias M1 injection M2 M T1 V bias out- out+ M T Pbias=0.44 Pbias=0.40 Pbias= Injection Frequency (GHz) Intrinsic free-running frequency of ILFD is sensitive to large injection signal
12 Dual-Step Mixing using Direct Injection 11 secondary LPF f out 2f out f inj primary 2f out 4f out f X2,X4,... Dual-step mixing mechanism for divide-by-4 and divide-by-6 operation
13 Proposed ILFD Configuration 12 0 o 45 o 90 o 135 o 180 o 225 o 270 o 315 o 2f 0 o 2f 90 o 2f 180 o 2f 270 o +INJ -INJ I core I core I core I core Dual-Step Mixing with Second Harmonic Direct Injection
14 4 th Harmonic Output 2 nd Harmonic Output Output Signal Divide-by-4 Operation 13 ~5GHz ~10GHz ~20GHz Locked State of Divide-by-4 operation
15 6 th Harmonic Output 2 nd Harmonic Output Output Signal Divide-by-6 Operation 14 ~5GHz ~10GHz ~30GHz Locked State of Divide-by-6 operation
16 Proposed Schematic 15 0 o 45 o 90 o 135 o 180 o 225 o 270 o 315 o I REF M inj1 M inj2 V bias VDD V bias Injection signal+ M1 M2 M3 M4 IN- f out 2f out f R Injection signal- +OUT- Secondary Mixer R IN+ 2f out 4f out f To even-harmonic enhanced node Schematic of the Proposed Dual-Step-Mixing ILFD using Even-Harmonic Direct Injection Technique
17 Output signals Chip Micrograph 16 42μm 0.33mm 48μm ILFD Core Differential Injection Technology 65nm CMOS Core area 0.002mm 2
18 Injection Power (dbm) Experimental Results for divide-by mW 4.2mW 3.6mW 3.0mW Injection Frequency (GHz) Required frequency range for the 60-GHz wireless standards
19 Divide-by-4 Performance Comparison 18 Features Div. Ratio Locking Range* (GHz) Locking Range* (%) Power (mw) FoM (%/mw) Area (mm 2 ) [4] Direct mixing [5] Direct mixing [6] Direct mixing [7] LC Direct mixing [8] CML + LC ILFD [9]* Progressive mixing This Evenharmonicenhanced FoM=(%Lock Range)/(mW Power) [4] A-SSCC 07 [5] RFIC 04 [6] ISSCC 06 [7] CICC 12 [8] MTT 11 [9] A-SSCC 11
20 Injection Power (dbm) Experimental Results for divide-by mW 5.1mW 4.2mW 3.8mW 3.6mW 3.0mW Injection Frequency (GHz) Required frequency range for the 60-GHz wireless standards
21 Divide-by-6 Performance Comparison 20 Features Div. Ratio Locking Range* (GHz) Locking Range* (%) Power (mw) FoM (%/mw) Area (mm 2 ) [4] Direct mixing [5] Direct mixing [6] Direct mixing [7] Direct mixing [8] Direct mixing [9] This Current reused ILFD Evenharmonicenhanced FoM = (%Lock Range)/(mW Power) [4] MTT 12 [5] ISSCC 09 [6] A-SSCC 11 [7] RFIC 04 [8] RFIC 05 [9] MTT 13
22 Measured Frequency (GHz) Measured Frequency (GHz) Measured Frequency (GHz) Frequency Drift over PVT variations Conventional Proposed Supply Voltage (V) /3/ Temperature ( C) Chip number
23 900um Integration with the 20GHz PLL 22 36MHz ref. 20GHz VCO 700um 2 PFD Charge Pump LPF (54,55,56, 57,58,59,60) 5 4 Proposed ILFD Proposed ILFD Proposed ILFD consumes only 4.2mW (Two cascading CML dividers consumes 14mW [1]) [1] K. Okada, et al., JSSC 2011
24 Phase noise (dbc/hz) Phase noise (dbc/hz) Phase noise (dbc/hz) Phase noise (dbc/hz) Experimental Results Channel 1-20 Channel K 100K 1M 10M Offset Frequency (Hz) Channel K 100K 1M 10M Offset Frequency (Hz) Channel /3/ K 100K 1M 10M Offset Frequency (Hz) K 100K 1M 10M Offset Frequency (Hz)
25 Conclusions 24 An Dual-Step-Mixing ILFD using a Even- Harmonic Direct Injection Technique is proposed for an enhanced locking range of divide-by-6 and divide-by-4 operations It achieves the widest locking range reported for divide-by-6 operation and comparable performance with the state-of-the-art divide-by- 4 ILFDs This work is suitable to be integrated in pushpush or sub-harmonic injection-locked 60GHz PLLs
26 Thank you for your interest 25
27 Acknowledgement 26 This work was partially supported by MIC, SCOPE, MEXT, STARC, Canon Foundation, and VDEC in collaboration with Cadence Design Systems, Inc., and Agilent Technologies Japan, Ltd.
28 High Speed Frequency Dividers 27 High speed frequency dividers and VCO are the most power hungry parts of modern high frequency PLLs. Static Frequency Dividers: Wide locking range Consume considerable power Conventionally only divides by 2 Injection Locked Frequency Dividers (ILFDs) Limited locking range Low power consumption Can divide by higher than GHz 10.2GHz CLK Data Q QB Coupling Coupling 5GHz (Freerun) 5.1GHz Injection Locked
29 Locked Spectrum for Divide-by-4 mode Output power (dbm) Free-Running Injection Locked Frequency (GHz) Injection frequency of 22GHz is applied
30 Locked Spectrum for Divide-by-6 mode Output power (dbm) Frequency (GHz) Free-running Injection Locked Injection frequency of 34GHz is applied
31 Dual-Step Mixing using Direct Injection 30 secondary LPF f out 2f out f inj primary 2f out 4f out f X2,X4,... Dual-step mixing mechanism for divide-by-4 and divide-by-6 operation
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