Digitally Assisted Wireless Transceivers and Synthesizers

Transcription

1 Digitally Assisted Wireless Transceivers and Synthesizers Kenichi Okada Tokyo Institute of Technology Symposia on VLSI Technology and Circuits

2 Outline Analog to Digital Digitization of Wireless TRX Digital Assistance Wireless Transceiver Frequency Synthesizer Future Analog Design Synthesizable Analog Slide 1

3 Analog to Digital Digitization Scalability Portability Analog Analog Digital Digital Digital Assistance Robustness Less redundancy Slide 2

4 Further Digitization Digitization Scalability Portability Analog Digital Digital Digital Massive Digital Assistance Robustness Less redundancy Slide 3

5 Case Study Partially replaced by pure digital-domain calculation (NOT time-domain analog processing) Filter: in AD-PLL, in wireless TX Equalizer: FIR in wireless, OFDM PLL: carrier and timing recovery in wireless RX Mixer: Low-IF transceiver Only analog-domain Oscillator: Clock generation Data converter: V-to-D, D-to-V, D-to-I, C-to-D,.. Analog amplifier: voltage-to-voltage Difficult for digitization Slide 4

6 History of Timing Recovery Analog Digital Analog recovery Digitally-assisted analog recovery Digital recovery analog processing timing recovery analog processing analog processing digital processing sampling clock digital processing timing recovery digital processing *F. Gardner, IEEE Trans. Comm timing recovery Slide 5

7 Analog Demodulator Costas-loop for BPSK 0 o 0/1 90 o loop filter timing recovery loop (carrier & phase) *H. Suzuki, et al., IEEE Trans. VT 1985 Slide 6

8 Digital Carrier and Timing Recovery Everything is implemented in digital domain. ADC timing recovery (phase) interpolation filter timing-recovered signal carrier recovery (freq.) rotation filter timing- & carrierrecovered signal NCO LF PD NCO LF PD *F. Gardner, IEEE Trans. Comm NCO: Number-Controlled Oscillator LF: Loop Filter PD: Phase Detector Slide 7

9 Recent Digital Transceiver Analog Digital RX VGA VGA ADC ADC RX filter Carrier & Timing Recovery Demapper FEC Decoder TX DAC DAC TX filter Mapper FEC Encoder Zero-IF Slide 8

10 RX Digital in Wireless Analog VGA VGA ADC ADC RX filter Digital Carrier & Timing Recovery Demapper FEC Decoder for transmitting bandwidth restriction TX DAC DAC TX filter Mapper FEC Encoder Slide 9

11 Digital Equalizers in Wireless Analog Adaptive RF&BB Digital equalizer RX VGA VGA ADC ADC RX filter Carrier & Timing Recovery Demapper FEC Decoder TX DAC DAC TX filter Mapper FEC Encoder RF&BB equalizer Slide 10

12 Digitization of IF Mixer Hetero-dyne RX Analog RF IF ADC Digital ADC Low-IF RX Analog Digital Very common for BT 1/f noise Overhead for ADC RF IF ADC Slide 11

13 Digitization Aim of This Talk Wireless transceiver is a good example of digitized analog circuit. (for hinting) Digital assistance Digital calibration/compensation is implemented in a system level to satisfy complicated requirements for wireless system. Mutual re-use of TX and RX for calibration Digitally-designed analog Toward Synthesizable Analog Circuit Slide 12

14 Outline Analog to Digital Digitization of Wireless TRX Digital Assistance Wireless Transceiver Frequency Synthesizer Future Analog Design Synthesizable Analog Slide 13

15 Impairments in Wireless Transceiver Mismatch in differential block DC offset in RX IIP2 in RX LO leakage in TX Mismatch btw I and Q blocks Image signal Analog filter BW () Non-linearity IMD in PA PVT variation Gain control Power control VCO LC tank ILFD/ILO Environmental variation TX-to-RX distance Fading Antenna reflection *A. Jerng, Digital Calibration for RF Transceivers, ISSCC 2012, Tutorial 9 Slide 14

16 Digital Equalizers Analog Adaptive RF&BB Digital equalizer RX TX VGA ADC Environmental VGAVariation ADC Fading by multi-path flat or frequency selective DAC DAC RX filter TX filter Carrier & Timing Recovery Demapper Mapper FEC Decoder FEC Encoder RF&BB equalizer Slide 15

17 Automatic Gain Control (AGC) Analog Digital RX VGA VGA ADC ADC RX filter Carrier & Timing Recovery Demapper FEC Decoder TX DAC Automatic Gain Control TX filter DC offset cancel Environmental Variation DAC Received signal strength Antenna reflection Mapper FEC Encoder Slide 16

18 I/Q Mismatch Analog Digital I VGA ADC RX Q I VGA phase mismatch ADC DAC Digital BB TX Q gain&phase mismatch DAC Slide 17

19 [dbm] Image Rejection Ratio (IMRR) e.g. ω BB = 10MHz Desired IMRR [db] LO leak Image ω LO ω BB ω LO ω LO + ω BB freq. [GHz] Slide 18

20 [dbm] Image for Modulated Sig. I/Q mismatch degrades SNR. Desired IMRR [db] Image ω LO ω BB ω LO ω LO + ω BB freq. [GHz] Slide 19

21 Phase Error [deg] Image Rejection Ratio (IMRR) Amplitude Error [db] IMRR Δg2 + Δθ 2 4 Δg: Amplitude error ratio Δθ: Phase error Target: 0.2dB, 1.0degree for IMRR of 35dB Slide 20

22 coupler TX IMRR Calibration TX I: 0 o Q: -90 o test signal Desired IM LO ω LO ω BB ω LO + ω BB freq. [GHz] Down-conversion is required. Detector can be used. (2 nd -order distortion) ω LO Slide 21

23 coupler TX IMRR Calibration TX Detector I: 0 o Q: -90 o test signal Desired Desired IM LO ω LO ω BB ω LO + ω BB freq. [GHz] 0 LO ω BB IM 2ω BB freq. [GHz] ω LO Slide 22

24 Detector v out = (A v in 2 ) RF (e.g. 5GHz) BB (e.g. 10MHz) Desired bias Desired LO IM LO IM ω LO ω BB ω LO ω LO + ω BB 0 ω BB 2ω BB Slide 23

25 I/Q Mismatch Calibration by Loop-back VGA ADC RX TX coupler Detector VGA ADC DAC DAC Digital BB TX filter I/Q Amplitude offset I/Q Phase offset Slide 24

26 I/Q Mismatch Calibration by Loop-back VGA ADC RX TX coupler Detector *Iason Vassiliou, et al., IEEE JSSC VGA ADC DAC DAC Digital BB DFT TX filter I/Q Amplitude offset I/Q Phase offset Slide 25

27 Gain [db] Frequency-Dependent I/Q Mismatch TX I DAC Q DAC Frequency [MHz] 5% cut-off mismatch causes a serious frequency-dependent I/Q mismatch. Slide 26

28 Phase [deg.] IMRR [db] Gain [db] Frequency-Dependent IMRR Gain/phase mismatch can be frequency-dependent. -20 BW % (-42.5dB) Freq. [MHz] 2.6% (-38.5dB) Freq. [MHz] Freq. [MHz] 5% cut-off frequency mismatch -37dB@1MHz, -27dB@10MHz Slide 27

29 Key Idea of Wireless Calibration Self-calibration with less additional blocks Reuse of TRX each other TX = Signal Generator for RX calibration RX = Spectrum Analyzer for TX calibration Slide 28

30 Overall Procedure of TRX Calibration 1. RX BB Calibration (using TX BB) I/Q gain mismatch cut-off mismatch (including VGA and ADC) 2. TX BB Calibration (using RX BB) I/Q gain mismatch cut-off mismatch 3. TX I/Q Calibration (using detector and RX BB) Impairments of mixer, LO, RF I/Q amps., etc compensated by digital BB 4. RX I/Q Calibration (using TX) Impairments of mixer, LO, RF I/Q amps., etc compensated by digital BB Slide 29

31 RX Filter Calibration (BB loopback) RX TX target VGA VGA ADC ADC DAC DAC Gain/Phase calculation Digital BB Test-tone generation VGA and ADC are also included in RX BB calibration. Slide 30

32 TX Filter Calibration (BB loopback) RX TX VGA VGA ADC ADC DAC DAC Digital BB gain/cut-off mismatch between I/Q paths are calibrated. target Gain/Phase calculation Test-tone generation Slide 31

33 RF Loop-Back Calibration for TX ADC is re-used for IM/LO calculation with DFT in BB. RX TX Detector *Iason Vassiliou, et al., IEEE JSSC VGA VGA target compensate ADC ADC DAC DAC IM/LO Calculation by DFT TX filter Test-tone generation Slide 32

34 RF Loop-Back Calibration for TX Desired HPF RX TX Desired LO IM 0 Detector LO *Iason Vassiliou, et al., IEEE JSSC IM VGA VGA target freq. [GHz] compensate ADC ADC DAC DAC IM/LO Calculation by DFT TX filter Test-tone generation Slide 33

35 RX RF Loop-Back Calibration for RX TX is used for a test-tone generator. target VGA VGA ADC ADC I/Q mismatch calculation TX ATT Desired DAC DAC TX filter Test-tone generation *Iason Vassiliou, et al., IEEE JSSC Slide 34

36 I/Q Gain/Phase Mismatch Calculation At least, a 10-bit ADC is required for a IMRR of 40dB. I Q t t I 2 + Q 2 RSSI AGC I 2 Q 2 Δg I Q Δθ/2 Modulated signal can be used. Background calibration *S. Lerstaveesin, et al., IEEE JSSC Slide 35

37 RF Loop-Back Calibration for RX target t RX VGA ADC I/Q mismatch calculation VGA ADC TX ATT Desired DAC DAC TX filter Test-tone generation t *Iason Vassiliou, et al., IEEE JSSC Slide 36

38 Calibration vs Compensation Frequency independent (RF) TX I/Q mismatch(rf) Digital compensation (BB TX filter) RX I/Q mismatch(rf) Digital compensation (BB RX filter) FDE/OFDM Frequency independent (BB) TX I/Q mismatch(bb) Digital compensation RX I/Q mismatch(bb) Digitally-calibrated analog (AGC) / Digital compensation Frequency dependent (BB) TX I/Q mismatch(bb) Digitally-calibrated analog RX I/Q mismatch(bb) Digitally-calibrated analog as a typical case / Digital compensation Slide 37

39 60GHz Transceiver Calibration One additional ADC is used for a fine resolution. VGA ADC RX VGA 5b 3.5GS/s ADC Detector 8b 1MS/s ADC Digital BB DAC TX DAC *T. Tsukizawa, et al., ISSCC 2013 Slide 38

40 Outline Analog to Digital Digitization of Wireless TRX Digital Assistance Wireless Transceiver Frequency Synthesizer Future Analog Design Synthesizable Analog Slide 39

41 Calibration in Frequency Synthesizer AFC for capacitor-bank in LC-VCO ILFD/ILO Calibration Linearity calibration/compensation Loop-BW, Quantization noise, FM/Polar-TX VCO: frequency voltage (varactor, C-bank) DCO: frequency code (C-bank, I-control) TDC: code delay (PVT, noise, layout, etc) (ADC: code voltage) (DAC: voltage code) (Amp: voltage voltage) AFC: Automatic Frequency Calibration ILFD: Injection-Locked Frequency Divider ILO: Injection-Locked Oscillator (Multiplier) Slide 40

42 ILFD Calibration Locked*/Free-run** frequency is used. 60GHz PLL *S. Pellerano, et al., ISSCC 2008 **T. Shima, et al., APMC 2011 ***W. Deng, et al., A-SSCC 2012 Slide 41

43 Summary of Transceiver Calibration Wireless transceiver is a big system. Historically, architecture-level digitization has been applied with system-level calibration and compensation for PVT and environmental variations. Re-use of counter-part block for calibration Slide 42

44 Outline Analog to Digital Digitization of Wireless TRX Digital Assistance Wireless Transceiver Frequency Synthesizer Future Analog Design Synthesizable Analog Slide 43

45 Issues of Analog Circuit Design Why is the simulated performance degraded? Imperfection caused by physical implementation PVT layout non-ideality mismatch isolation/coupling Compensated by digital assistance Slide 44

46 Layout Design Issues beyond 20nm Transistor matching cannot be expected any more. Double patterning Well proximity effect A B A B A B SA SB Larger Rd, Rs, Rg Fixed fin height (for FinFET) Self-heating No body effect LOD STI stress (LOD) Slide 45

47 Scaled CMOS Layout 65nm layout style 32nm layout style *M. Bohr, ISSCC 2009 Uni-directional features Uniform gate dimension Gridded layout Slide 46

48 Massive Digital Assistance PVT layout non-ideality mismatch isolation/coupling Compensated by digital assistance Delay and linearity in delay can be calibrated easily in time-domain analog circuits, e.g. AD-PLL. Slide 47

49 Further Analog Circuit Digitization Scalability Portability Analog Digital Digital Digital Massive Digital Assistance Robustness Less redundancy Slide 48

50 Outline Analog to Digital Digitization of Wireless TRX Digital Assistance Wireless Transceiver Frequency Synthesizer Future Analog Design Synthesizable Analog Slide 49

51 Synthesizable Analog Circuits HDL module PLL (CLK,, OUT) endmodule Digital design flow Commercial P&R tools GDS with a standard-cell library without any custom-designed cells without manual placement Slide 50

52 Analog Synthesis by Digital Tools Pure digital Logic Verilog RTL Digitally-designed Analog Verilog netlist (gate-level) DCO Logic Synt. Tool Logic Layout uncertainty Netlist P&R Tool *W. Deng, et al., ISSCC 2014 GDSII Slide 51

53 Issue: Layout Uncertainty Massive digital assistance can overcome the layout uncertainty issue. Ideal placement Actual placement Unbalanced loading No layout symmetry e.g., DCO &TDC linearity Slide 52

54 Synthesizable Analog Circuits only by standard cells Synthesizable PLL* Synthesizable DCO Synthesizable DAC Synthesizable TDC Synthesizable ADC** *W. Deng, et al., ISSCC 2014 **S. Weaver, et al., IEEE TCAS-I 204 Slide 53

55 Synthesizable ADC ADC architecture Comparator by NAND3 SNDR of 35.9dB, 210MS/s Gaussian offset distribution Linearity compensation by inverse Gaussian *S. Weaver, et al., IEEE TCAS-I 2014 Slide 54

56 Synthesizable DCO MUX and varactor* Phase-Interpolator**, I-DAC***, and fine varactor*** *D. Sheng, et al., IEEE TCAS-II 2007 **A. Matsumoto, et al., JSSC 2008 ***W. Deng, et al., ISSCC 2014 Slide 55

57 Only standard cell Synthesizable DAC D 0 = 0 D 0 = 1 V out = 1V V out = 0V D 0 D 1 = 11 V out = 0V D 0 D 1 = 10 V out = 0.5V D 0 D 1 = 01 V out = 0.5V D 0 D 1 = 00 V out = 1V Slide 56

58 Synthesizable I-linear DAC Only standard cell Current-starving RO D 0 1 by NAND2 D D I out D 3 8 *W. Deng, et al., ISSCC 2014 Slide 57

59 Current[mA] Frequency[GHz] V-linear DAC vs I-linear DAC 0.24 Current-starving RO by NAND Control Code Control Code Slide 58

60 Stdcell Varactor V in *P. L. Chen, et al., TCAS II 2005 Slide 59

61 Performance B Performance Trade-off Custom design Custom design but easy Synthesizable design Performance A Slide 60

62 Performance B Performance Trade-off A synthesis-friendly Custom design architecture can improve Custom performances. design but easy Synthesizable design Synthesis-friendly architecture Performance A Slide 61

63 Injection-Locked PLL (IL-PLL) Conventional CP-PLL and TDC-PLL (AD-PLL) Phase lock: feedback Frequency lock: feedback Injection-Locked PLL (IL-PLL) Phase lock: feed-forward Frequency lock: feedback Injection-lock Counter *W. Deng, et al., ISSCC 2014 The fine timing feedback is not required. Synthesis-friendly Slide 62

64 Phase noise [dbc/hz] Injection-Locked PLL fref fout = N * fref Flicker of PNVCO & Ref noise Reference injection Noise folding PNVCO & phase lock +20log10(N) PNref 0.4*fref Offset Freq. [Hz] *S. Ye, et al., IEEE JSSC 2002 **N. D. Dalt, IEEE TCAS-II 2014 Slide 63

65 Synthesizable IL-PLL Phase lock Frequency tracking with very narrow BW *W. Deng, et al., ISSCC 2013 **A. Musa, et al., JSSC 2014 ***W. Deng, et al., ISSCC 2014 Slide 64

66 Gated Edge Injection Severe timing design is NOT required. Vx gating window (1) (3) gating window (2) Inj. edge Vy *W. Deng, et al., ISSCC 2014 **D. Park, et al., ISSCC 2012 Slide 65

67 Layout CMOS 65nm 110mm Area: mm 2 Jitter: 1.7ps PDC: 780mW FOM: db 60mm Slide 66

68 Comparison of the state-of-the-art PLLs *W. Deng, et al., ISSCC 2014 Slide 67

69 Comparison of Synthesizable PLL This work 65nm [22] 28nm [23] 65nm [24] 65nm Power [mw] Area [mm 2 ] Integ. Jitter [ps] 1.7 N.A. 30 N.A. RMS Jitter [ps] N.A FOM [db] * * W/ custom cells? No No Yes Yes Topology IL-base TDC-base TDC-base TDC-base *FOM is calculated based on RMS jitter. Slide 68

70 Conclusion Digitization vs Digitally-Assisted Analog Digitally-Assisted Analog to Digitally-Designed Analog e.g. Synthesizable Analog Circuit portability, scalability, robustness,.. Slide 69

71 References [1] F. Gardner, "Interpolation in Digital Modems-Part I: Fundamentals," IEEE Trans. on Communications, Vol. 41, No. 3, pp , Mar [2] H. Suzuki, Y. Yamao, and H. Kikuchi, "A Single-Chip MSK Coherent Demodulator for Mobile Radio Transmission," IEEE Trans. on Vecular Technology, Vol. VT-34, No. 4, pp , Nov [3] A. Jerng, Digital Calibration for RF Transceivers, ISSCC 2012, Tutorial 9. [4] I. Vassiliou, et al., "A Digitally Calibrated GHz Transceiver for a Wireless LANs in 0.18μm CMOS," IEEE Journal of Solid-State Circuits, Vol. 38, No. 12, pp , Dec [5] S. Lerstaveesin, et al., "A Complex Image Rejection Circuit with Sign Detection Only," IEEE Journal of Solid-State Circuits, Vol. 41, No. 12, pp , Dec [6] T. Tsukizawa, et al., "A Fully Integrated 60GHz CMOS Transceiver Chipset Based on WiGig/IEEE802.11ad with Built-in Self-Calibration for Mobile Applications," ISSCC Dig. Tech. Papers, pp , Feb [7] S. Pellerano, R. Mukhopadhyay, A. Ravi, J. Laskar, and Y. Palaskas, "A 39.1-to- 41.6GHz DS Fractional-N Frequency Synthesizer in 90nm CMOS," ISSCC Dig. Tech. Papers, pp , Feb [8] T. Shima, J. Sato, K. Mizuno, K. Takinami, "A 60 GHz CMOS PLL Synthesizer Using a Wideband Injection-Locked Frequency Divider with Fast Calibration Technique," APMC, pp , Dec Slide 70

72 References [9] W. Deng, A. Musa, K. Okada, and A. Matsuzawa, "A 0.38mm 2, 10MHz-6.6GHz Quadrature Frequency Synthesizer Using Fractional-N Injection-Locked Technique," A-SSCC Dig. Tech. Papers, pp , Nov [10] M. Bohr, "The New Era of Scaling in an SoC World," ISSCC Dig. Tech. Papers, pp , Feb [11] W. Deng, A. Musa, T. Siriburanon, M. Miyahara, K. Okada, and A. Matsuzawa, "A mm μW Fully Synthesizable PLL with a Current Output DAC and an Interpolative-Phase Coupled Oscillator using Edge Injection Technique," ISSCC Dig. Tech. Papers, pp , Feb [12] S. Weaver, B. Hershberg, and Un-Ku Moon, "Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells," IEEE Transactions on Circuits and Systems-I, Vol. 61, No. 1, pp , Jan [13] P. M. Levine, and G. W. Roberts, A High-Resolution Flash Time-to-Digital Converter and Calibration Scheme, IEEE International Test Conference, pp , Oct [14] D. Sheng, et al., "An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications," IEEE Trans. Circuits and Systems-II, Vol. 54, No. 11, pp , Nov Slide 71

73 References [15] A. Matsumoto, S. Sakiyama, Y. Tokunaga, T. Morie, and S. Dosho, "A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System," IEEE Journal of Solid-State Circuits, Vol. 43, No. 4, pp , Apr [16] P. L. Chen, et al., "A Portable Digitally Controlled Oscillator Using Novel Varactors," IEEE Trans. Circuits and Systems-II, Vol. 52, No. 5, pp , May [17] S. Ye, L. Jansson, and I. Galton, "A Multiple-Crystal Interface PLL With VCO Realignment to Reduce Phase Noise," IEEE Journal of Solid-State Circuits, Vol. 37, No. 12, pp , Dec [18] N. D. Dalt, "An Analysis of Phase Noise in Realigned VCOs," IEEE Transactions on Circuits and Systems-II, Vol. 6, No. 3, pp , March [19] W. Deng, A. Musa, T. Siriburanon, M. Miyahara, K. Okada, and A. Matsuzawa, "A 0.022mm2 970μW Dual-Loop Injection-Locked PLL with -243dB FOM Using Synthesizable All-Digital PVT Calibration Circuits," ISSCC Dig. Tech. Papers, pp , Feb [20] A. Musa, W. Deng, T. Siriburanon, M. Miyahara, K. Okada, and A. Matsuzawa, "A Compact, Low Power and Low Jitter Dual-Loop Injection Locked PLL Using All- Digital PVT Calibration," IEEE Journal of Solid-State Circuits, Vol. 49, No. 1, pp , Jan Slide 72

74 References [21] D. Park, and S. Cho, "A 14.2mW 2.55-to-3GHz Cascaded PLL with Reference Injection, 800MHz Delta-Sigma modulator and 255fsrms Integrated Jitter in 0.13um CMOS," ISSCC Dig. Tech. Papers, pp , Feb [22] Y. Park, and D.D. Wentzloff, "An All-Digital PLL Synthesized from a Digital Standard Cell Library in 65nm CMOS," IEEE Custom Integrated Circuits Conf., Oct [23] W. Kim, et al., "A 0.032mm2 3.1mW Synthesized Pixel Clock Generator with 30psrms Integrated Jitter and 10-to-630MHz DCO Tuning Range," ISSCC Dig. Tech. Papers, pp , Feb [24] M. Faisal, and D.D. Wentzloff, "An Automatically Placed-and-Routed ADPLL for the MedRadio Band using PWM to Enhance DCO Resolution," IEEE Radio Frequency Integrated Circuits Symposium, pp , Jun Other example: [25] D. Kaczman, et al., "A Single-Chip 10-Band WCDMA/HSDPA 4-Band GSM/EDGE SAW-less CMOS Receiver With DigRF 3G Interface and +90 dbm IIP2, IEEE JSSC, Vol. 44, No. 3, pp , March Slide 73

75 Acknowledgement This work was partially supported by MIC, SCOPE, MEXT, STARC, and VDEC in collaboration with Cadence Design Systems, Inc., and Agilent Technologies Japan, Ltd. Slide 74

76 Appendix Slide 75

77 Up-conversion by cos(ω LO t) 1 j 0 e jω LOt 2 1 ω LO cos(ω BB t) = ejωbbt + e jω BBt 2 cos ω LO t = ejωlot + e jω LOt 2 e jω LOt 2 ω LO j 0 cos(ω BB t) cos(ω LO t) ω LO Slide 76

78 Up-conversion by sin(ω LO t) 1 je jω j 0 LOt 2 ω LO 1 ω LO sin(ω BB t) = jejωbbt + je jω BBt 2 sin ω LO t = jejωlot + je jω LOt 2 je jω LOt 2 j 0 sin(ω BB t) sin(ω LO t) ω LO Slide 77

79 Ideal I/Q Up-Conversion Image signals are canceled. I 0 Q 0-90 o TX image desired 0 desired 0 0 image Slide 78

80 I/Q Up-Conversion with Mismatch Image signals are NOT canceled. I Q 0-90 o +f 0 TX image desired 0 desired 0 0 image Slide 79

81 Calibration of Injection Lock Oscillator 10 Ref. Clock 3 3 PFD CP Gating Frac. ILFD 4 4 Div. Chain Div. Div. Div. Chain Chain Chain... 32/ / 127 Prog. Divider 2 2 Buffer 10 DAC 8:1 8:1 LFSR CLK IN 10 MASH Integ. N 7 Controller :1 4:1 Frequencyto-Digital Converter 2 Digital Logic Quadrature Output *W. Deng, et al., A-SSCC 2012 Slide 80

82 Stochastic TDC start stop D Q 0/1 Ideal condition (no noise, no PVT) 1 0 t0 tstart - tstop Slide 81

83 Stochastic TDC start stop D Q 0/1 (random) Noise & Process variation threshold distribution 1 0 t0 tstart - tstop Slide 82

84 start stop Stochastic TDC D Q D Q D Q D Q potentially synthesizable + Linearity compensation is not very difficult. 0 ~ n 1 Output code *P. M. Levine, et al., IEEE ITC 2004 t0 5 0 tstart - tstop Slide 83

85 Pulse Injection Free-running Injection Pulse Injection locked Severe timing design is required on the injection pulse width. *B. Helal, et al., JSSC 2009 Slide 84

86 Phase Noise [dbc/hz] 0-40 Measured Phase Noise Frequency: 900MHz Integrating Jitter: 1.7ps PDC: 780mW k 100k 1M 10M Offset Frequency[Hz] Slide 85

87 Cmedium [ff] Simulated C medium against V in Miller effect DM=1 4 NMOS PMOS+offset DM=0 offset Vin [V] Slide 86

88 Fine Varactor Miller effect is gain-dependent. A transient variation of VOUT can make a fine capacitance difference in CIN. t *W. Deng, et al., ISSCC 2014 Slide 87

89 V in [V] V in [V] Fine Varactor (cont.) V in V in V DD V DD D M =0 4.8ps D M =1 D F =1 0.4ps (0.066ps 6) D F = Time[ps] Time[ps] *W. Deng, et al., ISSCC 2014 Slide 88

90 60mm 70mm Robust for Layout Uncertainty Integrating Jitter: 1.7ps PDC: 780mW FOM: db 110 mm Integrating Jitter: 2.32ps PDC: 640mW FOM: db 130 mm DCO DCO DCO DCO Fully synthesized (proposed) Hierarchical P&R with synthesized DCOs (for comparison) Slide 89