A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder

Transcription

1 A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder Zhijie Chen, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology, Japan Matsuzawa & Okada Laḃ

2 Outline Motivation Traditional implementation Proposed architecture Circuit and Measurement Results Conclusion 2

3 Outline Motivation Traditional implementation Proposed architecture Circuit and Measurement Results Conclusion 3

4 Motivation A sigma delta modulator (SDM) architecture: X - Noise shaping Integrators DAC Quantizer Y Noise shaping for achieving high resolution Usually, 1 opamp integrator Most of power comes from opamp Target: how to reduce power? Reduce No. of opamp? PSD [db] PSD of Sigma-Delta Modulator Bandwidth Order of Noise Shaping Over-sampling Rate Frequency [Hz] 4

5 Outline Motivation Traditional implementation Proposed architecture Circuit and Measurement Results Conclusion 5

6 Single-opamp third-order DAC2 First Integrator DAC1 V ip C 3 C 1i Ф 2c Ф 2c -z -1 C 2 A V OP Analog: 1-Z -1 n-1 n n+1 Ф 1 Ф 2 Ф 1 Ф 2 Ф 1 Ф 2 Ф 1b Ф 2c Analog: 1 Analog: Z -1 DAC3 Feed-forward V OP C 3 C 5 C 4i Ф Ф 1b 1a Ф 1b DAC1 DAC2 DAC3 RDAC DAC1 Second Integrator Ф 1b Ф 1b 1 A. Pena-Perez, et al., JSSC

7 Opamp sharing and error feedback DAC2 First Integrator DAC1 V ip C 3 C 1i Ф 2c Ф 2c -z -1 C 2 A V OP Analog: 1-Z -1 n-1 n n+1 Ф 1 Ф 2 Ф 1 Ф 2 Ф 1 Ф 2 Ф 1b Ф 2c Analog: 1 Analog: Z -1 DAC3 Feed-forward V OP C 3 C 5 C 4i Ф Ф 1b 1a Ф 1b DAC1 DAC2 DAC3 RDAC DAC1 Second Integrator Ф 1b Ф 1b 1 Complex clock gen. RDAC, extra power 7

8 Stability during non-overlapped time DAC2 First Integrator DAC1 V ip C 3 C 1i Ф 2c Ф 2c -z -1 X X C 2 A V OP V OP DAC3 Feed-forward C 4i C 3 C 5 X X Analog: 1-Z -1 n-1 n n+1 Ф 1 Ф 2 Ф 1 Ф 2 Ф 1 Ф 2 Ф 1b Ф 2c Non-overlapped Analog: 1 Analog: Z -1 Ф Ф 1b 1a Ф 1b Opamp :Open-loop state DAC1 Second Integrator Ф 1b Ф 1b 1 Unstable issue 3 rd order, stability? 8

9 Outline Motivation Traditional implementation Proposed architecture Circuit and Measurement Results Conclusion 9

10 Feed-forward architecture Architecture X A single opamp 1 st integrator 2 nd integrator - - Shaped Quantization Noise NTF(z)Q 5-bit FPNS SAR Q f Y DAC DWA = 0.8z -1 1-z -1 = 2z-1 1-z z NTF(z)= z -1 :passive addition 5-bit FPNS SAR ADC, embedded with 1 st order NS A single opamp is shared to realize 2 nd order NS A Passive adder to realize FF addition 10

11 1 st order FPNS SAR ADC Fully passive noise shaping (FPNS) SAR Ф S N-1 Ф NS1 Ф NS2 Ф NS3 X X Ф s C1 C2 C 1 =C 2 =C 3 C-DAC A single N opamp 1 st integrator 2 nd integrator - Ф NS1 + - Ф NS3 C 3 Ф NS2 - Z. Chen, et al., VLSIC 2015 Y DAC Shaped Quantization Noise NTF(z)Q 5-bit FPNS SAR Suppress non-ideal effects 1 st order NS Noise transfer function (NTF): Q 1-0.5z NTF(z)= z -1 f Y 11

12 A single-opamp 2 nd order NS An opamp sharing technique: X 1 st integrator 2 nd integrator - A single opamp C 4 & C 5 : 1 st integrator C 7 & C 8 : 2 nd integrator C 6 : Feed-forward Additional SC: Solve stability issue - Y First Integrator Y X C 4 Feed-forward V OP Y C 5 A C 6 C 8 C 7 Second Integrator V OP Additional SC Non-overlapped 12

13 A passive adder by capacitor: X A passive adder X N X P V OP Differential signal: Input: X P & X N ; Opamp output: V OP,P & V OP,N ; =V OP,P -X N =V OP,N -X P X P + V OP,P X N + V OP,N V OP,P V OP,P +X P =V OP,P -X N V OP,N V OP,N +X N =V OP,N -X P Passive, save power Z. Chen, et al., A-SSCC

14 Outline Motivation Traditional implementation Proposed architecture Circuit and Measurement Results Conclusion 14

15 The schematic First Integrator REFP REFN FP i & FN i & V ip C 4i C 5 A V OP V OP FP i & REFP Feed-forward C 7i FN i & REFN Second Integrator C 6 C 8 ANALOG 5-bit FPNS SAR ADC Thermometer Decoder DIGITAL DWA Additional SC Non-overlapped REFP V OP,P V OP,N Passive addition REFP X N X P REFN REFN FP i i=1,2,,30,31 FN i No RDAC, save power Only two non-overlapped clocks No stability issue (1-0.5z -1 )(1-z -1 ) 2 Y(z)=X(z)+ (1+0.5z -1 )(1+0.6z -2 ) 15

16 Current mirror opamp: I 0 VB The opamp CMFB AVDD M9 M8 M5 M5 V OP V ip M6 M7 M4 M3 M1 M1 M2 V in V ON M4 M3 B Gain gm 1Rout 1 gm 1 B GBW 2 C 1 B W / L W / L W / L W / L L [J. Roh, et al., JSSC 2008] AVSS Single stage, save power 16

17 Chip photo CMOS 65 nm, core area: mm : 1 st sample cap 2: 2 nd sample cap 3: Feed-forward cap DWA Opamp FPNS SAR ADC 4: 1 st int. cap 5: 2 nd int. cap 6: additional SC CLK µm µm 17

18 PSD (db) The measured PSD Analog power supply: 0.7 V; Digital power supply: 0.85 V Power Spectral Density Fin = 9.95 khz BW = 100 khz SNDR = db ENOB = bits OSR = 16 Fs = 3.2 MHz 60dB/Dec Frequency (Hz) SNDR (db) 70 Input 10kHz 60 Full scale = 1 V DR=78 db dbfs Input amplitude (dbfs) Peak SNDR: 74.9 db; DR: 78 db 18

19 Performance Comparison The fewer No. of opamp is, the lower power is. [1] A. Pena-Perez, et al., JSSC 2012 [4] C. Briseno-Vidrios, et al., VLSIC 2015 [5] T. Kim, et al., VLSIC

20 Outline Motivation Traditional implementation Proposed architecture Circuit and Measurement Results Conclusion 20

21 Conclusion A single-opamp third-order SDM is introduced 74.9 db SNDR, 3.2-MHz Fs, 50 fj/con.-step FoM W, 168 db FoM S An opamp is sharing to realize 2 nd order noise shaping Stability is improved Power efficiency is enhanced 21

22 Acknowledgement This work was partially supported by MIC, HUAWEI, Mentor Graphics for the use of the Analog FastSPICE(AFS) Platform, and VDEC in collaboration with Cadence Design Systems, Inc, Synopsys, Inc. 22

23 Thank you for your interest! Zhijie Chen, 23