How to turn an ADC into a DAC: A 110dB THD, 18mW DAC using sampling of the output and feedback to reduce distortion

Transcription

1 How to turn an ADC into a DAC: A 110dB THD, 18mW DAC using sampling of the output and feedback to reduce distortion Axel Thomsen, Design Manager Silicon Laboratories Inc. Austin, TX 1

2 Why this talk? A good example how architectural design avoids hard circuit design A good illustration of the power of feedback An example of understanding new challenges in a new architecture

3 This work was done by Axel Thomsen, Dan B. Kasha, Lei Wang and Wai L. Lee, at Industrial Products Division, Cirrus Logic Inc. Austin, TX 3

4 Outline Introduction Traditional Architecture Feedback Architecture Integrator 1 Output Sampling Issues Loop Stability Other Circuits Experimental Results Conclusion 4

5 Introduction: Motivation and Goals channel test of a highly integrated data-acquisition channel low distortion, low power: 110dB THD, 18mW, 114dB SNR in 400Hz sinusoidal signal source minimal number of external components noise-shaped single bit bitstream provided at 56kHz, digitally interpolated to 104kHz jitter tolerance minimize number of critical building blocks with architectural solution to reduce circuit design complexity leverage knowledge of designing low distortion ADCs 5

6 Traditional Architecture Vout time distortion from signal dependent settling waveforms switched capacitor continuous time D*Vref DAC + filter reconstruction and Qnoise filter buffer Vout all blocks and interfaces must exceed noise and distortion requirements! 6

7 ADC Integrator 1 Implementation Vin D*Vref - H(z) D + Vref Cref 1 1 Cref D D D D ADC data feedback Cint Cint Cin 1 1 Cin 1 1 antialias filter with external C + Raaf Vin - Caaf ADC signal input 7

8 Feedback Architecture Concept ADC: prior art shows good linearity, only 1 critical block Vin D*Vref - sampling H(z) D DAC: only 1 critical block, distortion sources attenuated inside loop. But loop is not purely discrete time! D*Vref - Vout H(z) discrete time settling distortion H(s) Vout continuous time sampling 8

9 Integrator 1 Implementation ADC data feedback becomes DAC data input + Vref Cref 1 1 Cref D D D D Cint Cint ADC signal input becomes DAC signal feedback 1 1 Cfb Cfb 1 1 Raa antialias filter with external C + Vout - Caa 9

10 Integrator 1 opamp cmfb cmfb Vout- Vin+ Vin- Vout+ Vb Vb Folded cascode opamp with gain boosting and power management Reference: Kasha, ESSCIRC 98 10

11 A fundamental distortion source Vout Verror signal dependent error when observed in continuous time time time error is a sequence of impulses perfectly settled value, does not reflect settling distortion - need for smoothing 11

12 Spectrum of Signal Dependent Settling Waveforms VERROR(ω) AAF aliasing fs *fs n*fs (n+1)*fs frequency Distortion images near fs similar in size to in-band harmonics Continuous time application sees only in-band harmonics Sampling will alias the distortion images into band Loop gain will attenuate aliased distortion, not continuous time distortion Anti-alias filter is needed 1

13 Antialias Filtering filter stages with 50kHz cutoff achieve >40dB attenuation at fs to allow -80dB THD from glitches doubles as reconstruction filter in the DAC Single stage OTA, non-inverting, into capacitive load D*Vref antialias filter Vout sampling 13

14 Circuits: Quantization noise filter filtering of quantization noise needed. Noise rises 4th order at 400 Hz 1 st order Qnoise attenuation stage Butterworth filter switched cap output observed in continuous time D*Vref Vout sampling 14

15 Circuit blocks for loop gain Need high loop gain for distortion attenuation, but cannot afford large UGBW because of quantization noise attenuation A cascade of 3 integrators provides high gain at low frequencies without requiring high UGBW D*Vref Vout sampling A resonator formed by two integrators in feedback - extra loop gain 15

16 Stability: multipath feedforward compensation Architecture is similar to delta-sigma modulator loop 3 integrators cause 70 degrees of phase lag Feed-forward paths create LHP zeros At UGBW phase lag is reduced to less than 180 o Conditionally stable system D*Vref feedforward paths Block F [Hz] I1 00 I 1000 I3 700 F res 160 LPF 6000 Vout References: Nyquist (1930), Eschauzier (1996 (KAP)), Thomsen (1998(VLSI Circ)) 16

17 Transfer Function of the switched cap section gain [db] vs. frequency [Hz] LHP zeros -18dB/oct -18dB/oct phase Vs frequency [Hz] 30 o PM w/o resonance with resonance

18 Output Circuits Output buffer preceding loop gain relaxes requirements Target THD < -70dB into 1K Ohm low power class AB implementation: 1.5mW UGBW: 1MHz 6B gain reduces swing of internal nodes 18

19 Output Circuits Output can be taken from buffer or from resampling network both should have the same linearity Resampling Sampling best done from large charge reservoir (only external C) passive AAF cuts high frequency noise from output stage before sampling 19

20 Complete DAC Architecture D*Vref Integrator Qnoise filter antialias filter AAF 1 buffer x Vout Vout' sampling AAF 0

21 Results: In-band spectrum 0 Amplitude [db] vs frequency [Hz] -40 THD = 110dB SNR = 114dB in 400Hz

22 Results: Out of band noise signal output at -40dBfs total noise less than.5mvrms

23 Results: Measured step response differential voltage [V] vs. time [s] dBfs: large overshoot due to low phase margin -8 0dBfs: demonstrates robustness of complex system 3

24 Results: Measured performance technology 0.6 µm DPTM CMOS area 3.6 mm power 18 mw at 5V THD 110 db into 1kΩ SNR in 400Hz 114 dbfs total output noise <-50dB differential output swing 5 Vpp input sampling frequency 104 khz max signal bandwidth 100 Hz 4

25 Chip photo output buffer Integrator1 Qnoise filter I3 I AAF filter 5

26 Conclusion Presented a low distortion, low power DAC in 0.6µm CMOS process A DAC architecture with only 1 critical circuit building block leveraged of ADC design knowledge Analysis of a fundamental distortion source at the discrete time to continuous time interface Presented design and stability analysis of a conditionally stable loop 6