NOISE IN SC CIRCUITS

Transcription

1 ECE37 Advanced Analog Circuits Lecture 0 NOISE IN SC CIRCUITS Richard Schreier richard.schreier@analog.com Trevor Caldwell trevor.caldwell@utoronto.ca Course Goals Deepen Understanding of CMOS analog circuit design through a top-down study of a modern analog system The lectures will focus on Delta-Sigma ADCs, but you may do your project on another analog system. Develop circuit insight through brief peeks at some nifty little circuits The circuit world is filled with many little gems that every competent designer ought to recognize. ECE37 0-

2 Date Lecture Ref Homework RS Introduction: MOD & MOD S&T -3, A Matlab MOD RS Example Design: Part S&T 9., J&M 0 Switch-level sim RS 3 Example Design: Part J&M 4, S&T B Q-level sim TC 4 Pipeline and SAR ADCs J&M,3 Pipeline DNL ISSCC No Lecture RS 5 Advanced S&T 4, 6.6, 9.4, B CTMOD; Proj Reading Week No Lecture RS 6 Comparator and Flash ADC J&M TC 7 SC Circuits Raz, J&M TC 8 Amplifier Design TC 9 Amplifier Design TC 0 Noise in SC Circuits S&T C RS Switching Regulator Project Presentations TC Matching & MM-Shaping Project Report ECE NLCOTD: Gain Booster CMFB Need CMFB for Gain Booster One option is to use standard CT CMFB (Lecture 9) Is there an easier way with less circuitry? B4 M M 9 B4 M 0 B3 M M 7 B3 M 8 IN EFF M M IN OUT M 5 B M 6 OUT B B M M B 3 4 M 3 M 4 ECE37 0-4

3 Highlights (i.e. What you will learn today). How to analyze noise in switched-capacitor circuits. Significance of switch noise vs. OTA noise Power efficient solution Impact of OTA architecture 3. Design example for modulator ECE Review Previous analysis of kt/c noise (ignoring OTA/opamp noise) Phase : kt/c noise (on each side) Phase : kt/c added to previous noise (on each side) Total Noise (input referred): kt/c Differentially: 4kT/C ECE37 0-6

4 Review SNR Total noise power: 4kT/C Signal power: / SNR: C /8kT SNR (single-ended) Total noise power: kt/c (sampling capacitor C ) Signal power: / (signal from - to ) SNR: C /4kT ECE Thermal Noise in OTAs Single-Ended Example Noise current from each transistor is Assume /3 I n 4kT g m ECE37 0-8

5 Thermal Noise in OTAs Single-Ended Example Thermal noise in single-ended OTA Assuming paths match, tail current source M 5 does not contribute noise to output 8kT PSD of noise voltage in M (and M ): g PSD of noise voltage in M 3 (and M 4 ): 8kTg 3g Total input referred noise from M -M 4 6kT g m3 6kT Sneq, nf 3gm gm 3gm Noise factor n f depends on architecture 3 m m3 m ECE OTA with capacitive feedback Analyze output noise in single-stage OTA Use capacitive feedback in the amplification / integration phase of a switched-capacitor circuit n,eq ECE37 0-0

6 OTA with capacitive feedback Transfer function of closed loop OTA Hs ( ) OUT G s/ neq, where the DC Gain and st -pole frequency are o G C / C o g C m O Load capacitance C O depends on the type of OTA for a single-stage, it is C L +C C /(C +C ), while for a two-stage, it is the compensation capacitor C C ECE37 0- OTA with capacitive feedback Integrate total noise at output S () f H( j f) df OUT 0 n, eq 6kT o n f G 3gm 4 4kT n f 3C Minimum output noise for = is O Not a function of g m since bandwidth is proportional to g m while PSD is inversely proportional to g m 4kT n 3C O f ECE37 0-

7 OTA with capacitive feedback Graphically Noise is effectively filtered by the equivalent brick wall response with a cut-off frequency of f o / Total noise at OUT is the integral of the noise within the brick wall filter (area is simply f o / x / ) ECE Sampled Thermal Noise What happens to noise once it gets sampled? Total noise power is the same Noise is aliased folded back from higher frequencies to lower frequencies PSD of the noise increases significantly OUT S O,S n,eq IN L ECE37 0-4

8 Sampled Thermal Noise o,s Aliased Noise out s o Same total area, but PSD is larger from 0 to f S / GSneq, OUT 4kT Sout () f nf 4 f / f / 3 C f / Low frequency PSD S S O S is increased by 3dB GS neq, fs fs ECE f Sampled Thermal Noise /f 3dB is the settling time of the system, while /f S is the settling period for a two-phase clock / f S ( N ) e f3 db ( N )ln fs PSD is increased by at least ( N )ln If N = 0 bits, PSD is increased by 7.6, or 8.8dB This is an inherent disadvantage of sampleddata compared to continuous-time systems But noise is reduced by oversampling ratio after digital filtering ECE37 0-6

9 Noise in a SC Integrator Using the parasitic-insensitive SC integrator Two phases to consider ) Sampling Phase Includes noise from both switches ) Integrating Phase Includes noise from both switches and OTA ECE Noise in a SC Integrator Phase : Sampling Ron ON ON Ron ON Ron C Noise PSD from two switches: Time constant of R-C filter: PSD of noise voltage across C 8kTRON SC () f ( f ) S () f 8kTR Ron R ON ECE C ON

10 Noise in a SC Integrator Phase : Sampling Integrated across entire spectrum, total noise power in C is 8kTRON kt C, sw 4 C Independent of R ON (PSD is proportional to R ON, bandwidth is inversely proportional to R ON ) After sampling, charge is trapped in C ECE Noise in a SC Integrator Phase : Integrating Two noise sources - switches and OTA Noise PSD from two switches: Noise PSD from OTA: SRon() f 8kTRON 6kT Svn, eq () f n 3g Noise voltage across C charges to Ron n,eq ECE m f

11 Noise in a SC Integrator What is the time-constant? IN Ron ON OUT C m L Analysis shows that Z For large R L, assume that Resulting time constant (R / g ) C ECE37 0- IN / sc g Z IN R R m g ON m L L m Noise in a SC Integrator Total noise power with both switches and OTA on integrating phase C, op S vn, eq m ON m () f 4 6kT nf 3g 4(R / g ) C 4kT nf 3 C ( x) C, sw SRon() f 4 8kTRON 4(R / g ) C ON kt x C ( x) m Introduced extra parameter x R ON g m ECE37 0-

12 Noise in a SC Integrator Total noise power on C from both phases C C, op C, sw C, sw 4kT nf kt x kt 3 C ( x) C ( x) C kt 4 nf /3 x C x Lowest possible noise achieved if x kt In this case, C C What was assumed to be the total noise was actually the least possible noise! ECE Noise Contributions Percentage noise contribution from switches and OTA (assume n f =.5) Noise Fraction (%) Switch OTA x=r ON g m ECE37 0-4

13 Noise Contributions When g m >> /R ON (x >> ) Switch dominates both bandwidth and noise Total noise power is minimized When g m << /R ON (x << ) OTA dominates both bandwidth and noise Power-efficient solution Minimize g m (and power) for a given settling time and noise kt 4 gm n f x 3 C Minimized for x=0 ECE Maximum Noise How much larger can the noise get? Depends on n f (table excludes cascode noise) Architecture Relative EFF s n f Maximum Noise (x=0) +db Telescopic/ Diff.Pair EFF, = EFF,n /.5 3. kt/c.76 Telescopic/ Diff.Pair EFF, = EFF,n kt/c.63 Folded Cascode EFF, = EFF,n / kt/c 3.36 Folded Cascode EFF, = EFF,n kt/c 5.0 ECE37 0-6

14 Separate Input Capacitors Using separate input caps increases noise Each additional input capacitor adds to the total noise Separate caps help reduce signal dependent disturbances in the DAC reference voltages I O DAC a kt 4 n /3 x C... f a C C x C ECE Differential vs. Single-Ended All previous calculations assumed single-ended operation For same settling time, g m, is the same, resulting in the same total power [0dB] Differential input signal is twice as large [gain 6dB] Differential operation has twice as many caps and therefore twice as much capacitor noise (assume same size per side C and C ) [lose ~.db for n f =.5, x=0 less for larger n f ] Net Improvement: ~4.8dB ECE37 0-8

15 Differential vs. Single-Ended Single-Ended Noise kt 4 nf /3 x C, se C x Differential Noise C, diff C, op C, sw C, sw 4kT nf kt x kt 3 C ( x) C ( x) C kt 4 nf /3 4x C x Relative Noise (for n f =.5, x=0) C, diff 4 nf /3 4x 4 4 n /3 x 3 C, se f ECE Noise in an Integrator What is the total output-referred noise in an integrator? Assume an integrator transfer function kz Hz ( ) ( k) ( ) z C where k and C A I C OUT O ECE

16 Noise in an Integrator Total output-referred noise PSD where and S () f S () f H() z S () f INT C OUT C 4 OUT kt 3C O n kt 4 nf /3 x C x f Since all noise sources are sampled, white PSDs x Sx fs / To find output-referred noise for a given OSR fs /( OSR) () ECE37 INT SINT f df Noise in a Modulator How do we find the total input-referred noise in a modulator? ) Find all thermal noise sources ) Find PSDs of the thermal noise sources 3) Find transfer functions from each noise source to the output 4) Using the transfer functions, integrate all PSDs from DC to the signal band edge f S /. OSR 5) Sum the noise powers to determine the total output thermal noise 6) Input noise = output noise (assuming STF is ~ in the signal band) ECE37 0-3

17 Noise in a Modulator Example: f S = 00MHz, T = 0ns, OSR = 3 SNR = 80dB (3-bit resolution) Input Signal Power = 0.5 (-6dB from ) Noise Budget: 75% thermal noise Total input referred thermal noise: 0.75 * 0 (43.4 ) ( 6 SNR)/0 TH IN OUT ECE Noise in a Modulator ) Find all thermal noise sources ni no kt 4 nfa /3 x A C A xa 4kT 3 C A OA n fa f f 3 n3 ECE37 Cf Cf Cf Cf 0-34 ni no kt 4 nfb /3 x B C B xb 4kT 3 C B OB kt C C kt ( ) n fb

18 Noise in a Modulator ) Find PSDs of the thermal noise sources For each of the mean square voltage sources, S x x f / S 3) Find transfer functions from each noise source to the output Assume ideal integrators z HA( z) HB( z) z STF( z) NTF( z) ( z ) Hz ( ) Hz ( ) ECE Noise in a Modulator 3) Find transfer functions from each noise source to the output From input of H A (z) to output NTF z H z H z NTF z i( ) ( ) ( ) ( ) Hz ( ) Hz ( ) z z Hz ( ) Hz ( ) From output of H A (z) to output NTFo ( z) H( z) NTF( z) Hz ( ) Hz ( ) Hz ( ) ( z )( z ) ECE

19 Noise in a Modulator 3) Find transfer functions from each noise source to the output From input of H B (z) to output NTFi ( z) H( z) NTF( z) Hz ( ) z ( z ) Hz ( ) Hz ( ) From output of H B (z) to output (equal to transfer function at input of summer to output) NTF ( ) ( ) ( ) o z NTF z z ECE Noise in a Modulator 3) Find transfer functions from each noise source to the output Most significant is NTF i 0 Signal Band Magnitude (db) NTF i NTF o NTF i NTF o ECE37 Normalized Frequency 0-38

20 Noise in a Modulator 4) Using the transfer functions, integrate all PSDs from DC to the signal band edge f S /. OSR Use MATLAB/Maple to solve the integrals fs /( OSR) ni Ni NTFi() f df f / S 0 ni 5fS fs sin fs / OSR OSR fs /( OSR) no o o fs / 0 N NTF () f df no 7fS fs 9fS sin cos sin fs / OSR OSR OSR OSR ECE Noise in a Modulator 4) Using the transfer functions, integrate all PSDs from DC to the signal band edge f S /. OSR ni fs fs Ni sin fs / OSR OSR N 3f f sin cos f OSR OSR OSR no n3 S S o S / 4f S sin OSR (Some simplifications can be made for large OSR) ECE

21 Noise in a Modulator 5) Sum the noise powers to determine the total output thermal noise Assume x A = x B = 0. and n fa = n fb =.5 TH.9kT kt.9kt C OSR C 3OSR C 3OSR 3 3 A A OA B 4 4 kt 8kT C 5OSR C 5OSR 5 5 B OB f With an OSR of 3, first term is most significant (assume A = B = /3) kt kt kt TH C A COA C B ECE Noise in a Modulator 6) Input noise = output noise (assuming STF is ~ in the signal band) kt 9. 0 (43.4 ) TH C A => C A = 00fF Assuming other capacitors are smaller than C A, then subsequent terms are insignificant and the approximation is valid If lower oversampling ratios are used, other terms may become more significant in the calculation ECE37 0-4

22 Noise in a Pipeline ADC Similar procedure to modulator, except transfer functions are much easier to compute Differences Input refer all noise sources Gain from each stage to the input is a scalar Noise from later stages will be more significant since typical stage gains are as low as Sample-and-Hold adds extra noise which is input referred with a gain of Entire noise power is added since the signal band is from 0 to f S / (OSR=) ECE Noise in a Pipeline ADC Example If each stage has a gain G, G, G N N no ni no ni3 non i ni G GG GG GN S/H stage noise will add directly to ni ECE

23 NLCOTD: Gain Booster CMFB ECE What You Learned Today. Noise analysis for switched-capacitor circuits. Contributions of both switch noise and OTA noise Finding a power efficient solution Significance of OTA architecture 3. modulator design example ECE

24 Some Project Guidelines General: ) Corners: Do not need to simulate ) Noise analysis: use calculations to size the capacitors, but use Cadence to find OTA noise 3) Clock Generator: don t need to design nonoverlapping clock generator, but buffer the ideal clocks and take into account the buffer size for power calculations (if you have other clock phases not just and you should indicate how you would generate these) 4) Biasing: Ideal voltage source for DD/SS and reference ladder edges; Ideally one current source from which all currents are derived (at least use only one current source per circuit block) ECE Some Project Guidelines Presentation: 5-0 minutes Slides ( title, content) Focus on major design issues and circuit blocks (what you consider the most important design decisions) Report We should be able to replicate your circuit with the information provided in the report Give transistor sizes, preferably annotated on figures Try to avoid Cadence schematics (if you use them, make them more readable without all the unnecessary annotations) ECE